Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1794

1

T4

4

T5

9

T9

18

auto[1]

550

1

T5

9

T8

3

T9

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1702

1

T4

3

T5

9

T8

1

auto[1]

642

1

T4

1

T5

9

T8

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1782

1

T4

3

T5

18

T8

2

auto[1]

562

1

T4

1

T8

1

T9

4

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1705

1

T4

2

T5

7

T9

2

auto[1]

639

1

T4

2

T5

11

T8

3

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2178

1

T4

2

T5

18

T8

3

auto[1]

166

1

T4

2

T50

2

T59

3

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2135

1

T4

4

T5

18

T8

3

auto[1]

209

1

T50

1

T13

13

T39

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2194

1

T4

4

T5

18

T8

3

auto[1]

150

1

T50

3

T10

4

T13

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2176

1

T4

4

T5

18

T8

3

auto[1]

168

1

T50

1

T59

5

T39

9

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2085

1

T4

4

T5

18

T8

3

auto[1]

259

1

T50

2

T10

4

T59

8

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1750

1

T4

2

T5

16

T8

2

auto[1]

594

1

T4

2

T5

2

T8

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	856	1			T5	11		T8	3		T9	16
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	51	1			T4	2		T97	7		T131	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	104	1			T114	4		T254	1		T247	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	27	1			T59	3		T255	4		T257	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	44	1			T39	5		T366	6		T367	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	24	1			T36	8		T257	1		T354	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	29	1			T59	5		T255	8		T354	6
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	45	1			T114	5		T256	14		T352	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	13	1			T13	1		T348	10		T368	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	14	1			T50	2		T10	4		T345	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	9	1			T369	5		T370	2		T371	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	15	1			T255	5		T372	3		T373	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	3	1			T50	1		T354	1		T374	1
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	1	1			T375	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	76	1			T13	6		T254	2		T369	6
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	12	1			T50	1		T13	3		T256	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	29	1			T82	6		T376	4		T81	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	8	1			T97	2		T369	3		T356	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	15	1			T39	4		T352	3		T360	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T360	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	12	1			T255	7		T348	2		T356	3
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	22	1			T114	2		T345	6		T245	4
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T349	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	5	1			T377	5		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	10	1			T342	8		T378	2		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	1	1			T379	1		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

68

1

T12

1

T151

4

T372

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

76

1

T342

8

T151

4

T352

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

50

1

T39

5

T259

7

T133

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

115

1

T5

9

T9

10

T13

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

75

1

T10

2

T263

7

T82

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

49

1

T159

1

T133

5

T369

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

38

1

T38

4

T312

2

T245

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

138

1

T59

5

T36

8

T97

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

60

1

T79

4

T38

4

T254

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T39

4

T366

6

T206

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

11

1

T380

1

T360

4

T197

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T255

4

T159

1

T355

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

22

1

T9

4

T254

1

T99

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

23

1

T4

1

T50

1

T13

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

12

1

T8

1

T263

1

T381

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

114

1

T50

1

T97

7

T92

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

71

1

T255

8

T382

5

T370

10

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T9

2

T13

1

T257

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T114

5

T255

5

T313

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

64

1

T50

2

T114

4

T256

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T8

2

T10

2

T256

7

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

53

1

T4

1

T381

2

T341

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

15

1

T5

2

T99

2

T372

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T79

6

T312

2

T269

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T367

1

T161

1

T102

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

59

1

T258

3

T133

2

T151

24

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T383

2

T357

9

T127

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

14

1

T59

3

T92

1

T263

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T384

1

T385

2

T200

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T258

1

T242

3

T385

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T161

1

T172

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded