Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T27

6

T11

28

T72

12

auto[1]

1042

1

T27

14

T11

32

T72

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T27

5

T11

16

T72

3

from_0to1

499

1

T27

6

T11

16

T72

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T27

6

T11

31

T72

14

auto[1]

1038

1

T27

14

T11

29

T72

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T27

11

T11

32

T72

7

auto[1]

1045

1

T27

9

T11

28

T72

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

78

1

T11

1

T72

1

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T11

2

T72

2

T75

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T11

2

T73

1

T64

1

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T11

3

T73

2

T70

2

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T11

2

T64

1

T148

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T11

1

T72

1

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T27

2

T11

1

T70

2

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T11

1

T73

1

T64

2

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T11

4

T70

1

T64

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T27

1

T11

1

T148

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T27

1

T11

3

T12

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T27

3

T12

1

T64

4

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T27

2

T11

2

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

52

1

T11

2

T72

2

T73

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T11

4

T12

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T27

2

T11

3

T12

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T27

9

T11

29

T72

8

auto[1]

1054

1

T27

11

T11

31

T72

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T27

7

T11

9

T72

6

from_0to1

496

1

T27

7

T11

8

T72

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T27

7

T11

29

T72

10

auto[1]

1060

1

T27

13

T11

31

T72

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T27

4

T11

37

T72

12

auto[1]

1030

1

T27

16

T11

23

T72

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T11

1

T12

1

T64

2

auto[0]

from_1to0

auto[0]

auto[1]

50

1

T11

1

T72

2

T70

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T73

3

T70

1

T64

3

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T27

2

T11

1

T12

2

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T11

2

T72

3

T73

2

auto[0]

from_0to1

auto[0]

auto[1]

71

1

T27

1

T12

1

T70

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T11

1

T72

1

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T27

3

T11

1

T12

1

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T27

1

T11

2

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T27

2

T11

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T11

2

T72

2

T64

1

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T27

2

T11

1

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T11

1

T72

2

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T27

1

T11

1

T12

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T27

1

T11

2

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T27

1

T64

4

T147

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1033

1

T27

11

T11

30

T72

13

auto[1]

1053

1

T27

9

T11

30

T72

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

505

1

T27

3

T11

16

T72

5

from_0to1

513

1

T27

2

T11

15

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1056

1

T27

8

T11

27

T72

10

auto[1]

1030

1

T27

12

T11

33

T72

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T27

8

T11

26

T72

10

auto[1]

1035

1

T27

12

T11

34

T72

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T11

3

T72

1

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

69

1

T11

2

T305

2

T158

2

auto[0]

from_1to0

auto[1]

auto[0]

49

1

T11

1

T72

1

T73

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T11

1

T72

1

T64

2

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T11

2

T72

2

T73

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T11

1

T72

1

T73

2

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T12

1

T70

2

T64

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T11

5

T70

1

T147

2

auto[1]

from_1to0

auto[0]

auto[0]

55

1

T11

2

T70

1

T147

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T11

1

T70

2

T64

3

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T27

2

T11

4

T72

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T27

1

T11

2

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T73

2

T70

1

T147

1

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T27

1

T11

3

T12

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T27

1

T11

2

T64

2

auto[1]

from_0to1

auto[1]

auto[1]

48

1

T11

2

T72

1

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T27

8

T11

31

T72

13

auto[1]

1017

1

T27

12

T11

29

T72

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T27

5

T11

17

T72

5

from_0to1

500

1

T27

5

T11

17

T72

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1007

1

T27

12

T11

30

T72

5

auto[1]

1079

1

T27

8

T11

30

T72

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1069

1

T27

16

T11

27

T72

10

auto[1]

1017

1

T27

4

T11

33

T72

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T73

1

T147

1

T75

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T27

1

T11

4

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T27

1

T11

1

T72

2

auto[0]

from_1to0

auto[1]

auto[1]

58

1

T11

4

T72

1

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T11

3

T72

1

T148

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T11

3

T72

1

T70

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T11

3

T72

3

T64

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T11

2

T73

1

T70

1

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T27

2

T70

1

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T11

2

T73

1

T147

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T11

2

T72

1

T73

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T27

1

T11

4

T72

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T27

3

T11

1

T73

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T11

2

T12

1

T64

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T27

2

T11

2

T72

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T11

1

T73

1

T147

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T27

12

T11

29

T72

12

auto[1]

1062

1

T27

8

T11

31

T72

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T27

4

T11

12

T72

6

from_0to1

497

1

T27

4

T11

13

T72

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1052

1

T27

8

T11

29

T72

15

auto[1]

1034

1

T27

12

T11

31

T72

5

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1026

1

T27

11

T11

28

T72

11

auto[1]

1060

1

T27

9

T11

32

T72

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T27

1

T11

1

T72

2

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T11

2

T12

1

T73

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T11

2

T72

1

T70

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T27

1

T11

1

T72

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T11

1

T12

1

T70

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T11

3

T72

2

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T27

2

T11

3

T73

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T70

1

T64

2

T148

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T11

2

T72

1

T70

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T12

1

T73

3

T64

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T11

2

T64

1

T148

1

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T27

2

T11

2

T70

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T11

2

T72

1

T70

3

auto[1]

from_0to1

auto[0]

auto[1]

54

1

T11

1

T72

2

T64

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T27

2

T11

3

T73

2

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T12

1

T147

1

T148

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1070

1

T27

8

T11

30

T72

13

auto[1]

1016

1

T27

12

T11

30

T72

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T27

6

T11

17

T72

7

from_0to1

503

1

T27

6

T11

17

T72

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T27

6

T11

36

T72

8

auto[1]

1036

1

T27

14

T11

24

T72

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1001

1

T27

10

T11

27

T72

11

auto[1]

1085

1

T27

10

T11

33

T72

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T11

3

T72

1

T12

2

auto[0]

from_1to0

auto[0]

auto[1]

57

1

T11

4

T64

2

T148

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T27

1

T11

2

T72

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T11

2

T72

1

T70

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T11

2

T72

2

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T11

2

T72

2

T12

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T72

3

T73

1

T70

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T27

2

T11

4

T72

1

auto[1]

from_1to0

auto[0]

auto[0]

51

1

T27

1

T11

3

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T27

1

T11

1

T73

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T11

1

T72

4

T70

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T27

3

T11

1

T12

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T27

1

T12

1

T64

3

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T11

5

T70

1

T64

3

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T27

1

T11

3

T64

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T27

2

T11

1

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T27

8

T11

29

T72

13

auto[1]

1027

1

T27

12

T11

31

T72

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

486

1

T27

4

T11

18

T72

4

from_0to1

486

1

T27

4

T11

18

T72

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T27

10

T11

34

T72

17

auto[1]

1022

1

T27

10

T11

26

T72

3

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T27

13

T11

29

T72

9

auto[1]

1051

1

T27

7

T11

31

T72

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T11

2

T72

1

T12

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T11

3

T72

2

T12

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T12

1

T70

1

T64

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T27

1

T11

3

T73

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T27

2

T11

1

T72

1

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T11

3

T72

1

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T11

1

T73

1

T64

4

auto[0]

from_0to1

auto[1]

auto[1]

78

1

T11

4

T12

2

T73

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T27

1

T11

3

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T11

5

T72

1

T73

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T27

2

T11

2

T70

2

auto[1]

from_1to0

auto[1]

auto[1]

49

1

T73

1

T70

1

T165

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T27

1

T11

3

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T27

1

T11

1

T64

2

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T11

4

T12

1

T70

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T11

1

T72

1

T73

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1064

1

T27

9

T11

30

T72

10

auto[1]

1022

1

T27

11

T11

30

T72

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T27

5

T11

10

T72

5

from_0to1

502

1

T27

6

T11

11

T72

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T27

11

T11

26

T72

10

auto[1]

1039

1

T27

9

T11

34

T72

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T27

7

T11

18

T72

10

auto[1]

1051

1

T27

13

T11

42

T72

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T27

1

T12

1

T73

2

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T27

1

T72

3

T12

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T12

1

T73

1

T148

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T27

1

T11

1

T72

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T11

1

T72

1

T12

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T27

2

T11

2

T73

1

auto[0]

from_0to1

auto[1]

auto[0]

76

1

T11

1

T72

1

T12

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T11

2

T73

1

T64

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T11

3

T70

1

T64

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T27

1

T11

1

T72

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T11

1

T73

1

T70

2

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T27

1

T11

4

T147

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T27

1

T72

1

T73

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T27

1

T11

1

T72

2

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T27

1

T11

3

T12

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T27

1

T11

1

T64

1