Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	154452	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

122396

1

T4

268

T5

289

T6

17

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143596	1			T4	229		T5	392		T6	22
values[0x0]	66346	1			T4	284		T5	73		T6	9
values[0x1]	66906	1			T4	274		T5	77		T6	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	125127	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

151721

1

T4

331

T5

343

T6

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1316	1			T5	6		T1	1		T107	1
valid_sources[0x01]	869	1			T5	4		T26	1		T29	4
valid_sources[0x02]	969	1			T5	4		T1	1		T26	1
valid_sources[0x03]	799	1			T17	2		T26	3		T29	2
valid_sources[0x04]	871	1			T29	5		T9	1		T30	1
valid_sources[0x05]	1053	1			T1	1		T26	4		T29	1
valid_sources[0x06]	955	1			T5	5		T26	1		T29	1
valid_sources[0x07]	809	1			T5	16		T6	2		T17	1
valid_sources[0x08]	1104	1			T5	2		T107	1		T29	3
valid_sources[0x09]	1745	1			T5	5		T3	2		T26	2
valid_sources[0x0a]	1095	1			T1	1		T26	1		T29	2
valid_sources[0x0b]	1241	1			T5	1		T26	3		T29	3
valid_sources[0x0c]	1119	1			T5	3		T17	1		T29	1
valid_sources[0x0d]	778	1			T26	3		T29	3		T30	2
valid_sources[0x0e]	1196	1			T6	1		T26	2		T29	1
valid_sources[0x0f]	1965	1			T15	13		T17	1		T26	1
valid_sources[0x10]	1084	1			T5	2		T30	2		T57	1
valid_sources[0x11]	1366	1			T5	4		T26	4		T29	1
valid_sources[0x12]	811	1			T5	4		T17	1		T29	2
valid_sources[0x13]	1064	1			T5	1		T1	1		T30	4
valid_sources[0x14]	1925	1			T26	1		T29	3		T27	1
valid_sources[0x15]	889	1			T5	6		T17	1		T29	2
valid_sources[0x16]	1235	1			T5	3		T26	1		T9	1
valid_sources[0x17]	2677	1			T26	3		T9	3		T30	2
valid_sources[0x18]	952	1			T5	6		T107	1		T29	1
valid_sources[0x19]	1466	1			T5	2		T29	3		T27	2
valid_sources[0x1a]	788	1			T5	10		T1	1		T115	2
valid_sources[0x1b]	1621	1			T26	1		T29	1		T9	3
valid_sources[0x1c]	1493	1			T5	3		T26	1		T29	3
valid_sources[0x1d]	947	1			T29	1		T27	1		T9	1
valid_sources[0x1e]	1339	1			T7	11		T115	1		T26	2
valid_sources[0x1f]	1166	1			T5	3		T7	5		T107	1
valid_sources[0x20]	1025	1			T5	4		T1	2		T26	3
valid_sources[0x21]	1010	1			T26	1		T29	1		T9	6
valid_sources[0x22]	958	1			T5	3		T1	1		T26	2
valid_sources[0x23]	898	1			T26	2		T29	1		T9	2
valid_sources[0x24]	752	1			T6	3		T107	1		T26	1
valid_sources[0x25]	792	1			T1	3		T26	3		T29	5
valid_sources[0x26]	997	1			T5	1		T26	1		T29	4
valid_sources[0x27]	1271	1			T5	2		T29	4		T9	1
valid_sources[0x28]	1060	1			T29	2		T27	1		T9	2
valid_sources[0x29]	1628	1			T26	3		T29	1		T27	1
valid_sources[0x2a]	922	1			T27	1		T9	1		T30	2
valid_sources[0x2b]	976	1			T5	2		T26	5		T30	1
valid_sources[0x2c]	991	1			T29	2		T27	1		T9	3
valid_sources[0x2d]	724	1			T5	7		T26	1		T29	3
valid_sources[0x2e]	1016	1			T27	1		T9	7		T30	5
valid_sources[0x2f]	868	1			T5	1		T26	1		T27	2
valid_sources[0x30]	999	1			T26	1		T29	4		T9	4
valid_sources[0x31]	1069	1			T5	1		T1	1		T26	2
valid_sources[0x32]	1127	1			T5	2		T26	2		T29	1
valid_sources[0x33]	773	1			T9	4		T57	1		T50	1
valid_sources[0x34]	1575	1			T5	1		T26	1		T29	5
valid_sources[0x35]	952	1			T26	1		T29	4		T27	3
valid_sources[0x36]	952	1			T26	2		T29	1		T9	2
valid_sources[0x37]	855	1			T26	3		T29	2		T9	2
valid_sources[0x38]	1712	1			T5	1		T3	5		T107	1
valid_sources[0x39]	898	1			T115	1		T26	2		T29	6
valid_sources[0x3a]	873	1			T5	6		T26	5		T29	1
valid_sources[0x3b]	823	1			T5	11		T26	3		T30	1
valid_sources[0x3c]	1084	1			T5	2		T26	2		T29	1
valid_sources[0x3d]	850	1			T6	3		T26	5		T29	1
valid_sources[0x3e]	1728	1			T5	17		T9	1		T30	3
valid_sources[0x3f]	804	1			T1	1		T26	1		T29	3
valid_sources[0x40]	1173	1			T107	1		T26	3		T29	1
valid_sources[0x41]	804	1			T29	3		T27	2		T30	2
valid_sources[0x42]	925	1			T26	2		T9	3		T30	2
valid_sources[0x43]	1186	1			T5	16		T26	1		T29	1
valid_sources[0x44]	967	1			T1	1		T26	1		T29	1
valid_sources[0x45]	803	1			T5	2		T1	2		T26	3
valid_sources[0x46]	1020	1			T5	4		T29	2		T9	4
valid_sources[0x47]	1117	1			T5	1		T26	1		T29	2
valid_sources[0x48]	997	1			T7	1		T26	1		T9	1
valid_sources[0x49]	845	1			T26	1		T29	2		T27	2
valid_sources[0x4a]	1471	1			T29	3		T30	2		T57	2
valid_sources[0x4b]	1617	1			T5	1		T26	1		T29	3
valid_sources[0x4c]	1073	1			T6	1		T1	1		T26	1
valid_sources[0x4d]	863	1			T26	1		T29	1		T30	2
valid_sources[0x4e]	1013	1			T5	11		T107	1		T26	7
valid_sources[0x4f]	991	1			T5	4		T26	1		T29	2
valid_sources[0x50]	849	1			T5	6		T29	2		T9	1
valid_sources[0x51]	1697	1			T5	2		T17	2		T26	1
valid_sources[0x52]	930	1			T26	6		T29	2		T27	2
valid_sources[0x53]	762	1			T5	9		T26	1		T9	3
valid_sources[0x54]	1820	1			T5	3		T26	2		T29	2
valid_sources[0x55]	893	1			T26	1		T29	2		T9	1
valid_sources[0x56]	1071	1			T5	2		T1	1		T26	2
valid_sources[0x57]	787	1			T26	1		T29	1		T9	2
valid_sources[0x58]	952	1			T5	1		T1	1		T26	2
valid_sources[0x59]	1728	1			T29	2		T27	2		T9	1
valid_sources[0x5a]	946	1			T5	3		T107	1		T26	2
valid_sources[0x5b]	754	1			T18	2		T26	4		T29	1
valid_sources[0x5c]	1110	1			T1	1		T26	1		T27	1
valid_sources[0x5d]	1044	1			T29	4		T9	1		T30	2
valid_sources[0x5e]	764	1			T5	3		T17	1		T26	1
valid_sources[0x5f]	1110	1			T5	2		T26	4		T29	1
valid_sources[0x60]	935	1			T5	1		T107	1		T26	3
valid_sources[0x61]	747	1			T6	2		T107	1		T26	1
valid_sources[0x62]	861	1			T1	1		T26	1		T29	1
valid_sources[0x63]	1588	1			T6	1		T51	16		T107	1
valid_sources[0x64]	908	1			T1	1		T17	1		T26	2
valid_sources[0x65]	780	1			T5	2		T3	3		T26	2
valid_sources[0x66]	995	1			T6	1		T29	3		T9	2
valid_sources[0x67]	865	1			T6	3		T26	1		T29	1
valid_sources[0x68]	809	1			T1	1		T26	2		T29	2
valid_sources[0x69]	829	1			T30	5		T57	2		T58	5
valid_sources[0x6a]	997	1			T5	2		T26	2		T27	1
valid_sources[0x6b]	1638	1			T5	6		T29	2		T58	2
valid_sources[0x6c]	825	1			T5	9		T26	1		T29	4
valid_sources[0x6d]	1024	1			T5	2		T26	2		T29	1
valid_sources[0x6e]	928	1			T5	2		T6	5		T29	1
valid_sources[0x6f]	967	1			T26	2		T29	1		T9	2
valid_sources[0x70]	844	1			T26	2		T29	1		T30	2
valid_sources[0x71]	1037	1			T5	2		T6	3		T26	2
valid_sources[0x72]	1633	1			T4	787		T26	1		T29	2
valid_sources[0x73]	930	1			T7	3		T26	3		T29	1
valid_sources[0x74]	848	1			T5	3		T29	2		T27	1
valid_sources[0x75]	1320	1			T6	1		T29	2		T57	1
valid_sources[0x76]	809	1			T26	3		T29	1		T27	1
valid_sources[0x77]	1235	1			T5	16		T26	1		T9	1
valid_sources[0x78]	1376	1			T2	10		T26	4		T29	3
valid_sources[0x79]	882	1			T5	7		T6	1		T26	1
valid_sources[0x7a]	1924	1			T26	2		T9	2		T30	2
valid_sources[0x7b]	956	1			T26	3		T29	4		T27	2
valid_sources[0x7c]	919	1			T3	4		T26	1		T9	5
valid_sources[0x7d]	950	1			T5	1		T26	1		T29	1
valid_sources[0x7e]	1666	1			T5	2		T26	1		T9	5
valid_sources[0x7f]	791	1			T26	1		T27	1		T9	1
valid_sources[0x80]	1051	1			T18	12		T29	2		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65769

1

T4

110

T5

215

T6

12

values[0x0]

all_enables

biggest_size

32848

1

T4

111

T5

37

T6

3

values[0x1]

all_enables

biggest_size

23779

1

T4

47

T5

37

T6

2