Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T17,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T17,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T17,T19,T20
1	0	Covered	T4,T5,T6
1	1	Covered	T17,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T20
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T17,T19,T20
0	1	Covered	T17,T19,T20
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T17,T19,T20
1	-	Covered	T17,T19,T20

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T17,T19,T20
DetectSt	168	Covered	T17,T19,T20
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T17,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T17,T19,T20
DebounceSt->IdleSt	163	Covered	T56,T28,T70
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T17,T19,T20
IdleSt->DebounceSt	148	Covered	T17,T19,T20
StableSt->IdleSt	206	Covered	T17,T19,T20

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T17,T19,T20
0	1	Covered	T17,T19,T20
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T17,T19,T20
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T17,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T17,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T28,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T17,T19,T20
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T17,T19,T20
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T17,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T17,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	291	0	0
CntIncr_A	7234767	303892	0	0
CntNoWrap_A	7234767	6576210	0	0
DetectStDropOut_A	7234767	0	0	0
DetectedOut_A	7234767	923	0	0
DetectedPulseOut_A	7234767	134	0	0
DisabledIdleSt_A	7234767	6265781	0	0
DisabledNoDetection_A	7234767	6268061	0	0
EnterDebounceSt_A	7234767	161	0	0
EnterDetectSt_A	7234767	134	0	0
EnterStableSt_A	7234767	134	0	0
PulseIsPulse_A	7234767	134	0	0
StayInStableSt	7234767	789	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	6841	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	133	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7234767	291
T3	781	0
T7	819	0
T17	37916	4
T18	427	0
T19	694	2
T20	729	4
T24	496	0
T28	0	3
T51	669	4
T52	721	2
T53	683	2
T54	0	2
T56	0	5
T91	0	4

CntIncr_A

Name	Attempts	Real Successes
Total	7234767	303892
T3	781	0
T7	819	0
T17	37916	37316
T18	427	0
T19	694	59
T20	729	96
T24	496	0
T28	0	87
T51	669	112
T52	721	11
T53	683	47
T54	0	32
T56	0	5516
T91	0	112

CntNoWrap_A

Name	Attempts	Real Successes
Total	7234767	6576210
T1	274961	274560
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37511
T18	427	26

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7234767	923
T3	781	0
T7	819	0
T17	37916	16
T18	427	0
T19	694	7
T20	729	10
T24	496	0
T28	0	4
T51	669	14
T52	721	8
T53	683	1
T54	0	12
T56	0	21
T91	0	13

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7234767	134
T3	781	0
T7	819	0
T17	37916	2
T18	427	0
T19	694	1
T20	729	2
T24	496	0
T28	0	1
T51	669	2
T52	721	1
T53	683	1
T54	0	1
T56	0	2
T91	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7234767	6265781
T1	274961	274560
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	101
T18	427	26

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7234767	6268061
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	102
T18	427	27

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7234767	161
T3	781	0
T7	819	0
T17	37916	2
T18	427	0
T19	694	1
T20	729	2
T24	496	0
T28	0	2
T51	669	2
T52	721	1
T53	683	1
T54	0	1
T56	0	3
T91	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7234767	134
T3	781	0
T7	819	0
T17	37916	2
T18	427	0
T19	694	1
T20	729	2
T24	496	0
T28	0	1
T51	669	2
T52	721	1
T53	683	1
T54	0	1
T56	0	2
T91	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	7234767	134
T3	781	0
T7	819	0
T17	37916	2
T18	427	0
T19	694	1
T20	729	2
T24	496	0
T28	0	1
T51	669	2
T52	721	1
T53	683	1
T54	0	1
T56	0	2
T91	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7234767	134
T3	781	0
T7	819	0
T17	37916	2
T18	427	0
T19	694	1
T20	729	2
T24	496	0
T28	0	1
T51	669	2
T52	721	1
T53	683	1
T54	0	1
T56	0	2
T91	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	7234767	789
T3	781	0
T7	819	0
T17	37916	14
T18	427	0
T19	694	6
T20	729	8
T24	496	0
T28	0	3
T51	669	12
T52	721	7
T53	683	0
T54	0	11
T56	0	19
T70	0	25
T91	0	11

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7234767	6841
T1	274961	6
T2	649	0
T3	0	1
T4	11702	31
T5	25273	12
T6	497	7
T14	408	0
T15	409	0
T16	425	2
T17	37916	3
T18	427	4
T19	0	3
T20	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7234767	6578836
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7234767	133
T3	781	0
T7	819	0
T17	37916	2
T18	427	0
T19	694	1
T20	729	2
T24	496	0
T28	0	1
T51	669	2
T52	721	1
T53	683	1
T54	0	1
T56	0	2
T91	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T62

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T62
0	1	Covered	T1,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T62
0	1	Unreachable
1	0	Covered	T1,T7,T62

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T12
DetectSt	168	Covered	T1,T7,T62
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T62

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T62
DebounceSt->IdleSt	163	Covered	T12,T99,T61
DetectSt->IdleSt	186	Covered	T1,T89,T90
DetectSt->StableSt	191	Covered	T1,T7,T62
IdleSt->DebounceSt	148	Covered	T1,T7,T12
StableSt->IdleSt	206	Covered	T1,T7,T62

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T62
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T62
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T99,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	1	-	-	Covered	T1,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T62
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T62
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T62
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	166	0	0
CntIncr_A	7234767	142404	0	0
CntNoWrap_A	7234767	6576335	0	0
DetectStDropOut_A	7234767	14	0	0
DetectedOut_A	7234767	100171	0	0
DetectedPulseOut_A	7234767	47	0	0
DisabledIdleSt_A	7234767	5637274	0	0
DisabledNoDetection_A	7234767	5639606	0	0
EnterDebounceSt_A	7234767	105	0	0
EnterDetectSt_A	7234767	61	0	0
EnterStableSt_A	7234767	47	0	0
PulseIsPulse_A	7234767	47	0	0
StayInStableSt	7234767	100124	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	6841	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_sticky_sva.StableStDropOut_A	7234767	121134	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7234767	166
T1	274961	6
T2	649	0
T3	781	0
T7	0	2
T12	0	4
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	2
T63	0	2
T64	0	2
T65	0	2
T66	0	2
T77	0	2
T78	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7234767	142404
T1	274961	137172
T2	649	0
T3	781	0
T7	0	32
T12	0	84
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	11
T63	0	51
T64	0	49
T65	0	91
T66	0	32
T77	0	45
T78	0	93

CntNoWrap_A

Name	Attempts	Real Successes
Total	7234767	6576335
T1	274961	274554
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7234767	14
T1	274961	1
T2	649	0
T3	781	0
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T89	0	1
T90	0	2
T120	0	1
T121	0	3
T122	0	4
T123	0	2

DetectedOut_A

Name	Attempts	Real Successes
Total	7234767	100171
T1	274961	91451
T2	649	0
T3	781	0
T7	0	8
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	63
T63	0	185
T64	0	248
T65	0	702
T66	0	116
T77	0	96
T78	0	229
T87	0	34

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7234767	47
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T78	0	1
T87	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7234767	5637274
T1	274961	45803
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7234767	5639606
T1	274961	45804
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7234767	105
T1	274961	3
T2	649	0
T3	781	0
T7	0	1
T12	0	4
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T78	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7234767	61
T1	274961	3
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T78	0	1
T87	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7234767	47
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T78	0	1
T87	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7234767	47
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	1
T63	0	1
T64	0	1
T65	0	1
T66	0	1
T77	0	1
T78	0	1
T87	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7234767	100124
T1	274961	91449
T2	649	0
T3	781	0
T7	0	7
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	62
T63	0	184
T64	0	247
T65	0	701
T66	0	115
T77	0	95
T78	0	228
T87	0	33

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7234767	6841
T1	274961	6
T2	649	0
T3	0	1
T4	11702	31
T5	25273	12
T6	497	7
T14	408	0
T15	409	0
T16	425	2
T17	37916	3
T18	427	4
T19	0	3
T20	0	3

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7234767	6578836
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7234767	121134
T1	274961	84
T2	649	0
T3	781	0
T7	0	148
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	451
T63	0	762
T64	0	374
T65	0	87
T66	0	294
T77	0	310
T78	0	127
T87	0	30

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T12,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T6,T1,T2
1	1	Covered	T1,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T64
0	1	Covered	T1,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T12,T64
0	1	Unreachable
1	0	Covered	T1,T12,T64

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T12
DetectSt	168	Covered	T1,T12,T64
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T12,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T12,T64
DebounceSt->IdleSt	163	Covered	T1,T7,T62
DetectSt->IdleSt	186	Covered	T1,T87,T88
DetectSt->StableSt	191	Covered	T1,T12,T64
IdleSt->DebounceSt	148	Covered	T1,T7,T12
StableSt->IdleSt	206	Covered	T1,T12,T64

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T64
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T12,T64
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T7,T62
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	1	-	-	Covered	T1,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T1,T12,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T12,T64
StableSt	-	-	-	-	-	-	0	Covered	T1,T12,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	164	0	0
CntIncr_A	7234767	318331	0	0
CntNoWrap_A	7234767	6576337	0	0
DetectStDropOut_A	7234767	12	0	0
DetectedOut_A	7234767	8719	0	0
DetectedPulseOut_A	7234767	39	0	0
DisabledIdleSt_A	7234767	5637274	0	0
DisabledNoDetection_A	7234767	5639606	0	0
EnterDebounceSt_A	7234767	113	0	0
EnterDetectSt_A	7234767	51	0	0
EnterStableSt_A	7234767	39	0	0
PulseIsPulse_A	7234767	39	0	0
StayInStableSt	7234767	8680	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_sticky_sva.StableStDropOut_A	7234767	469025	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7234767	164
T1	274961	7
T2	649	0
T3	781	0
T7	0	1
T12	0	2
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	4
T63	0	4
T64	0	2
T65	0	2
T66	0	2
T77	0	3
T78	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7234767	318331
T1	274961	204
T2	649	0
T3	781	0
T7	0	63
T12	0	40
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	220
T63	0	336
T64	0	81
T65	0	32
T66	0	98
T77	0	162
T78	0	174

CntNoWrap_A

Name	Attempts	Real Successes
Total	7234767	6576337
T1	274961	274553
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7234767	12
T1	274961	2
T2	649	0
T3	781	0
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T87	0	1
T88	0	1
T89	0	2
T104	0	2
T124	0	2
T125	0	1
T126	0	1

DetectedOut_A

Name	Attempts	Real Successes
Total	7234767	8719
T1	274961	53
T2	649	0
T3	781	0
T12	0	250
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T64	0	374
T65	0	131
T66	0	232
T83	0	47
T99	0	212
T116	0	159
T117	0	79
T118	0	231

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7234767	39
T1	274961	1
T2	649	0
T3	781	0
T12	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T64	0	1
T65	0	1
T66	0	1
T83	0	1
T99	0	1
T116	0	1
T117	0	1
T118	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7234767	5637274
T1	274961	45803
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7234767	5639606
T1	274961	45804
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7234767	113
T1	274961	4
T2	649	0
T3	781	0
T7	0	1
T12	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	4
T63	0	4
T64	0	1
T65	0	1
T66	0	1
T77	0	3
T78	0	2

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7234767	51
T1	274961	3
T2	649	0
T3	781	0
T12	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T64	0	1
T65	0	1
T66	0	1
T87	0	1
T99	0	1
T116	0	1
T117	0	1
T118	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7234767	39
T1	274961	1
T2	649	0
T3	781	0
T12	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T64	0	1
T65	0	1
T66	0	1
T83	0	1
T99	0	1
T116	0	1
T117	0	1
T118	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7234767	39
T1	274961	1
T2	649	0
T3	781	0
T12	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T64	0	1
T65	0	1
T66	0	1
T83	0	1
T99	0	1
T116	0	1
T117	0	1
T118	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7234767	8680
T1	274961	52
T2	649	0
T3	781	0
T12	0	249
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T64	0	373
T65	0	130
T66	0	231
T83	0	46
T99	0	211
T116	0	158
T117	0	78
T118	0	230

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7234767	6578836
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7234767	469025
T1	274961	91389
T2	649	0
T3	781	0
T12	0	257876
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T64	0	203
T65	0	703
T66	0	113
T83	0	436
T99	0	204
T116	0	595
T117	0	417
T118	0	385

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T7,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T7,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T63
0	1	Covered	T83,T84,T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T63
0	1	Unreachable
1	0	Covered	T1,T7,T63

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T12
DetectSt	168	Covered	T1,T7,T63
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T63
DebounceSt->IdleSt	163	Covered	T12,T62,T64
DetectSt->IdleSt	186	Covered	T83,T84,T85
DetectSt->StableSt	191	Covered	T1,T7,T63
IdleSt->DebounceSt	148	Covered	T1,T7,T12
StableSt->IdleSt	206	Covered	T1,T7,T63

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T12
0	1	Covered	T1,T7,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T63
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T62,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T12
DetectSt	-	-	-	-	1	-	-	Covered	T83,T84,T85
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T63
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	162	0	0
CntIncr_A	7234767	368571	0	0
CntNoWrap_A	7234767	6576339	0	0
DetectStDropOut_A	7234767	7	0	0
DetectedOut_A	7234767	16708	0	0
DetectedPulseOut_A	7234767	43	0	0
DisabledIdleSt_A	7234767	5637274	0	0
DisabledNoDetection_A	7234767	5639606	0	0
EnterDebounceSt_A	7234767	112	0	0
EnterDetectSt_A	7234767	50	0	0
EnterStableSt_A	7234767	43	0	0
PulseIsPulse_A	7234767	43	0	0
StayInStableSt	7234767	16665	0	0
gen_high_event_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_sticky_sva.StableStDropOut_A	7234767	548651	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7234767	162
T1	274961	4
T2	649	0
T3	781	0
T7	0	2
T12	0	4
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	4
T63	0	2
T64	0	5
T65	0	2
T66	0	3
T77	0	2
T78	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7234767	368571
T1	274961	46
T2	649	0
T3	781	0
T7	0	83
T12	0	258132
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	320
T63	0	98
T64	0	180
T65	0	16
T66	0	111
T77	0	82
T78	0	33

CntNoWrap_A

Name	Attempts	Real Successes
Total	7234767	6576339
T1	274961	274556
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7234767	7
T83	941	1
T84	0	1
T85	0	1
T86	1085	0
T88	1135	0
T104	0	1
T127	0	1
T128	0	2
T129	491	0
T130	124887	0
T131	16886	0
T132	411	0
T133	29447	0
T134	511	0
T135	786	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7234767	16708
T1	274961	172
T2	649	0
T3	781	0
T7	0	47
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T63	0	547
T65	0	86
T77	0	240
T78	0	46
T87	0	1
T99	0	81
T116	0	437
T117	0	378

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7234767	43
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T63	0	1
T65	0	1
T77	0	1
T78	0	1
T87	0	1
T99	0	1
T116	0	1
T117	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7234767	5637274
T1	274961	45803
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7234767	5639606
T1	274961	45804
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7234767	112
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T12	0	4
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T62	0	4
T63	0	1
T64	0	5
T65	0	1
T66	0	3
T77	0	1
T78	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7234767	50
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T63	0	1
T65	0	1
T77	0	1
T78	0	1
T87	0	1
T99	0	1
T116	0	1
T117	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7234767	43
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T63	0	1
T65	0	1
T77	0	1
T78	0	1
T87	0	1
T99	0	1
T116	0	1
T117	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7234767	43
T1	274961	2
T2	649	0
T3	781	0
T7	0	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T63	0	1
T65	0	1
T77	0	1
T78	0	1
T87	0	1
T99	0	1
T116	0	1
T117	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7234767	16665
T1	274961	170
T2	649	0
T3	781	0
T7	0	46
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T63	0	546
T65	0	85
T77	0	239
T78	0	45
T99	0	80
T116	0	436
T117	0	377
T118	0	257

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7234767	6578836
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7234767	6578836
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7234767	548651
T1	274961	228527
T2	649	0
T3	781	0
T7	0	65
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T63	0	365
T65	0	782
T77	0	141
T78	0	374
T87	0	30
T99	0	350
T116	0	285
T117	0	59

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T43,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T45,T43,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T43,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T45,T43,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T43,T49
0	1	Not Covered
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T43,T49
0	1	Covered	T45,T43,T48
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T43,T49
1	-	Covered	T45,T43,T48

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T45,T43,T49
DetectSt	168	Covered	T45,T43,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T45,T43,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T43,T49
DebounceSt->IdleSt	163	Covered	T136,T80
DetectSt->IdleSt	186	Covered	T61
DetectSt->StableSt	191	Covered	T45,T43,T49
IdleSt->DebounceSt	148	Covered	T45,T43,T49
StableSt->IdleSt	206	Covered	T45,T43,T48

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T43,T49
0	1	Covered	T45,T43,T49
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T45,T43,T49
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T43,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T43,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T136
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T43,T49
DetectSt	-	-	-	-	1	-	-	Covered	T61
DetectSt	-	-	-	-	0	1	-	Covered	T45,T43,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T43,T48
StableSt	-	-	-	-	-	-	0	Covered	T45,T43,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	74	0	0
CntIncr_A	7234767	3137	0	0
CntNoWrap_A	7234767	6576427	0	0
DetectStDropOut_A	7234767	0	0	0
DetectedOut_A	7234767	2455	0	0
DetectedPulseOut_A	7234767	35	0	0
DisabledIdleSt_A	7234767	6299761	0	0
DisabledNoDetection_A	7234767	6302042	0	0
EnterDebounceSt_A	7234767	38	0	0
EnterDetectSt_A	7234767	36	0	0
EnterStableSt_A	7234767	35	0	0
PulseIsPulse_A	7234767	35	0	0
StayInStableSt	7234767	2401	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	16	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7234767	74
T36	12454	0
T42	0	4
T43	0	4
T45	858	4
T47	526	0
T48	0	2
T49	0	2
T61	0	2
T63	1702	0
T70	67007	0
T86	0	2
T89	0	4
T93	402	0
T94	412	0
T96	4416	0
T136	0	3
T137	0	4
T138	423	0
T139	402	0

CntIncr_A

Name	Attempts	Real Successes
Total	7234767	3137
T36	12454	0
T42	0	124
T43	0	54
T45	858	102
T47	526	0
T48	0	93
T49	0	71
T61	0	46
T63	1702	0
T70	67007	0
T86	0	77
T89	0	110
T93	402	0
T94	412	0
T96	4416	0
T136	0	168
T137	0	26
T138	423	0
T139	402	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	7234767	6576427
T1	274961	274560
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	0	0	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7234767	2455
T36	12454	0
T42	0	175
T43	0	71
T45	858	154
T47	526	0
T48	0	221
T49	0	43
T63	1702	0
T70	67007	0
T86	0	243
T89	0	62
T93	402	0
T94	412	0
T96	4416	0
T136	0	129
T137	0	86
T138	423	0
T139	402	0
T140	0	57

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7234767	35
T36	12454	0
T42	0	2
T43	0	2
T45	858	2
T47	526	0
T48	0	1
T49	0	1
T63	1702	0
T70	67007	0
T86	0	1
T89	0	2
T93	402	0
T94	412	0
T96	4416	0
T136	0	1
T137	0	2
T138	423	0
T139	402	0
T140	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7234767	6299761
T1	274961	274560
T2	649	248
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7234767	6302042
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7234767	38
T36	12454	0
T42	0	2
T43	0	2
T45	858	2
T47	526	0
T48	0	1
T49	0	1
T61	0	1
T63	1702	0
T70	67007	0
T86	0	1
T89	0	2
T93	402	0
T94	412	0
T96	4416	0
T136	0	2
T137	0	2
T138	423	0
T139	402	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7234767	36
T36	12454	0
T42	0	2
T43	0	2
T45	858	2
T47	526	0
T48	0	1
T49	0	1
T61	0	1
T63	1702	0
T70	67007	0
T86	0	1
T89	0	2
T93	402	0
T94	412	0
T96	4416	0
T136	0	1
T137	0	2
T138	423	0
T139	402	0

EnterStableSt_A

Name	Attempts	Real Successes
Total	7234767	35
T36	12454	0
T42	0	2
T43	0	2
T45	858	2
T47	526	0
T48	0	1
T49	0	1
T63	1702	0
T70	67007	0
T86	0	1
T89	0	2
T93	402	0
T94	412	0
T96	4416	0
T136	0	1
T137	0	2
T138	423	0
T139	402	0
T140	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7234767	35
T36	12454	0
T42	0	2
T43	0	2
T45	858	2
T47	526	0
T48	0	1
T49	0	1
T63	1702	0
T70	67007	0
T86	0	1
T89	0	2
T93	402	0
T94	412	0
T96	4416	0
T136	0	1
T137	0	2
T138	423	0
T139	402	0
T140	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7234767	2401
T36	12454	0
T42	0	172
T43	0	68
T45	858	151
T47	526	0
T48	0	220
T49	0	41
T63	1702	0
T70	67007	0
T86	0	242
T89	0	60
T93	402	0
T94	412	0
T96	4416	0
T136	0	127
T137	0	83
T138	423	0
T139	402	0
T140	0	55

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	7234767	6578836
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7234767	16
T36	12454	0
T42	0	1
T43	0	1
T45	858	1
T47	526	0
T48	0	1
T63	1702	0
T70	67007	0
T86	0	1
T89	0	2
T93	402	0
T94	412	0
T96	4416	0
T137	0	1
T138	423	0
T139	402	0
T141	0	1
T142	0	1
T143	0	2

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T43
0	1	Covered	T47,T48
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T43
0	1	Covered	T43,T41,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T43
1	-	Covered	T43,T41,T46

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T47
DetectSt	168	Covered	T2,T3,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T47
DebounceSt->IdleSt	163	Covered	T49,T130,T144
DetectSt->IdleSt	186	Covered	T47,T48,T61
DetectSt->StableSt	191	Covered	T2,T3,T43
IdleSt->DebounceSt	148	Covered	T2,T3,T47
StableSt->IdleSt	206	Covered	T43,T41,T46

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00



	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ?

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T47
0	1	Covered	T2,T3,T47
0	0	Excluded	T4,T5,T6	VC_COV_UNR



	LineNo.	Expression
-1-:	99	(thresh_sel) ?

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T47
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T144,T100
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T47
DetectSt	-	-	-	-	1	-	-	Covered	T47,T48,T61
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T41,T46
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR



	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	167	0	0
CntIncr_A	7234767	247220	0	0
CntNoWrap_A	7234767	6576334	0	0
DetectStDropOut_A	7234767	2	0	0
DetectedOut_A	7234767	110663	0	0
DetectedPulseOut_A	7234767	78	0	0
DisabledIdleSt_A	7234767	5749005	0	0
DisabledNoDetection_A	7234767	5751272	0	0
EnterDebounceSt_A	7234767	88	0	0
EnterDetectSt_A	7234767	81	0	0
EnterStableSt_A	7234767	78	0	0
PulseIsPulse_A	7234767	78	0	0
StayInStableSt	7234767	110553	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	2643	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	46	0	0

CntClr_A

Name	Attempts	Real Successes
Total	7234767	167
T2	649	2
T3	781	2
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	2
T42	0	4
T43	0	4
T46	0	4
T47	0	2
T48	0	4
T49	0	1
T145	0	2

CntIncr_A

Name	Attempts	Real Successes
Total	7234767	247220
T2	649	73
T3	781	36
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	41
T42	0	124
T43	0	54
T46	0	116
T47	0	38
T48	0	186
T49	0	71
T145	0	23

CntNoWrap_A

Name	Attempts	Real Successes
Total	7234767	6576334
T1	274961	274560
T2	649	246
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DetectStDropOut_A

Name	Attempts	Real Successes
Total	7234767	2
T47	526	1
T48	0	1
T64	5296	0
T71	1295	0
T74	529	0
T92	35436	0
T97	21993	0
T146	443	0
T147	512	0
T148	503	0
T149	496	0

DetectedOut_A

Name	Attempts	Real Successes
Total	7234767	110663
T2	649	56
T3	781	42
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	82
T42	0	130
T43	0	79
T46	0	178
T48	0	43
T86	0	199
T145	0	72
T150	0	110

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	7234767	78
T2	649	1
T3	781	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	1
T42	0	2
T43	0	2
T46	0	2
T48	0	1
T86	0	2
T145	0	1
T150	0	1

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	7234767	5749005
T1	274961	274560
T2	649	4
T4	11702	11297
T5	25273	24817
T6	497	96
T14	408	7
T15	409	8
T16	425	24
T17	37916	37515
T18	427	26

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	7234767	5751272
T1	274961	274561
T2	649	4
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	7234767	88
T2	649	1
T3	781	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	1
T42	0	2
T43	0	2
T46	0	2
T47	0	1
T48	0	2
T49	0	1
T145	0	1

EnterDetectSt_A

Name	Attempts	Real Successes
Total	7234767	81
T2	649	1
T3	781	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	1
T42	0	2
T43	0	2
T46	0	2
T47	0	1
T48	0	2
T86	0	2
T145	0	1

EnterStableSt_A

Name	Attempts	Real Successes
Total	7234767	78
T2	649	1
T3	781	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	1
T42	0	2
T43	0	2
T46	0	2
T48	0	1
T86	0	2
T145	0	1
T150	0	1

PulseIsPulse_A

Name	Attempts	Real Successes
Total	7234767	78
T2	649	1
T3	781	1
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	1
T42	0	2
T43	0	2
T46	0	2
T48	0	1
T86	0	2
T145	0	1
T150	0	1

StayInStableSt

Name	Attempts	Real Successes
Total	7234767	110553
T2	649	54
T3	781	40
T14	408	0
T15	409	0
T16	425	0
T17	37916	0
T18	427	0
T19	694	0
T20	729	0
T24	496	0
T41	0	81
T42	0	128
T43	0	77
T46	0	175
T48	0	41
T86	0	196
T145	0	70
T150	0	109

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	7234767	2643
T1	274961	0
T2	649	1
T3	0	1
T6	497	5
T14	408	0
T15	409	0
T16	425	3
T17	37916	0
T18	427	2
T19	694	0
T20	729	0
T24	0	4
T25	0	3
T26	0	19
T27	0	4
T107	0	4

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	7234767	6578836
T1	274961	274561
T2	649	249
T4	11702	11299
T5	25273	24827
T6	497	97
T14	408	8
T15	409	9
T16	425	25
T17	37916	37516
T18	427	27

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	7234767	46
T41	0	1
T42	0	2
T43	709	2
T44	775	0
T46	0	1
T75	6848	0
T79	21359	0
T86	0	1
T89	0	2
T113	468	0
T114	14013	0
T137	0	2
T150	0	1
T151	0	2
T152	0	1
T153	885	0
T154	416	0
T155	404	0
T156	524	0

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr