Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T46,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T45,T46,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T46,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T45,T47,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T45,T46,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T40
0	1	Covered	T46,T157,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T40
1	-	Covered	T46,T157,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T45,T46,T40
DetectSt	168	Covered	T45,T46,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T45,T46,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T46,T40
DebounceSt->IdleSt	163	Covered	T130,T61,T80
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T45,T46,T40
IdleSt->DebounceSt	148	Covered	T45,T46,T40
StableSt->IdleSt	206	Covered	T46,T157,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T46,T40
0	1	Covered	T45,T46,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T46,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T46,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T46,T40
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T157,T42
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	68	0	0
CntIncr_A	7234767	2034	0	0
CntNoWrap_A	7234767	6576433	0	0
DetectStDropOut_A	7234767	0	0	0
DetectedOut_A	7234767	2472	0	0
DetectedPulseOut_A	7234767	33	0	0
DisabledIdleSt_A	7234767	6478273	0	0
DisabledNoDetection_A	7234767	6480557	0	0
EnterDebounceSt_A	7234767	36	0	0
EnterDetectSt_A	7234767	33	0	0
EnterStableSt_A	7234767	33	0	0
PulseIsPulse_A	7234767	33	0	0
StayInStableSt	7234767	2422	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	68	0	0
T36	12454	0	0	0
T40	0	2	0	0
T42	0	4	0	0
T45	858	2	0	0
T46	0	2	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	2	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	2	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	2	0	0
T157	0	2	0	0
T158	0	2	0	0
T159	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2034	0	0
T36	12454	0	0	0
T40	0	70	0	0
T42	0	124	0	0
T45	858	51	0	0
T46	0	58	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	77	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	79	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	23	0	0
T157	0	49	0	0
T158	0	37	0	0
T159	0	176	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576433	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2472	0	0
T36	12454	0	0	0
T40	0	450	0	0
T42	0	158	0	0
T45	858	301	0	0
T46	0	54	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	44	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	40	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	7	0	0
T157	0	1	0	0
T158	0	38	0	0
T159	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	33	0	0
T36	12454	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6478273	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6480557	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	36	0	0
T36	12454	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	2	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	33	0	0
T36	12454	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	33	0	0
T36	12454	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	33	0	0
T36	12454	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2422	0	0
T36	12454	0	0	0
T40	0	448	0	0
T42	0	155	0	0
T45	858	299	0	0
T46	0	53	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	43	0	0
T89	0	35	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T130	0	38	0	0
T138	423	0	0	0
T139	402	0	0	0
T145	0	6	0	0
T158	0	36	0	0
T159	0	79	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	16	0	0
T40	1000	0	0	0
T42	0	1	0	0
T46	2897	1	0	0
T48	955	0	0	0
T66	1318	0	0	0
T86	0	1	0	0
T89	0	1	0	0
T136	0	1	0	0
T145	0	1	0	0
T157	0	1	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	531	0	0	0
T163	511	0	0	0
T164	692	0	0	0
T165	505	0	0	0
T166	450	0	0	0
T167	644	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T11,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T47
0	1	Covered	T3,T41
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T47
0	1	Covered	T11,T41,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T47
1	-	Covered	T11,T41,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T47
DetectSt	168	Covered	T3,T11,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T47
DebounceSt->IdleSt	163	Covered	T11,T40,T168
DetectSt->IdleSt	186	Covered	T3,T41,T61
DetectSt->StableSt	191	Covered	T3,T11,T47
IdleSt->DebounceSt	148	Covered	T3,T11,T47
StableSt->IdleSt	206	Covered	T11,T75,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T47
0	1	Covered	T3,T11,T47
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T40,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T47
DetectSt	-	-	-	-	1	-	-	Covered	T3,T41,T61
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T41,T49
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	147	0	0
CntIncr_A	7234767	226095	0	0
CntNoWrap_A	7234767	6576354	0	0
DetectStDropOut_A	7234767	3	0	0
DetectedOut_A	7234767	114265	0	0
DetectedPulseOut_A	7234767	64	0	0
DisabledIdleSt_A	7234767	5890887	0	0
DisabledNoDetection_A	7234767	5893157	0	0
EnterDebounceSt_A	7234767	79	0	0
EnterDetectSt_A	7234767	68	0	0
EnterStableSt_A	7234767	64	0	0
PulseIsPulse_A	7234767	64	0	0
StayInStableSt	7234767	114169	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	2942	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	147	0	0
T3	781	6	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	3	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T41	0	4	0	0
T43	0	2	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	2	0	0
T107	428	0	0	0
T115	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	226095	0	0
T3	781	108	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	28	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	70	0	0
T41	0	82	0	0
T43	0	27	0	0
T46	0	116	0	0
T47	0	38	0	0
T48	0	93	0	0
T49	0	71	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	68	0	0
T107	428	0	0	0
T115	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576354	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3	0	0
T3	781	2	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	114265	0	0
T3	781	42	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	51	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	34	0	0
T42	0	70	0	0
T43	0	70	0	0
T46	0	88	0	0
T47	0	40	0	0
T48	0	315	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	41	0	0
T107	428	0	0	0
T115	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	64	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	5890887	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	5893157	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	79	0	0
T3	781	3	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	2	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	68	0	0
T3	781	3	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	64	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	64	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	114169	0	0
T3	781	40	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	50	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	33	0	0
T42	0	68	0	0
T43	0	68	0	0
T46	0	85	0	0
T47	0	38	0	0
T48	0	314	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T75	0	39	0	0
T107	428	0	0	0
T115	402	0	0	0
T169	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2942	0	0
T1	274961	0	0	0
T2	649	1	0	0
T3	0	3	0	0
T6	497	5	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	2	0	0
T17	37916	0	0	0
T18	427	4	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	0	3	0	0
T25	0	5	0	0
T26	0	24	0	0
T27	0	6	0	0
T107	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	32	0	0
T11	12265	1	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T89	0	1	0	0
T111	714	0	0	0
T112	420	0	0	0
T130	0	1	0	0
T140	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T171,T161,T172
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T3,T11,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T3,T11,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T157,T130,T140
DetectSt->IdleSt	186	Covered	T61,T171,T161
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T3,T11,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T157,T140,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T61,T171,T161
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T43
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	150	0	0
CntIncr_A	7234767	133755	0	0
CntNoWrap_A	7234767	6576351	0	0
DetectStDropOut_A	7234767	3	0	0
DetectedOut_A	7234767	13895	0	0
DetectedPulseOut_A	7234767	68	0	0
DisabledIdleSt_A	7234767	6290388	0	0
DisabledNoDetection_A	7234767	6292660	0	0
EnterDebounceSt_A	7234767	80	0	0
EnterDetectSt_A	7234767	72	0	0
EnterStableSt_A	7234767	68	0	0
PulseIsPulse_A	7234767	68	0	0
StayInStableSt	7234767	13798	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	39	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	150	0	0
T2	649	2	0	0
T3	781	4	0	0
T11	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	4	0	0
T41	0	2	0	0
T43	0	4	0	0
T44	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	133755	0	0
T2	649	73	0	0
T3	781	72	0	0
T11	0	14	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	140	0	0
T41	0	41	0	0
T43	0	54	0	0
T44	0	60	0	0
T46	0	58	0	0
T47	0	38	0	0
T49	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576351	0	0
T1	274961	274560	0	0
T2	649	246	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3	0	0
T101	186702	0	0	0
T161	28861	1	0	0
T171	483	1	0	0
T172	0	1	0	0
T174	422	0	0	0
T175	523	0	0	0
T176	8929	0	0	0
T177	26301	0	0	0
T178	9631	0	0	0
T179	9923	0	0	0
T180	2198	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	13895	0	0
T2	649	166	0	0
T3	781	219	0	0
T11	0	71	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	155	0	0
T41	0	159	0	0
T43	0	81	0	0
T44	0	12	0	0
T46	0	157	0	0
T47	0	78	0	0
T49	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	68	0	0
T2	649	1	0	0
T3	781	2	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6290388	0	0
T1	274961	274560	0	0
T2	649	4	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6292660	0	0
T1	274961	274561	0	0
T2	649	4	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	80	0	0
T2	649	1	0	0
T3	781	2	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	72	0	0
T2	649	1	0	0
T3	781	2	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	68	0	0
T2	649	1	0	0
T3	781	2	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	68	0	0
T2	649	1	0	0
T3	781	2	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	13798	0	0
T2	649	164	0	0
T3	781	216	0	0
T11	0	70	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T40	0	152	0	0
T41	0	158	0	0
T43	0	78	0	0
T44	0	11	0	0
T46	0	156	0	0
T47	0	76	0	0
T49	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	39	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T46	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T135	0	1	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T12,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T12,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T12,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T12,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T45
0	1	Covered	T45,T43,T40
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T45
1	-	Covered	T45,T43,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T45
DetectSt	168	Covered	T11,T12,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T12,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T45
DebounceSt->IdleSt	163	Covered	T80,T181
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T12,T45
IdleSt->DebounceSt	148	Covered	T11,T12,T45
StableSt->IdleSt	206	Covered	T11,T12,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T45
0	1	Covered	T11,T12,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T181
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T43,T40
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	110	0	0
CntIncr_A	7234767	3853	0	0
CntNoWrap_A	7234767	6576391	0	0
DetectStDropOut_A	7234767	0	0	0
DetectedOut_A	7234767	3844	0	0
DetectedPulseOut_A	7234767	54	0	0
DisabledIdleSt_A	7234767	6393211	0	0
DisabledNoDetection_A	7234767	6395481	0	0
EnterDebounceSt_A	7234767	56	0	0
EnterDetectSt_A	7234767	54	0	0
EnterStableSt_A	7234767	54	0	0
PulseIsPulse_A	7234767	54	0	0
StayInStableSt	7234767	3761	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	6533	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	110	0	0
T11	12265	2	0	0
T12	271438	2	0	0
T35	1215	0	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	2	0	0
T159	0	2	0	0
T182	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3853	0	0
T11	12265	14	0	0
T12	271438	42	0	0
T35	1215	0	0	0
T40	0	70	0	0
T42	0	62	0	0
T43	0	27	0	0
T44	0	60	0	0
T45	0	51	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	49	0	0
T159	0	88	0	0
T182	0	128	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576391	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3844	0	0
T11	12265	55	0	0
T12	271438	38	0	0
T35	1215	0	0	0
T40	0	223	0	0
T42	0	41	0	0
T43	0	1	0	0
T44	0	45	0	0
T45	0	39	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	181	0	0
T159	0	39	0	0
T182	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	54	0	0
T11	12265	1	0	0
T12	271438	1	0	0
T35	1215	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T182	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6393211	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6395481	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	56	0	0
T11	12265	1	0	0
T12	271438	1	0	0
T35	1215	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T182	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	54	0	0
T11	12265	1	0	0
T12	271438	1	0	0
T35	1215	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T182	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	54	0	0
T11	12265	1	0	0
T12	271438	1	0	0
T35	1215	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T182	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	54	0	0
T11	12265	1	0	0
T12	271438	1	0	0
T35	1215	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	1	0	0
T159	0	1	0	0
T182	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3761	0	0
T11	12265	53	0	0
T12	271438	36	0	0
T35	1215	0	0	0
T40	0	222	0	0
T42	0	39	0	0
T44	0	43	0	0
T45	0	38	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T86	0	85	0	0
T111	714	0	0	0
T112	420	0	0	0
T157	0	179	0	0
T159	0	38	0	0
T182	0	83	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6533	0	0
T1	274961	6	0	0
T2	649	0	0	0
T3	0	1	0	0
T4	11702	27	0	0
T5	25273	11	0	0
T6	497	7	0	0
T7	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	3	0	0
T17	37916	0	0	0
T18	427	1	0	0
T24	0	7	0	0
T25	0	9	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	24	0	0
T36	12454	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T45	858	1	0	0
T47	526	0	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T89	0	3	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	1	0	0
T159	0	1	0	0
T182	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T12,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T12,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T12,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T45
0	1	Covered	T3,T49,T86
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T45
0	1	Covered	T3,T45,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T45
1	-	Covered	T3,T45,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T45
DetectSt	168	Covered	T3,T12,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T12,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T45
DebounceSt->IdleSt	163	Covered	T130,T150,T120
DetectSt->IdleSt	186	Covered	T3,T49,T86
DetectSt->StableSt	191	Covered	T3,T12,T45
IdleSt->DebounceSt	148	Covered	T3,T12,T45
StableSt->IdleSt	206	Covered	T3,T12,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T12,T45
0	1	Covered	T3,T12,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T120,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T45
DetectSt	-	-	-	-	1	-	-	Covered	T3,T49,T86
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T45,T43
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	140	0	0
CntIncr_A	7234767	212091	0	0
CntNoWrap_A	7234767	6576361	0	0
DetectStDropOut_A	7234767	5	0	0
DetectedOut_A	7234767	49389	0	0
DetectedPulseOut_A	7234767	61	0	0
DisabledIdleSt_A	7234767	6019371	0	0
DisabledNoDetection_A	7234767	6021648	0	0
EnterDebounceSt_A	7234767	75	0	0
EnterDetectSt_A	7234767	67	0	0
EnterStableSt_A	7234767	61	0	0
PulseIsPulse_A	7234767	61	0	0
StayInStableSt	7234767	49303	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	36	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	140	0	0
T3	781	6	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	2	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	4	0	0
T45	0	2	0	0
T49	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T158	0	2	0	0
T169	0	2	0	0
T182	0	4	0	0
T183	0	2	0	0
T184	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	212091	0	0
T3	781	108	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	42	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	54	0	0
T45	0	51	0	0
T49	0	71	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T158	0	37	0	0
T169	0	23	0	0
T182	0	128	0	0
T183	0	48	0	0
T184	0	110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576361	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	5	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T185	0	1	0	0
T186	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	49389	0	0
T3	781	85	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	112	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	110	0	0
T45	0	39	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T130	0	1	0	0
T158	0	76	0	0
T169	0	81	0	0
T182	0	88	0	0
T183	0	59	0	0
T184	0	287	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	61	0	0
T3	781	2	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T130	0	1	0	0
T158	0	1	0	0
T169	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6019371	0	0
T1	274961	274560	0	0
T2	649	4	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6021648	0	0
T1	274961	274561	0	0
T2	649	4	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	75	0	0
T3	781	3	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T158	0	1	0	0
T169	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	67	0	0
T3	781	3	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T158	0	1	0	0
T169	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	61	0	0
T3	781	2	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T130	0	1	0	0
T158	0	1	0	0
T169	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	61	0	0
T3	781	2	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	2	0	0
T45	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T107	428	0	0	0
T115	402	0	0	0
T130	0	1	0	0
T158	0	1	0	0
T169	0	1	0	0
T182	0	2	0	0
T183	0	1	0	0
T184	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	49303	0	0
T3	781	82	0	0
T7	819	0	0	0
T8	8737	0	0	0
T12	0	110	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	107	0	0
T45	0	38	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	164	0	0
T107	428	0	0	0
T115	402	0	0	0
T158	0	74	0	0
T169	0	79	0	0
T182	0	85	0	0
T183	0	57	0	0
T184	0	284	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	36	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T89	0	4	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	1	0	0
T130	0	1	0	0
T135	0	1	0	0
T151	0	2	0	0
T182	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T44,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T45,T44,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T44,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T45
1	0	Covered	T4,T5,T6
1	1	Covered	T45,T44,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T44,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T44,T46
0	1	Covered	T44,T46,T48
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T44,T46
1	-	Covered	T44,T46,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T45,T44,T46
DetectSt	168	Covered	T45,T44,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T45,T44,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T44,T46
DebounceSt->IdleSt	163	Covered	T80
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T45,T44,T46
IdleSt->DebounceSt	148	Covered	T45,T44,T46
StableSt->IdleSt	206	Covered	T44,T46,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T45,T44,T46
0	1	Covered	T45,T44,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T45,T44,T46
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T45,T44,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T44,T46
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T45,T44,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T44,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T46,T48
StableSt	-	-	-	-	-	-	0	Covered	T45,T44,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	107	0	0
CntIncr_A	7234767	117172	0	0
CntNoWrap_A	7234767	6576394	0	0
DetectStDropOut_A	7234767	0	0	0
DetectedOut_A	7234767	53588	0	0
DetectedPulseOut_A	7234767	53	0	0
DisabledIdleSt_A	7234767	6183621	0	0
DisabledNoDetection_A	7234767	6185896	0	0
EnterDebounceSt_A	7234767	54	0	0
EnterDetectSt_A	7234767	53	0	0
EnterStableSt_A	7234767	53	0	0
PulseIsPulse_A	7234767	53	0	0
StayInStableSt	7234767	53509	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	6094	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	107	0	0
T36	12454	0	0	0
T42	0	2	0	0
T44	0	2	0	0
T45	858	2	0	0
T46	0	2	0	0
T47	526	0	0	0
T48	0	4	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	2	0	0
T89	0	10	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	2	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	2	0	0
T182	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	117172	0	0
T36	12454	0	0	0
T42	0	62	0	0
T44	0	60	0	0
T45	858	51	0	0
T46	0	58	0	0
T47	526	0	0	0
T48	0	186	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	77	0	0
T89	0	228	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	36	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	34	0	0
T182	0	64	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576394	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	53588	0	0
T36	12454	0	0	0
T42	0	39	0	0
T44	0	10	0	0
T45	858	39	0	0
T46	0	43	0	0
T47	526	0	0	0
T48	0	83	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	43	0	0
T89	0	249	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	7	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	40	0	0
T182	0	208	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	53	0	0
T36	12454	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T48	0	2	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T89	0	5	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	1	0	0
T182	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6183621	0	0
T1	274961	274560	0	0
T2	649	4	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6185896	0	0
T1	274961	274561	0	0
T2	649	4	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	54	0	0
T36	12454	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T48	0	2	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T89	0	5	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	1	0	0
T182	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	53	0	0
T36	12454	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T48	0	2	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T89	0	5	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	1	0	0
T182	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	53	0	0
T36	12454	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T48	0	2	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T89	0	5	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	1	0	0
T182	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	53	0	0
T36	12454	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T45	858	1	0	0
T46	0	1	0	0
T47	526	0	0	0
T48	0	2	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	1	0	0
T89	0	5	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	1	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	1	0	0
T182	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	53509	0	0
T36	12454	0	0	0
T42	0	38	0	0
T44	0	9	0	0
T45	858	37	0	0
T46	0	42	0	0
T47	526	0	0	0
T48	0	80	0	0
T63	1702	0	0	0
T70	67007	0	0	0
T86	0	42	0	0
T89	0	242	0	0
T93	402	0	0	0
T94	412	0	0	0
T96	4416	0	0	0
T135	0	6	0	0
T138	423	0	0	0
T139	402	0	0	0
T150	0	39	0	0
T182	0	207	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6094	0	0
T1	274961	0	0	0
T2	649	0	0	0
T3	0	2	0	0
T4	11702	27	0	0
T5	25273	9	0	0
T6	497	7	0	0
T8	0	9	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	2	0	0
T17	37916	0	0	0
T18	427	3	0	0
T24	0	5	0	0
T25	0	9	0	0
T107	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	26	0	0
T37	25919	0	0	0
T42	0	1	0	0
T44	775	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	1	0	0
T89	0	3	0	0
T135	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T155	404	0	0	0
T156	524	0	0	0
T182	0	1	0	0
T187	10087	0	0	0
T188	717	0	0	0
T189	690	0	0	0
T190	630	0	0	0