Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T11,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T11,T12
0	1	Covered	T2,T11,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T11,T12
1	-	Covered	T2,T11,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T11,T12
DetectSt	168	Covered	T2,T11,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T11,T12
DebounceSt->IdleSt	163	Covered	T11,T61,T142
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T11,T12
IdleSt->DebounceSt	148	Covered	T2,T11,T12
StableSt->IdleSt	206	Covered	T2,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T11,T12
0	1	Covered	T2,T11,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T12
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T11,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T11,T43
StableSt	-	-	-	-	-	-	0	Covered	T2,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	150	0	0
CntIncr_A	7234767	57162	0	0
CntNoWrap_A	7234767	6576351	0	0
DetectStDropOut_A	7234767	0	0	0
DetectedOut_A	7234767	4692	0	0
DetectedPulseOut_A	7234767	73	0	0
DisabledIdleSt_A	7234767	6444667	0	0
DisabledNoDetection_A	7234767	6446946	0	0
EnterDebounceSt_A	7234767	77	0	0
EnterDetectSt_A	7234767	73	0	0
EnterStableSt_A	7234767	73	0	0
PulseIsPulse_A	7234767	73	0	0
StayInStableSt	7234767	4591	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	45	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	150	0	0
T2	649	2	0	0
T3	781	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	4	0	0
T44	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T75	0	2	0	0
T157	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	57162	0	0
T2	649	73	0	0
T3	781	0	0	0
T11	0	28	0	0
T12	0	42	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	54	0	0
T44	0	60	0	0
T47	0	38	0	0
T48	0	93	0	0
T49	0	71	0	0
T75	0	68	0	0
T157	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576351	0	0
T1	274961	274560	0	0
T2	649	246	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	4692	0	0
T2	649	37	0	0
T3	781	0	0	0
T11	0	13	0	0
T12	0	38	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	69	0	0
T44	0	27	0	0
T47	0	40	0	0
T48	0	225	0	0
T49	0	42	0	0
T75	0	119	0	0
T157	0	221	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	73	0	0
T2	649	1	0	0
T3	781	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T75	0	1	0	0
T157	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6444667	0	0
T1	274961	274560	0	0
T2	649	4	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6446946	0	0
T1	274961	274561	0	0
T2	649	4	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	77	0	0
T2	649	1	0	0
T3	781	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T75	0	1	0	0
T157	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	73	0	0
T2	649	1	0	0
T3	781	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T75	0	1	0	0
T157	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	73	0	0
T2	649	1	0	0
T3	781	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T75	0	1	0	0
T157	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	73	0	0
T2	649	1	0	0
T3	781	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T75	0	1	0	0
T157	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	4591	0	0
T2	649	36	0	0
T3	781	0	0	0
T11	0	12	0	0
T12	0	36	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	67	0	0
T44	0	26	0	0
T47	0	38	0	0
T48	0	223	0	0
T49	0	40	0	0
T75	0	117	0	0
T157	0	219	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	45	0	0
T2	649	1	0	0
T3	781	0	0	0
T11	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T43	0	2	0	0
T44	0	1	0	0
T145	0	1	0	0
T157	0	2	0	0
T159	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T11,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T47
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T43,T44
0	1	Covered	T191,T104
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T43,T44
0	1	Covered	T11,T43,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T43,T44
1	-	Covered	T11,T43,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T43,T44
DetectSt	168	Covered	T11,T43,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T43,T44
DebounceSt->IdleSt	163	Covered	T135,T192,T80
DetectSt->IdleSt	186	Covered	T61,T191,T104
DetectSt->StableSt	191	Covered	T11,T43,T44
IdleSt->DebounceSt	148	Covered	T11,T43,T44
StableSt->IdleSt	206	Covered	T11,T43,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T43,T44
0	1	Covered	T11,T43,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T43,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T135,T192
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T43,T44
DetectSt	-	-	-	-	1	-	-	Covered	T61,T191,T104
DetectSt	-	-	-	-	0	1	-	Covered	T11,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T43,T40
StableSt	-	-	-	-	-	-	0	Covered	T11,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	101	0	0
CntIncr_A	7234767	106337	0	0
CntNoWrap_A	7234767	6576400	0	0
DetectStDropOut_A	7234767	2	0	0
DetectedOut_A	7234767	3175	0	0
DetectedPulseOut_A	7234767	46	0	0
DisabledIdleSt_A	7234767	6330234	0	0
DisabledNoDetection_A	7234767	6332508	0	0
EnterDebounceSt_A	7234767	52	0	0
EnterDetectSt_A	7234767	49	0	0
EnterStableSt_A	7234767	46	0	0
PulseIsPulse_A	7234767	46	0	0
StayInStableSt	7234767	3105	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	6123	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	101	0	0
T11	12265	4	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	4	0	0
T43	0	4	0	0
T44	0	2	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	3	0	0
T145	0	2	0	0
T159	0	2	0	0
T182	0	2	0	0
T183	0	2	0	0
T184	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	106337	0	0
T11	12265	28	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	140	0	0
T43	0	54	0	0
T44	0	60	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	72	0	0
T145	0	23	0	0
T159	0	88	0	0
T182	0	64	0	0
T183	0	48	0	0
T184	0	55	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576400	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2	0	0
T104	0	1	0	0
T191	558	1	0	0
T193	495	0	0	0
T194	402	0	0	0
T195	1853	0	0	0
T196	581	0	0	0
T197	32560	0	0	0
T198	2228	0	0	0
T199	10354	0	0	0
T200	15405	0	0	0
T201	116124	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3175	0	0
T11	12265	155	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	52	0	0
T43	0	81	0	0
T44	0	218	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	6	0	0
T145	0	114	0	0
T159	0	41	0	0
T182	0	104	0	0
T183	0	58	0	0
T184	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	46	0	0
T11	12265	2	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	1	0	0
T145	0	1	0	0
T159	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6330234	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6332508	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	52	0	0
T11	12265	2	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	2	0	0
T145	0	1	0	0
T159	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	49	0	0
T11	12265	2	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	1	0	0
T145	0	1	0	0
T159	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	46	0	0
T11	12265	2	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	1	0	0
T145	0	1	0	0
T159	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	46	0	0
T11	12265	2	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	1	0	0
T145	0	1	0	0
T159	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3105	0	0
T11	12265	152	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	49	0	0
T43	0	78	0	0
T44	0	216	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	5	0	0
T145	0	113	0	0
T159	0	39	0	0
T182	0	103	0	0
T183	0	56	0	0
T184	0	97	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6123	0	0
T1	274961	0	0	0
T2	649	1	0	0
T3	0	1	0	0
T4	11702	31	0	0
T5	25273	12	0	0
T6	497	9	0	0
T8	0	11	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	4	0	0
T17	37916	0	0	0
T18	427	3	0	0
T24	0	7	0	0
T25	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	22	0	0
T11	12265	1	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T40	0	1	0	0
T43	0	1	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T89	0	2	0	0
T111	714	0	0	0
T112	420	0	0	0
T135	0	1	0	0
T145	0	1	0	0
T152	0	1	0	0
T160	0	1	0	0
T182	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T3,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T137,T192
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T3,T11,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T3,T11,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T11
DetectSt	168	Covered	T2,T3,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T11
DebounceSt->IdleSt	163	Covered	T152,T170,T120
DetectSt->IdleSt	186	Covered	T61,T137,T192
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T3,T11
StableSt->IdleSt	206	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T11
0	1	Covered	T2,T3,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T11
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T152,T170,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	1	-	-	Covered	T61,T137,T192
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T44
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	143	0	0
CntIncr_A	7234767	133432	0	0
CntNoWrap_A	7234767	6576358	0	0
DetectStDropOut_A	7234767	2	0	0
DetectedOut_A	7234767	21598	0	0
DetectedPulseOut_A	7234767	66	0	0
DisabledIdleSt_A	7234767	6177453	0	0
DisabledNoDetection_A	7234767	6179724	0	0
EnterDebounceSt_A	7234767	74	0	0
EnterDetectSt_A	7234767	69	0	0
EnterStableSt_A	7234767	66	0	0
PulseIsPulse_A	7234767	66	0	0
StayInStableSt	7234767	21497	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	143	0	0
T2	649	2	0	0
T3	781	2	0	0
T11	0	4	0	0
T12	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	4	0	0
T44	0	2	0	0
T48	0	4	0	0
T157	0	2	0	0
T158	0	2	0	0
T203	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	133432	0	0
T2	649	73	0	0
T3	781	36	0	0
T11	0	28	0	0
T12	0	42	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	124	0	0
T44	0	60	0	0
T48	0	186	0	0
T157	0	49	0	0
T158	0	37	0	0
T203	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576358	0	0
T1	274961	274560	0	0
T2	649	246	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2	0	0
T84	17752	0	0	0
T90	2067	0	0	0
T137	555	1	0	0
T192	0	1	0	0
T204	502	0	0	0
T205	494	0	0	0
T206	16310	0	0	0
T207	422	0	0	0
T208	794	0	0	0
T209	541	0	0	0
T210	7978	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	21598	0	0
T2	649	55	0	0
T3	781	102	0	0
T11	0	53	0	0
T12	0	112	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	251	0	0
T44	0	112	0	0
T48	0	84	0	0
T157	0	284	0	0
T158	0	37	0	0
T203	0	177	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	66	0	0
T2	649	1	0	0
T3	781	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T203	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6177453	0	0
T1	274961	274560	0	0
T2	649	4	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6179724	0	0
T1	274961	274561	0	0
T2	649	4	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	74	0	0
T2	649	1	0	0
T3	781	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T203	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	69	0	0
T2	649	1	0	0
T3	781	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T203	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	66	0	0
T2	649	1	0	0
T3	781	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T203	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	66	0	0
T2	649	1	0	0
T3	781	1	0	0
T11	0	2	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	2	0	0
T44	0	1	0	0
T48	0	2	0	0
T157	0	1	0	0
T158	0	1	0	0
T203	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	21497	0	0
T2	649	53	0	0
T3	781	101	0	0
T11	0	51	0	0
T12	0	110	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T20	729	0	0	0
T24	496	0	0	0
T42	0	248	0	0
T44	0	111	0	0
T48	0	81	0	0
T157	0	283	0	0
T158	0	35	0	0
T203	0	175	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	31	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	2	0	0
T24	496	0	0	0
T25	497	0	0	0
T42	0	1	0	0
T44	0	1	0	0
T48	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T107	428	0	0	0
T115	402	0	0	0
T130	0	1	0	0
T157	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T41,T42
0	1	Covered	T211
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T41,T42
0	1	Covered	T41,T42,T145
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T41,T42
1	-	Covered	T41,T42,T145

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T41,T42
DetectSt	168	Covered	T3,T41,T42
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T41,T42
DebounceSt->IdleSt	163	Covered	T61,T212,T80
DetectSt->IdleSt	186	Covered	T211
DetectSt->StableSt	191	Covered	T3,T41,T42
IdleSt->DebounceSt	148	Covered	T3,T41,T42
StableSt->IdleSt	206	Covered	T41,T42,T145

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T41,T42
0	1	Covered	T3,T41,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T41,T42
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T212
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T211
DetectSt	-	-	-	-	0	1	-	Covered	T3,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T145
StableSt	-	-	-	-	-	-	0	Covered	T3,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	67	0	0
CntIncr_A	7234767	69701	0	0
CntNoWrap_A	7234767	6576434	0	0
DetectStDropOut_A	7234767	1	0	0
DetectedOut_A	7234767	3779	0	0
DetectedPulseOut_A	7234767	31	0	0
DisabledIdleSt_A	7234767	6200242	0	0
DisabledNoDetection_A	7234767	6202522	0	0
EnterDebounceSt_A	7234767	35	0	0
EnterDetectSt_A	7234767	32	0	0
EnterStableSt_A	7234767	31	0	0
PulseIsPulse_A	7234767	31	0	0
StayInStableSt	7234767	3738	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	6211	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	67	0	0
T3	781	2	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T61	0	1	0	0
T86	0	2	0	0
T89	0	2	0	0
T107	428	0	0	0
T115	402	0	0	0
T135	0	4	0	0
T144	0	2	0	0
T145	0	4	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	69701	0	0
T3	781	36	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	41	0	0
T42	0	62	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T61	0	46	0	0
T86	0	77	0	0
T89	0	25	0	0
T107	428	0	0	0
T115	402	0	0	0
T135	0	72	0	0
T144	0	67	0	0
T145	0	46	0	0
T160	0	23	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576434	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1	0	0
T211	1032	1	0	0
T213	28249	0	0	0
T214	526	0	0	0
T215	5516	0	0	0
T216	422	0	0	0
T217	2008	0	0	0
T218	901	0	0	0
T219	417	0	0	0
T220	493	0	0	0
T221	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3779	0	0
T3	781	43	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	39	0	0
T42	0	117	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	43	0	0
T89	0	17	0	0
T107	428	0	0	0
T115	402	0	0	0
T120	0	41	0	0
T135	0	87	0	0
T144	0	106	0	0
T145	0	114	0	0
T160	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	31	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T89	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T120	0	1	0	0
T135	0	2	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6200242	0	0
T1	274961	274560	0	0
T2	649	4	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6202522	0	0
T1	274961	274561	0	0
T2	649	4	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	35	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T61	0	1	0	0
T86	0	1	0	0
T89	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T135	0	2	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	32	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T89	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T120	0	1	0	0
T135	0	2	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	31	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T89	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T120	0	1	0	0
T135	0	2	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	31	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T89	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T120	0	1	0	0
T135	0	2	0	0
T144	0	1	0	0
T145	0	2	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3738	0	0
T3	781	41	0	0
T7	819	0	0	0
T8	8737	0	0	0
T24	496	0	0	0
T25	497	0	0	0
T41	0	38	0	0
T42	0	116	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	42	0	0
T89	0	16	0	0
T107	428	0	0	0
T115	402	0	0	0
T120	0	40	0	0
T135	0	85	0	0
T144	0	104	0	0
T145	0	112	0	0
T160	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6211	0	0
T1	274961	0	0	0
T2	649	0	0	0
T3	0	1	0	0
T4	11702	34	0	0
T5	25273	9	0	0
T6	497	9	0	0
T8	0	10	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	4	0	0
T17	37916	0	0	0
T18	427	3	0	0
T24	0	7	0	0
T25	0	6	0	0
T107	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	21	0	0
T38	11113	0	0	0
T41	690	1	0	0
T42	0	1	0	0
T49	595	0	0	0
T86	0	1	0	0
T89	0	1	0	0
T120	0	1	0	0
T135	0	2	0	0
T145	0	2	0	0
T160	0	1	0	0
T185	0	1	0	0
T222	0	1	0	0
T223	522	0	0	0
T224	413	0	0	0
T225	434	0	0	0
T226	402	0	0	0
T227	693	0	0	0
T228	419	0	0	0
T229	495	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T46,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T43,T46,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T46,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T47,T43,T46
1	0	Covered	T4,T5,T6
1	1	Covered	T43,T46,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T46,T48
0	1	Covered	T172
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T46,T48
0	1	Covered	T43,T46,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T46,T48
1	-	Covered	T43,T46,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T46,T48
DetectSt	168	Covered	T43,T46,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T43,T46,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T46,T48
DebounceSt->IdleSt	163	Covered	T80,T230
DetectSt->IdleSt	186	Covered	T61,T172
DetectSt->StableSt	191	Covered	T43,T46,T48
IdleSt->DebounceSt	148	Covered	T43,T46,T48
StableSt->IdleSt	206	Covered	T43,T46,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T43,T46,T48
0	1	Covered	T43,T46,T48
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T46,T48
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T46,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T46,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T230
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T46,T48
DetectSt	-	-	-	-	1	-	-	Covered	T61,T172
DetectSt	-	-	-	-	0	1	-	Covered	T43,T46,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T46,T40
StableSt	-	-	-	-	-	-	0	Covered	T43,T46,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	134	0	0
CntIncr_A	7234767	57839	0	0
CntNoWrap_A	7234767	6576367	0	0
DetectStDropOut_A	7234767	1	0	0
DetectedOut_A	7234767	66709	0	0
DetectedPulseOut_A	7234767	64	0	0
DisabledIdleSt_A	7234767	6350324	0	0
DisabledNoDetection_A	7234767	6352605	0	0
EnterDebounceSt_A	7234767	68	0	0
EnterDetectSt_A	7234767	66	0	0
EnterStableSt_A	7234767	64	0	0
PulseIsPulse_A	7234767	64	0	0
StayInStableSt	7234767	66616	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	134	0	0
T40	0	2	0	0
T43	709	4	0	0
T44	775	0	0	0
T46	0	2	0	0
T48	0	2	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	4	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	2	0	0
T135	0	4	0	0
T145	0	2	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	2	0	0
T184	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	57839	0	0
T40	0	70	0	0
T43	709	54	0	0
T44	775	0	0	0
T46	0	58	0	0
T48	0	93	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	154	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	53336	0	0
T135	0	72	0	0
T145	0	23	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	48	0	0
T184	0	110	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576367	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1	0	0
T104	129420	0	0	0
T172	66750	1	0	0
T231	526	0	0	0
T232	505	0	0	0
T233	15521	0	0	0
T234	633	0	0	0
T235	489	0	0	0
T236	408	0	0	0
T237	22836	0	0	0
T238	403	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	66709	0	0
T40	0	232	0	0
T43	709	69	0	0
T44	775	0	0	0
T46	0	121	0	0
T48	0	225	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	322	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	61048	0	0
T135	0	101	0	0
T145	0	71	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	38	0	0
T184	0	140	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	64	0	0
T40	0	1	0	0
T43	709	2	0	0
T44	775	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	2	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	1	0	0
T135	0	2	0	0
T145	0	1	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	1	0	0
T184	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6350324	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6352605	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	68	0	0
T40	0	1	0	0
T43	709	2	0	0
T44	775	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	2	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	1	0	0
T135	0	2	0	0
T145	0	1	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	1	0	0
T184	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	66	0	0
T40	0	1	0	0
T43	709	2	0	0
T44	775	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	2	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	1	0	0
T135	0	2	0	0
T145	0	1	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	1	0	0
T184	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	64	0	0
T40	0	1	0	0
T43	709	2	0	0
T44	775	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	2	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	1	0	0
T135	0	2	0	0
T145	0	1	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	1	0	0
T184	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	64	0	0
T40	0	1	0	0
T43	709	2	0	0
T44	775	0	0	0
T46	0	1	0	0
T48	0	1	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	2	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	1	0	0
T135	0	2	0	0
T145	0	1	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	1	0	0
T184	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	66616	0	0
T40	0	231	0	0
T43	709	67	0	0
T44	775	0	0	0
T46	0	120	0	0
T48	0	223	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	319	0	0
T113	468	0	0	0
T114	14013	0	0	0
T130	0	61046	0	0
T135	0	99	0	0
T145	0	69	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	37	0	0
T184	0	137	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	35	0	0
T40	0	1	0	0
T43	709	2	0	0
T44	775	0	0	0
T46	0	1	0	0
T75	6848	0	0	0
T79	21359	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T113	468	0	0	0
T114	14013	0	0	0
T135	0	2	0	0
T140	0	2	0	0
T151	0	1	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T183	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T11,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T11,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T40
1	0	Covered	T4,T5,T6
1	1	Covered	T3,T11,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T40
0	1	Covered	T144
1	0	Covered	T61

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T40
0	1	Covered	T157,T42,T86
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T40
1	-	Covered	T157,T42,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T40
DetectSt	168	Covered	T3,T11,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T11,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T40
DebounceSt->IdleSt	163	Covered	T80
DetectSt->IdleSt	186	Covered	T61,T144
DetectSt->StableSt	191	Covered	T3,T11,T40
IdleSt->DebounceSt	148	Covered	T3,T11,T40
StableSt->IdleSt	206	Covered	T11,T157,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T40
0	1	Covered	T3,T11,T40
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T80
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T40
DetectSt	-	-	-	-	1	-	-	Covered	T61,T144
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T157,T42,T86
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	91	0	0
CntIncr_A	7234767	18382	0	0
CntNoWrap_A	7234767	6576410	0	0
DetectStDropOut_A	7234767	1	0	0
DetectedOut_A	7234767	31370	0	0
DetectedPulseOut_A	7234767	43	0	0
DisabledIdleSt_A	7234767	6147889	0	0
DisabledNoDetection_A	7234767	6150163	0	0
EnterDebounceSt_A	7234767	46	0	0
EnterDetectSt_A	7234767	45	0	0
EnterStableSt_A	7234767	43	0	0
PulseIsPulse_A	7234767	43	0	0
StayInStableSt	7234767	31305	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7234767	6841	0	0
gen_low_level_sva.LowLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	91	0	0
T3	781	2	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	2	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	2	0	0
T42	0	4	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	2	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	2	0	0
T135	0	4	0	0
T157	0	2	0	0
T169	0	2	0	0
T183	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	18382	0	0
T3	781	36	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	14	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	70	0	0
T42	0	124	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	77	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	31	0	0
T135	0	72	0	0
T157	0	49	0	0
T169	0	23	0	0
T183	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6576410	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1	0	0
T120	11871	0	0	0
T144	993	1	0	0
T173	93230	0	0	0
T239	778	0	0	0
T240	410	0	0	0
T241	503	0	0	0
T242	21167	0	0	0
T243	716	0	0	0
T244	495	0	0	0
T245	21911	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	31370	0	0
T3	781	101	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	55	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	147	0	0
T42	0	250	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	121	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	83	0	0
T135	0	128	0	0
T157	0	197	0	0
T169	0	39	0	0
T183	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	43	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	1	0	0
T135	0	2	0	0
T157	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6147889	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6150163	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	46	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	1	0	0
T135	0	2	0	0
T157	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	45	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	1	0	0
T135	0	2	0	0
T157	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	43	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	1	0	0
T135	0	2	0	0
T157	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	43	0	0
T3	781	1	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	1	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	1	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	1	0	0
T135	0	2	0	0
T157	0	1	0	0
T169	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	31305	0	0
T3	781	99	0	0
T7	819	0	0	0
T8	8737	0	0	0
T11	0	53	0	0
T24	496	0	0	0
T25	497	0	0	0
T40	0	145	0	0
T42	0	247	0	0
T51	669	0	0	0
T52	721	0	0	0
T53	683	0	0	0
T86	0	120	0	0
T107	428	0	0	0
T115	402	0	0	0
T124	0	82	0	0
T135	0	125	0	0
T157	0	196	0	0
T169	0	37	0	0
T183	0	57	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6841	0	0
T1	274961	6	0	0
T2	649	0	0	0
T3	0	1	0	0
T4	11702	31	0	0
T5	25273	12	0	0
T6	497	7	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	2	0	0
T17	37916	3	0	0
T18	427	4	0	0
T19	0	3	0	0
T20	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	21	0	0
T42	965	1	0	0
T67	3872	0	0	0
T86	0	1	0	0
T89	0	2	0	0
T124	0	1	0	0
T135	0	1	0	0
T140	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T151	0	1	0	0
T157	832	1	0	0
T246	629	0	0	0
T247	10709	0	0	0
T248	422	0	0	0
T249	443	0	0	0
T250	424	0	0	0
T251	525	0	0	0
T252	404	0	0	0