Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T29,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T30,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T29,T30
1	0	Covered	T4,T50,T10
1	1	Covered	T4,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T30,T57
0	1	Covered	T30,T57,T58
1	0	Covered	T10,T59,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T50,T13
0	1	Covered	T4,T50,T13
1	0	Covered	T82,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T50,T13
1	-	Covered	T4,T50,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T29,T30
DetectSt	168	Covered	T4,T30,T57
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T50,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T30,T57
DebounceSt->IdleSt	163	Covered	T29,T61,T253
DetectSt->IdleSt	186	Covered	T30,T57,T58
DetectSt->StableSt	191	Covered	T4,T50,T13
IdleSt->DebounceSt	148	Covered	T4,T29,T30
StableSt->IdleSt	206	Covered	T4,T50,T13

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T29,T30
0	1	Covered	T4,T29,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T30,T57
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T29,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T30,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T61,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T57,T58
DetectSt	-	-	-	-	0	1	-	Covered	T4,T50,T13
DetectSt	-	-	-	-	0	0	-	Covered	T4,T30,T57
StableSt	-	-	-	-	-	-	1	Covered	T4,T50,T13
StableSt	-	-	-	-	-	-	0	Covered	T4,T50,T13
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	2847	0	0
CntIncr_A	7234767	94110	0	0
CntNoWrap_A	7234767	6573654	0	0
DetectStDropOut_A	7234767	478	0	0
DetectedOut_A	7234767	63613	0	0
DetectedPulseOut_A	7234767	757	0	0
DisabledIdleSt_A	7234767	6153056	0	0
DisabledNoDetection_A	7234767	6155225	0	0
EnterDebounceSt_A	7234767	1442	0	0
EnterDetectSt_A	7234767	1406	0	0
EnterStableSt_A	7234767	757	0	0
PulseIsPulse_A	7234767	757	0	0
StayInStableSt	7234767	62777	0	0
gen_high_event_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	676	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2847	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	54	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	52	0	0
T13	0	18	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	2	0	0
T30	0	20	0	0
T50	0	24	0	0
T57	0	54	0	0
T58	0	12	0	0
T59	0	16	0	0
T76	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	94110	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1917	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	1440	0	0
T13	0	621	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	100	0	0
T30	0	494	0	0
T50	0	1032	0	0
T57	0	1351	0	0
T58	0	366	0	0
T59	0	565	0	0
T76	0	517	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6573654	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11243	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	478	0	0
T10	8780	12	0	0
T11	12265	0	0	0
T28	1623	0	0	0
T30	5120	10	0	0
T36	0	8	0	0
T50	21396	0	0	0
T57	5119	27	0	0
T58	5716	6	0	0
T76	0	17	0	0
T95	0	31	0	0
T96	0	33	0	0
T97	0	8	0	0
T98	0	3	0	0
T108	402	0	0	0
T109	424	0	0	0
T110	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	63613	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	2468	0	0
T5	25273	0	0	0
T6	497	0	0	0
T13	0	650	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	1903	0	0
T50	0	1637	0	0
T113	0	43	0	0
T114	0	2090	0	0
T187	0	289	0	0
T254	0	808	0	0
T255	0	1815	0	0
T256	0	556	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	757	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T13	0	9	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	23	0	0
T50	0	12	0	0
T113	0	1	0	0
T114	0	23	0	0
T187	0	8	0	0
T254	0	24	0	0
T255	0	13	0	0
T256	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6153056	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	4045	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6155225	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	4045	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1442	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	26	0	0
T13	0	9	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	2	0	0
T30	0	10	0	0
T50	0	12	0	0
T57	0	27	0	0
T58	0	6	0	0
T59	0	8	0	0
T76	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1406	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	26	0	0
T13	0	9	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T30	0	10	0	0
T50	0	12	0	0
T57	0	27	0	0
T58	0	6	0	0
T59	0	8	0	0
T76	0	17	0	0
T95	0	31	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	757	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T13	0	9	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	23	0	0
T50	0	12	0	0
T113	0	1	0	0
T114	0	23	0	0
T187	0	8	0	0
T254	0	24	0	0
T255	0	13	0	0
T256	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	757	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T13	0	9	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	23	0	0
T50	0	12	0	0
T113	0	1	0	0
T114	0	23	0	0
T187	0	8	0	0
T254	0	24	0	0
T255	0	13	0	0
T256	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	62777	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	2440	0	0
T5	25273	0	0	0
T6	497	0	0	0
T13	0	640	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	1876	0	0
T50	0	1624	0	0
T113	0	41	0	0
T114	0	2065	0	0
T187	0	281	0	0
T254	0	783	0	0
T255	0	1799	0	0
T256	0	544	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	676	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	26	0	0
T5	25273	0	0	0
T6	497	0	0	0
T13	0	8	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	19	0	0
T50	0	11	0	0
T114	0	21	0	0
T187	0	8	0	0
T254	0	23	0	0
T255	0	10	0	0
T256	0	10	0	0
T257	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T5,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T11,T99,T100
1	0	Covered	T61,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T8
0	1	Covered	T5,T8,T9
1	0	Covered	T81,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T5,T8
1	-	Covered	T5,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T5,T8
DetectSt	168	Covered	T4,T5,T8
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T5,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T5,T8
DebounceSt->IdleSt	163	Covered	T4,T9,T11
DetectSt->IdleSt	186	Covered	T11,T99,T61
DetectSt->StableSt	191	Covered	T4,T5,T8
IdleSt->DebounceSt	148	Covered	T4,T5,T8
StableSt->IdleSt	206	Covered	T4,T5,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T8
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T5,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T5,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T9,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T5,T8
DetectSt	-	-	-	-	1	-	-	Covered	T11,T99,T61
DetectSt	-	-	-	-	0	1	-	Covered	T4,T5,T8
DetectSt	-	-	-	-	0	0	-	Covered	T4,T5,T8
StableSt	-	-	-	-	-	-	1	Covered	T5,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T4,T5,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	899	0	0
CntIncr_A	7234767	45255	0	0
CntNoWrap_A	7234767	6575602	0	0
DetectStDropOut_A	7234767	38	0	0
DetectedOut_A	7234767	14896	0	0
DetectedPulseOut_A	7234767	368	0	0
DisabledIdleSt_A	7234767	6212877	0	0
DisabledNoDetection_A	7234767	6214516	0	0
EnterDebounceSt_A	7234767	493	0	0
EnterDetectSt_A	7234767	410	0	0
EnterStableSt_A	7234767	368	0	0
PulseIsPulse_A	7234767	368	0	0
StayInStableSt	7234767	14499	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	336	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	899	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	3	0	0
T5	25273	18	0	0
T6	497	0	0	0
T8	0	4	0	0
T9	0	22	0	0
T11	0	4	0	0
T12	0	2	0	0
T13	0	4	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	6	0	0
T50	0	2	0	0
T92	0	27	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	45255	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	108	0	0
T5	25273	1431	0	0
T6	497	0	0	0
T8	0	292	0	0
T9	0	1184	0	0
T11	0	237	0	0
T12	0	72	0	0
T13	0	130	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	177	0	0
T50	0	91	0	0
T92	0	1996	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6575602	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11294	0	0
T5	25273	24799	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	38	0	0
T11	12265	1	0	0
T12	271438	0	0	0
T35	1215	0	0	0
T59	24652	0	0	0
T68	494	0	0	0
T69	1296	0	0	0
T72	503	0	0	0
T76	4166	0	0	0
T99	0	13	0	0
T100	0	2	0	0
T101	0	4	0	0
T102	0	6	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	4	0	0
T106	0	6	0	0
T111	714	0	0	0
T112	420	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	14896	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	38	0	0
T5	25273	56	0	0
T6	497	0	0	0
T8	0	9	0	0
T9	0	333	0	0
T11	0	3	0	0
T13	0	111	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	115	0	0
T50	0	53	0	0
T92	0	60	0	0
T114	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	368	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1	0	0
T5	25273	9	0	0
T6	497	0	0	0
T8	0	2	0	0
T9	0	10	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	3	0	0
T50	0	1	0	0
T92	0	13	0	0
T114	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6212877	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	8830	0	0
T5	25273	20147	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6214516	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	8831	0	0
T5	25273	20147	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	493	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	2	0	0
T5	25273	9	0	0
T6	497	0	0	0
T8	0	2	0	0
T9	0	12	0	0
T11	0	3	0	0
T12	0	2	0	0
T13	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	3	0	0
T50	0	1	0	0
T92	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	410	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1	0	0
T5	25273	9	0	0
T6	497	0	0	0
T8	0	2	0	0
T9	0	10	0	0
T11	0	2	0	0
T13	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	3	0	0
T50	0	1	0	0
T92	0	13	0	0
T114	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	368	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1	0	0
T5	25273	9	0	0
T6	497	0	0	0
T8	0	2	0	0
T9	0	10	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	3	0	0
T50	0	1	0	0
T92	0	13	0	0
T114	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	368	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1	0	0
T5	25273	9	0	0
T6	497	0	0	0
T8	0	2	0	0
T9	0	10	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	3	0	0
T50	0	1	0	0
T92	0	13	0	0
T114	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	14499	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	36	0	0
T5	25273	47	0	0
T6	497	0	0	0
T8	0	7	0	0
T9	0	323	0	0
T11	0	2	0	0
T13	0	109	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T39	0	112	0	0
T50	0	51	0	0
T92	0	47	0	0
T114	0	157	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	336	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	9	0	0
T6	497	0	0	0
T8	0	2	0	0
T9	0	10	0	0
T11	0	1	0	0
T13	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T37	0	10	0	0
T39	0	3	0	0
T79	0	6	0	0
T92	0	13	0	0
T114	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T29,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T29,T30
1	0	Covered	T4,T50,T10
1	1	Covered	T4,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T29,T30
0	1	Covered	T30,T57,T58
1	0	Covered	T10,T13,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T29,T50
0	1	Covered	T4,T29,T50
1	0	Covered	T61

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T29,T50
1	-	Covered	T4,T29,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T29,T30
DetectSt	168	Covered	T4,T29,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T29,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T29,T30
DebounceSt->IdleSt	163	Covered	T29,T61,T253
DetectSt->IdleSt	186	Covered	T30,T57,T58
DetectSt->StableSt	191	Covered	T4,T29,T50
IdleSt->DebounceSt	148	Covered	T4,T29,T30
StableSt->IdleSt	206	Covered	T4,T29,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T29,T30
0	1	Covered	T4,T29,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T29,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T29,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T29,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T61,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T57,T58
DetectSt	-	-	-	-	0	1	-	Covered	T4,T29,T50
DetectSt	-	-	-	-	0	0	-	Covered	T4,T29,T30
StableSt	-	-	-	-	-	-	1	Covered	T4,T29,T50
StableSt	-	-	-	-	-	-	0	Covered	T4,T29,T50
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	3084	0	0
CntIncr_A	7234767	113450	0	0
CntNoWrap_A	7234767	6573417	0	0
DetectStDropOut_A	7234767	573	0	0
DetectedOut_A	7234767	67305	0	0
DetectedPulseOut_A	7234767	730	0	0
DisabledIdleSt_A	7234767	6151943	0	0
DisabledNoDetection_A	7234767	6154107	0	0
EnterDebounceSt_A	7234767	1560	0	0
EnterDetectSt_A	7234767	1525	0	0
EnterStableSt_A	7234767	730	0	0
PulseIsPulse_A	7234767	730	0	0
StayInStableSt	7234767	66492	0	0
gen_high_event_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	646	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	3084	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	24	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	34	0	0
T13	0	48	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	8	0	0
T30	0	26	0	0
T50	0	24	0	0
T57	0	52	0	0
T58	0	52	0	0
T59	0	30	0	0
T76	0	34	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	113450	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1008	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	935	0	0
T13	0	1680	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	392	0	0
T30	0	643	0	0
T50	0	1116	0	0
T57	0	1298	0	0
T58	0	1615	0	0
T59	0	990	0	0
T76	0	517	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6573417	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11273	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	573	0	0
T10	8780	8	0	0
T11	12265	0	0	0
T13	0	6	0	0
T28	1623	0	0	0
T30	5120	13	0	0
T50	21396	0	0	0
T57	5119	26	0	0
T58	5716	26	0	0
T76	0	17	0	0
T95	0	22	0	0
T96	0	23	0	0
T97	0	13	0	0
T108	402	0	0	0
T109	424	0	0	0
T110	427	0	0	0
T254	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	67305	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	401	0	0
T5	25273	0	0	0
T6	497	0	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	4	0	0
T36	0	1719	0	0
T39	0	14	0	0
T50	0	2295	0	0
T59	0	1606	0	0
T114	0	33	0	0
T187	0	628	0	0
T247	0	1741	0	0
T255	0	956	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	730	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	12	0	0
T5	25273	0	0	0
T6	497	0	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	1	0	0
T36	0	13	0	0
T39	0	6	0	0
T50	0	12	0	0
T59	0	15	0	0
T114	0	13	0	0
T187	0	16	0	0
T247	0	24	0	0
T255	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6151943	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	5294	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6154107	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	5295	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1560	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	12	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	17	0	0
T13	0	24	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	7	0	0
T30	0	13	0	0
T50	0	12	0	0
T57	0	26	0	0
T58	0	26	0	0
T59	0	15	0	0
T76	0	17	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1525	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	12	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	17	0	0
T13	0	24	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	1	0	0
T30	0	13	0	0
T50	0	12	0	0
T57	0	26	0	0
T58	0	26	0	0
T59	0	15	0	0
T76	0	17	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	730	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	12	0	0
T5	25273	0	0	0
T6	497	0	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	1	0	0
T36	0	13	0	0
T39	0	6	0	0
T50	0	12	0	0
T59	0	15	0	0
T114	0	13	0	0
T187	0	16	0	0
T247	0	24	0	0
T255	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	730	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	12	0	0
T5	25273	0	0	0
T6	497	0	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	1	0	0
T36	0	13	0	0
T39	0	6	0	0
T50	0	12	0	0
T59	0	15	0	0
T114	0	13	0	0
T187	0	16	0	0
T247	0	24	0	0
T255	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	66492	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	389	0	0
T5	25273	0	0	0
T6	497	0	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	3	0	0
T36	0	1704	0	0
T39	0	8	0	0
T50	0	2281	0	0
T59	0	1586	0	0
T114	0	20	0	0
T187	0	612	0	0
T247	0	1715	0	0
T255	0	937	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	646	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	12	0	0
T5	25273	0	0	0
T6	497	0	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	1	0	0
T36	0	11	0	0
T39	0	6	0	0
T50	0	10	0	0
T59	0	10	0	0
T114	0	13	0	0
T187	0	16	0	0
T247	0	22	0	0
T255	0	11	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T5,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T8,T79,T258
1	0	Covered	T61,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T9,T50
0	1	Covered	T5,T9,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T9,T50
1	-	Covered	T5,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T8,T9
DetectSt	168	Covered	T5,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T9,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T8,T9
DebounceSt->IdleSt	163	Covered	T8,T9,T12
DetectSt->IdleSt	186	Covered	T8,T79,T258
DetectSt->StableSt	191	Covered	T5,T9,T50
IdleSt->DebounceSt	148	Covered	T5,T8,T9
StableSt->IdleSt	206	Covered	T5,T9,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T9,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T8,T79,T258
DetectSt	-	-	-	-	0	1	-	Covered	T5,T9,T50
DetectSt	-	-	-	-	0	0	-	Covered	T5,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T5,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T5,T9,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	756	0	0
CntIncr_A	7234767	41791	0	0
CntNoWrap_A	7234767	6575745	0	0
DetectStDropOut_A	7234767	49	0	0
DetectedOut_A	7234767	13160	0	0
DetectedPulseOut_A	7234767	306	0	0
DisabledIdleSt_A	7234767	6212804	0	0
DisabledNoDetection_A	7234767	6214512	0	0
EnterDebounceSt_A	7234767	398	0	0
EnterDetectSt_A	7234767	359	0	0
EnterStableSt_A	7234767	306	0	0
PulseIsPulse_A	7234767	306	0	0
StayInStableSt	7234767	12823	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	274	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	756	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	14	0	0
T6	497	0	0	0
T8	0	5	0	0
T9	0	5	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	4	0	0
T37	0	20	0	0
T50	0	4	0	0
T59	0	10	0	0
T79	0	20	0	0
T92	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	41791	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	791	0	0
T6	497	0	0	0
T8	0	369	0	0
T9	0	275	0	0
T12	0	52	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	138	0	0
T37	0	520	0	0
T50	0	198	0	0
T59	0	415	0	0
T79	0	1504	0	0
T92	0	82	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6575745	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24803	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	49	0	0
T8	8737	2	0	0
T9	26122	0	0	0
T26	4461	0	0	0
T27	508	0	0	0
T29	4921	0	0	0
T54	733	0	0	0
T55	679	0	0	0
T60	414	0	0	0
T79	0	9	0	0
T106	0	11	0	0
T107	428	0	0	0
T115	402	0	0	0
T159	0	1	0	0
T197	0	3	0	0
T258	0	1	0	0
T259	0	5	0	0
T260	0	11	0	0
T261	0	2	0	0
T262	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	13160	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	363	0	0
T6	497	0	0	0
T9	0	68	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	82	0	0
T37	0	271	0	0
T38	0	23	0	0
T50	0	92	0	0
T59	0	197	0	0
T92	0	75	0	0
T247	0	144	0	0
T263	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	306	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	7	0	0
T6	497	0	0	0
T9	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	2	0	0
T37	0	10	0	0
T38	0	2	0	0
T50	0	2	0	0
T59	0	5	0	0
T92	0	1	0	0
T247	0	2	0	0
T263	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6212804	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	10896	0	0
T5	25273	20147	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6214512	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	10898	0	0
T5	25273	20147	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	398	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	7	0	0
T6	497	0	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	2	0	0
T37	0	10	0	0
T50	0	2	0	0
T59	0	5	0	0
T79	0	11	0	0
T92	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	359	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	7	0	0
T6	497	0	0	0
T8	0	2	0	0
T9	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	2	0	0
T37	0	10	0	0
T50	0	2	0	0
T59	0	5	0	0
T79	0	9	0	0
T92	0	1	0	0
T263	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	306	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	7	0	0
T6	497	0	0	0
T9	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	2	0	0
T37	0	10	0	0
T38	0	2	0	0
T50	0	2	0	0
T59	0	5	0	0
T92	0	1	0	0
T247	0	2	0	0
T263	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	306	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	7	0	0
T6	497	0	0	0
T9	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	2	0	0
T37	0	10	0	0
T38	0	2	0	0
T50	0	2	0	0
T59	0	5	0	0
T92	0	1	0	0
T247	0	2	0	0
T263	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	12823	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	356	0	0
T6	497	0	0	0
T9	0	66	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	80	0	0
T37	0	261	0	0
T38	0	21	0	0
T50	0	88	0	0
T59	0	187	0	0
T92	0	74	0	0
T247	0	142	0	0
T263	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	274	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	7	0	0
T6	497	0	0	0
T9	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	2	0	0
T37	0	10	0	0
T38	0	2	0	0
T92	0	1	0	0
T247	0	2	0	0
T255	0	1	0	0
T256	0	2	0	0
T263	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T29,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T30,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T29,T30
1	0	Covered	T4,T50,T10
1	1	Covered	T4,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T30,T57
0	1	Covered	T30,T57,T58
1	0	Covered	T59,T254,T131

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T50,T10
0	1	Covered	T4,T50,T10
1	0	Covered	T59

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T50,T10
1	-	Covered	T4,T50,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T29,T30
DetectSt	168	Covered	T4,T30,T57
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T50,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T30,T57
DebounceSt->IdleSt	163	Covered	T29,T61,T253
DetectSt->IdleSt	186	Covered	T30,T57,T58
DetectSt->StableSt	191	Covered	T4,T50,T10
IdleSt->DebounceSt	148	Covered	T4,T29,T30
StableSt->IdleSt	206	Covered	T4,T50,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T29,T30
0	1	Covered	T4,T29,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T30,T57
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T29,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T30,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T61,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T57,T58
DetectSt	-	-	-	-	0	1	-	Covered	T4,T50,T10
DetectSt	-	-	-	-	0	0	-	Covered	T4,T30,T57
StableSt	-	-	-	-	-	-	1	Covered	T4,T50,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T50,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	2598	0	0
CntIncr_A	7234767	84130	0	0
CntNoWrap_A	7234767	6573903	0	0
DetectStDropOut_A	7234767	411	0	0
DetectedOut_A	7234767	72590	0	0
DetectedPulseOut_A	7234767	761	0	0
DisabledIdleSt_A	7234767	6143656	0	0
DisabledNoDetection_A	7234767	6145799	0	0
EnterDebounceSt_A	7234767	1315	0	0
EnterDetectSt_A	7234767	1284	0	0
EnterStableSt_A	7234767	761	0	0
PulseIsPulse_A	7234767	761	0	0
StayInStableSt	7234767	71725	0	0
gen_high_event_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	656	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2598	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	12	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	28	0	0
T13	0	20	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	3	0	0
T30	0	48	0	0
T50	0	16	0	0
T57	0	54	0	0
T58	0	48	0	0
T59	0	24	0	0
T76	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	84130	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	534	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	756	0	0
T13	0	470	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	150	0	0
T30	0	1202	0	0
T50	0	872	0	0
T57	0	1351	0	0
T58	0	1488	0	0
T59	0	843	0	0
T76	0	425	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6573903	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11285	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	411	0	0
T10	8780	0	0	0
T11	12265	0	0	0
T28	1623	0	0	0
T30	5120	24	0	0
T50	21396	0	0	0
T57	5119	27	0	0
T58	5716	24	0	0
T59	0	5	0	0
T76	0	14	0	0
T95	0	8	0	0
T96	0	9	0	0
T98	0	10	0	0
T108	402	0	0	0
T109	424	0	0	0
T110	427	0	0	0
T254	0	1	0	0
T264	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	72590	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	169	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	1387	0	0
T13	0	1122	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T36	0	1472	0	0
T39	0	555	0	0
T50	0	656	0	0
T59	0	1	0	0
T97	0	591	0	0
T114	0	2323	0	0
T187	0	353	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	761	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	6	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	10	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T36	0	13	0	0
T39	0	16	0	0
T50	0	8	0	0
T59	0	1	0	0
T97	0	3	0	0
T114	0	30	0	0
T187	0	18	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6143656	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	5325	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6145799	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	5326	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1315	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	6	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	10	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	3	0	0
T30	0	24	0	0
T50	0	8	0	0
T57	0	27	0	0
T58	0	24	0	0
T59	0	12	0	0
T76	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1284	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	6	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	10	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T30	0	24	0	0
T50	0	8	0	0
T57	0	27	0	0
T58	0	24	0	0
T59	0	12	0	0
T76	0	14	0	0
T95	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	761	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	6	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	10	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T36	0	13	0	0
T39	0	16	0	0
T50	0	8	0	0
T59	0	1	0	0
T97	0	3	0	0
T114	0	30	0	0
T187	0	18	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	761	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	6	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	10	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T36	0	13	0	0
T39	0	16	0	0
T50	0	8	0	0
T59	0	1	0	0
T97	0	3	0	0
T114	0	30	0	0
T187	0	18	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	71725	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	163	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	1372	0	0
T13	0	1110	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T36	0	1457	0	0
T39	0	536	0	0
T50	0	647	0	0
T97	0	586	0	0
T114	0	2291	0	0
T187	0	335	0	0
T247	0	216	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	656	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	6	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	13	0	0
T13	0	8	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T36	0	11	0	0
T39	0	13	0	0
T50	0	7	0	0
T97	0	1	0	0
T114	0	28	0	0
T187	0	18	0	0
T247	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T5,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T50
0	1	Covered	T8,T79,T159
1	0	Covered	T61,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T50,T10
0	1	Covered	T9,T10,T13
1	0	Covered	T61,T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T50,T10
1	-	Covered	T9,T10,T13

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T8,T9
DetectSt	168	Covered	T8,T9,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T50,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T50
DebounceSt->IdleSt	163	Covered	T5,T8,T9
DetectSt->IdleSt	186	Covered	T8,T79,T159
DetectSt->StableSt	191	Covered	T9,T50,T10
IdleSt->DebounceSt	148	Covered	T5,T8,T9
StableSt->IdleSt	206	Covered	T9,T50,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T50
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T8,T9
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T8,T79,T159
DetectSt	-	-	-	-	0	1	-	Covered	T9,T50,T10
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T50
StableSt	-	-	-	-	-	-	1	Covered	T9,T10,T13
StableSt	-	-	-	-	-	-	0	Covered	T9,T50,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	801	0	0
CntIncr_A	7234767	45412	0	0
CntNoWrap_A	7234767	6575700	0	0
DetectStDropOut_A	7234767	57	0	0
DetectedOut_A	7234767	15946	0	0
DetectedPulseOut_A	7234767	312	0	0
DisabledIdleSt_A	7234767	6197477	0	0
DisabledNoDetection_A	7234767	6199142	0	0
EnterDebounceSt_A	7234767	429	0	0
EnterDetectSt_A	7234767	373	0	0
EnterStableSt_A	7234767	312	0	0
PulseIsPulse_A	7234767	312	0	0
StayInStableSt	7234767	15609	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	284	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	801	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	1	0	0
T6	497	0	0	0
T8	0	7	0	0
T9	0	13	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	0	2	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	4	0	0
T39	0	4	0	0
T50	0	2	0	0
T97	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	45412	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	87	0	0
T6	497	0	0	0
T8	0	517	0	0
T9	0	835	0	0
T10	0	61	0	0
T12	0	52	0	0
T13	0	53	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	160	0	0
T39	0	92	0	0
T50	0	87	0	0
T97	0	148	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6575700	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11297	0	0
T5	25273	24816	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	57	0	0
T8	8737	3	0	0
T9	26122	0	0	0
T26	4461	0	0	0
T27	508	0	0	0
T29	4921	0	0	0
T54	733	0	0	0
T55	679	0	0	0
T60	414	0	0	0
T79	0	4	0	0
T99	0	4	0	0
T102	0	3	0	0
T107	428	0	0	0
T115	402	0	0	0
T159	0	3	0	0
T172	0	2	0	0
T197	0	1	0	0
T265	0	6	0	0
T266	0	2	0	0
T267	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	15946	0	0
T9	26122	58	0	0
T10	0	56	0	0
T13	0	68	0	0
T28	1623	0	0	0
T30	5120	0	0	0
T36	0	60	0	0
T39	0	101	0	0
T50	0	57	0	0
T54	733	0	0	0
T55	679	0	0	0
T56	6048	0	0	0
T57	5119	0	0	0
T58	5716	0	0	0
T92	0	19	0	0
T97	0	119	0	0
T108	402	0	0	0
T109	424	0	0	0
T114	0	155	0	0
T263	0	368	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	312	0	0
T9	26122	6	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	1623	0	0	0
T30	5120	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T50	0	1	0	0
T54	733	0	0	0
T55	679	0	0	0
T56	6048	0	0	0
T57	5119	0	0	0
T58	5716	0	0	0
T92	0	1	0	0
T97	0	2	0	0
T108	402	0	0	0
T109	424	0	0	0
T114	0	2	0	0
T263	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6197477	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11127	0	0
T5	25273	20147	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6199142	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11129	0	0
T5	25273	20147	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	429	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	1	0	0
T6	497	0	0	0
T8	0	4	0	0
T9	0	7	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T50	0	1	0	0
T97	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	373	0	0
T8	8737	3	0	0
T9	26122	6	0	0
T10	0	1	0	0
T13	0	1	0	0
T26	4461	0	0	0
T27	508	0	0	0
T29	4921	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T50	0	1	0	0
T54	733	0	0	0
T55	679	0	0	0
T60	414	0	0	0
T92	0	1	0	0
T97	0	2	0	0
T107	428	0	0	0
T114	0	2	0	0
T115	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	312	0	0
T9	26122	6	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	1623	0	0	0
T30	5120	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T50	0	1	0	0
T54	733	0	0	0
T55	679	0	0	0
T56	6048	0	0	0
T57	5119	0	0	0
T58	5716	0	0	0
T92	0	1	0	0
T97	0	2	0	0
T108	402	0	0	0
T109	424	0	0	0
T114	0	2	0	0
T263	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	312	0	0
T9	26122	6	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	1623	0	0	0
T30	5120	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T50	0	1	0	0
T54	733	0	0	0
T55	679	0	0	0
T56	6048	0	0	0
T57	5119	0	0	0
T58	5716	0	0	0
T92	0	1	0	0
T97	0	2	0	0
T108	402	0	0	0
T109	424	0	0	0
T114	0	2	0	0
T263	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	15609	0	0
T9	26122	52	0	0
T10	0	55	0	0
T13	0	67	0	0
T28	1623	0	0	0
T30	5120	0	0	0
T36	0	58	0	0
T39	0	99	0	0
T50	0	55	0	0
T54	733	0	0	0
T55	679	0	0	0
T56	6048	0	0	0
T57	5119	0	0	0
T58	5716	0	0	0
T92	0	18	0	0
T97	0	117	0	0
T108	402	0	0	0
T109	424	0	0	0
T114	0	152	0	0
T263	0	358	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	284	0	0
T9	26122	6	0	0
T10	0	1	0	0
T13	0	1	0	0
T28	1623	0	0	0
T30	5120	0	0	0
T36	0	2	0	0
T39	0	2	0	0
T54	733	0	0	0
T55	679	0	0	0
T56	6048	0	0	0
T57	5119	0	0	0
T58	5716	0	0	0
T92	0	1	0	0
T97	0	2	0	0
T108	402	0	0	0
T109	424	0	0	0
T114	0	1	0	0
T255	0	2	0	0
T263	0	10	0	0