Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T29,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T29,T30
1	0	Covered	T4,T50,T10
1	1	Covered	T4,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T29,T30
0	1	Covered	T30,T57,T58
1	0	Covered	T50,T39,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T29,T10
0	1	Covered	T4,T29,T10
1	0	Covered	T268

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T29,T10
1	-	Covered	T4,T29,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T29,T30
DetectSt	168	Covered	T4,T29,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T4,T29,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T29,T30
DebounceSt->IdleSt	163	Covered	T29,T61,T253
DetectSt->IdleSt	186	Covered	T30,T57,T58
DetectSt->StableSt	191	Covered	T4,T29,T10
IdleSt->DebounceSt	148	Covered	T4,T29,T30
StableSt->IdleSt	206	Covered	T4,T29,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T29,T30
0	1	Covered	T4,T29,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T29,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T4,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T29,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T29,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T29,T61,T253
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T57,T58
DetectSt	-	-	-	-	0	1	-	Covered	T4,T29,T10
DetectSt	-	-	-	-	0	0	-	Covered	T4,T29,T30
StableSt	-	-	-	-	-	-	1	Covered	T4,T29,T10
StableSt	-	-	-	-	-	-	0	Covered	T4,T29,T10
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	2914	0	0
CntIncr_A	7234767	100675	0	0
CntNoWrap_A	7234767	6573587	0	0
DetectStDropOut_A	7234767	387	0	0
DetectedOut_A	7234767	77869	0	0
DetectedPulseOut_A	7234767	869	0	0
DisabledIdleSt_A	7234767	6140194	0	0
DisabledNoDetection_A	7234767	6142332	0	0
EnterDebounceSt_A	7234767	1474	0	0
EnterDetectSt_A	7234767	1441	0	0
EnterStableSt_A	7234767	869	0	0
PulseIsPulse_A	7234767	869	0	0
StayInStableSt	7234767	76890	0	0
gen_high_event_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	756	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	2914	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	54	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	28	0	0
T13	0	58	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	22	0	0
T30	0	38	0	0
T50	0	20	0	0
T57	0	24	0	0
T58	0	18	0	0
T59	0	22	0	0
T76	0	24	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	100675	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	2457	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	700	0	0
T13	0	1566	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	900	0	0
T30	0	946	0	0
T50	0	1705	0	0
T57	0	596	0	0
T58	0	555	0	0
T59	0	594	0	0
T76	0	368	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6573587	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11243	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	387	0	0
T10	8780	0	0	0
T11	12265	0	0	0
T28	1623	0	0	0
T30	5120	19	0	0
T36	0	4	0	0
T50	21396	2	0	0
T57	5119	12	0	0
T58	5716	9	0	0
T76	0	12	0	0
T82	0	11	0	0
T95	0	5	0	0
T96	0	26	0	0
T108	402	0	0	0
T109	424	0	0	0
T110	427	0	0	0
T247	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	77869	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1928	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	1443	0	0
T13	0	2408	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	181	0	0
T59	0	1078	0	0
T97	0	2699	0	0
T114	0	203	0	0
T187	0	2965	0	0
T254	0	1356	0	0
T255	0	792	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	869	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	29	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	5	0	0
T59	0	11	0	0
T97	0	25	0	0
T114	0	12	0	0
T187	0	31	0	0
T254	0	24	0	0
T255	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6140194	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	4047	0	0
T5	25273	24817	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6142332	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	4047	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1474	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	29	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	17	0	0
T30	0	19	0	0
T50	0	10	0	0
T57	0	12	0	0
T58	0	9	0	0
T59	0	11	0	0
T76	0	12	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	1441	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	29	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	5	0	0
T30	0	19	0	0
T50	0	10	0	0
T57	0	12	0	0
T58	0	9	0	0
T59	0	11	0	0
T76	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	869	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	29	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	5	0	0
T59	0	11	0	0
T97	0	25	0	0
T114	0	12	0	0
T187	0	31	0	0
T254	0	24	0	0
T255	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	869	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	27	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	14	0	0
T13	0	29	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	5	0	0
T59	0	11	0	0
T97	0	25	0	0
T114	0	12	0	0
T187	0	31	0	0
T254	0	24	0	0
T255	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	76890	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1900	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	1428	0	0
T13	0	2374	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	176	0	0
T59	0	1064	0	0
T97	0	2667	0	0
T114	0	190	0	0
T187	0	2934	0	0
T254	0	1330	0	0
T255	0	780	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	756	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	26	0	0
T5	25273	0	0	0
T6	497	0	0	0
T10	0	13	0	0
T13	0	24	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T29	0	5	0	0
T59	0	8	0	0
T97	0	18	0	0
T114	0	11	0	0
T187	0	31	0	0
T254	0	22	0	0
T255	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T8
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T5,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T8
1	0	Covered	T4,T5,T8
1	1	Covered	T4,T5,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T92,T269,T270
1	0	Covered	T61,T80

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T9
0	1	Covered	T5,T8,T9
1	0	Covered	T80

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T8,T9
1	-	Covered	T5,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T5,T8
DetectSt	168	Covered	T5,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T8,T9
DebounceSt->IdleSt	163	Covered	T4,T8,T11
DetectSt->IdleSt	186	Covered	T92,T269,T61
DetectSt->StableSt	191	Covered	T5,T8,T9
IdleSt->DebounceSt	148	Covered	T4,T5,T8
StableSt->IdleSt	206	Covered	T5,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T5,T8
0	1	Covered	T4,T5,T8
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T5,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T61,T80
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T8,T92
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T5,T8
DetectSt	-	-	-	-	1	-	-	Covered	T92,T269,T61
DetectSt	-	-	-	-	0	1	-	Covered	T5,T8,T9
DetectSt	-	-	-	-	0	0	-	Covered	T5,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T5,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T5,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7234767	817	0	0
CntIncr_A	7234767	49454	0	0
CntNoWrap_A	7234767	6575684	0	0
DetectStDropOut_A	7234767	54	0	0
DetectedOut_A	7234767	16733	0	0
DetectedPulseOut_A	7234767	331	0	0
DisabledIdleSt_A	7234767	6190820	0	0
DisabledNoDetection_A	7234767	6192472	0	0
EnterDebounceSt_A	7234767	430	0	0
EnterDetectSt_A	7234767	389	0	0
EnterStableSt_A	7234767	331	0	0
PulseIsPulse_A	7234767	331	0	0
StayInStableSt	7234767	16376	0	0
gen_high_level_sva.HighLevelEvent_A	7234767	6578836	0	0
gen_not_sticky_sva.StableStDropOut_A	7234767	302	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	817	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1	0	0
T5	25273	4	0	0
T6	497	0	0	0
T8	0	4	0	0
T9	0	8	0	0
T10	0	2	0	0
T12	0	2	0	0
T13	0	10	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T59	0	6	0	0
T92	0	26	0	0
T97	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	49454	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	42	0	0
T5	25273	254	0	0
T6	497	0	0	0
T8	0	211	0	0
T9	0	384	0	0
T10	0	70	0	0
T11	0	88	0	0
T12	0	94	0	0
T13	0	410	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T59	0	159	0	0
T97	0	285	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6575684	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	11296	0	0
T5	25273	24813	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	54	0	0
T43	709	0	0	0
T44	775	0	0	0
T75	6848	0	0	0
T92	35436	12	0	0
T101	0	6	0	0
T105	0	4	0	0
T113	468	0	0	0
T114	14013	0	0	0
T153	885	0	0	0
T154	416	0	0	0
T155	404	0	0	0
T156	524	0	0	0
T197	0	6	0	0
T199	0	6	0	0
T266	0	1	0	0
T269	0	12	0	0
T270	0	2	0	0
T271	0	1	0	0
T272	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	16733	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	77	0	0
T6	497	0	0	0
T8	0	73	0	0
T9	0	165	0	0
T10	0	48	0	0
T12	0	44	0	0
T13	0	193	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T59	0	207	0	0
T79	0	256	0	0
T97	0	380	0	0
T114	0	97	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	331	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	2	0	0
T6	497	0	0	0
T8	0	1	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T59	0	3	0	0
T79	0	4	0	0
T97	0	5	0	0
T114	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6190820	0	0
T1	274961	274560	0	0
T2	649	248	0	0
T4	11702	9370	0	0
T5	25273	20147	0	0
T6	497	96	0	0
T14	408	7	0	0
T15	409	8	0	0
T16	425	24	0	0
T17	37916	37515	0	0
T18	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6192472	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	9371	0	0
T5	25273	20147	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	430	0	0
T1	274961	0	0	0
T2	649	0	0	0
T4	11702	1	0	0
T5	25273	2	0	0
T6	497	0	0	0
T8	0	3	0	0
T9	0	4	0	0
T10	0	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T59	0	3	0	0
T97	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	389	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	2	0	0
T6	497	0	0	0
T8	0	1	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T59	0	3	0	0
T92	0	12	0	0
T97	0	5	0	0
T114	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	331	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	2	0	0
T6	497	0	0	0
T8	0	1	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T59	0	3	0	0
T79	0	4	0	0
T97	0	5	0	0
T114	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	331	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	2	0	0
T6	497	0	0	0
T8	0	1	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T59	0	3	0	0
T79	0	4	0	0
T97	0	5	0	0
T114	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	16376	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	75	0	0
T6	497	0	0	0
T8	0	72	0	0
T9	0	161	0	0
T10	0	47	0	0
T12	0	43	0	0
T13	0	188	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T59	0	201	0	0
T79	0	252	0	0
T97	0	375	0	0
T114	0	96	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	6578836	0	0
T1	274961	274561	0	0
T2	649	249	0	0
T4	11702	11299	0	0
T5	25273	24827	0	0
T6	497	97	0	0
T14	408	8	0	0
T15	409	9	0	0
T16	425	25	0	0
T17	37916	37516	0	0
T18	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7234767	302	0	0
T1	274961	0	0	0
T2	649	0	0	0
T5	25273	2	0	0
T6	497	0	0	0
T8	0	1	0	0
T9	0	4	0	0
T10	0	1	0	0
T12	0	1	0	0
T13	0	5	0	0
T14	408	0	0	0
T15	409	0	0	0
T16	425	0	0	0
T17	37916	0	0	0
T18	427	0	0	0
T19	694	0	0	0
T79	0	4	0	0
T97	0	5	0	0
T114	0	1	0	0
T263	0	2	0	0