Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1370416554	10626	0	0
auto_block_debounce_ctl_rd_A	1370416554	2018	0	0
auto_block_out_ctl_rd_A	1370416554	2474	0	0
com_det_ctl_0_rd_A	1370416554	3675	0	0
com_det_ctl_1_rd_A	1370416554	3709	0	0
com_det_ctl_2_rd_A	1370416554	3790	0	0
com_det_ctl_3_rd_A	1370416554	3665	0	0
com_out_ctl_0_rd_A	1370416554	3848	0	0
com_out_ctl_1_rd_A	1370416554	3817	0	0
com_out_ctl_2_rd_A	1370416554	4213	0	0
com_out_ctl_3_rd_A	1370416554	4058	0	0
com_pre_det_ctl_0_rd_A	1370416554	1547	0	0
com_pre_det_ctl_1_rd_A	1370416554	1653	0	0
com_pre_det_ctl_2_rd_A	1370416554	1587	0	0
com_pre_det_ctl_3_rd_A	1370416554	1512	0	0
com_pre_sel_ctl_0_rd_A	1370416554	4344	0	0
com_pre_sel_ctl_1_rd_A	1370416554	4087	0	0
com_pre_sel_ctl_2_rd_A	1370416554	4210	0	0
com_pre_sel_ctl_3_rd_A	1370416554	4076	0	0
com_sel_ctl_0_rd_A	1370416554	4061	0	0
com_sel_ctl_1_rd_A	1370416554	4071	0	0
com_sel_ctl_2_rd_A	1370416554	4020	0	0
com_sel_ctl_3_rd_A	1370416554	4051	0	0
ec_rst_ctl_rd_A	1370416554	2608	0	0
intr_enable_rd_A	1370416554	2272	0	0
key_intr_ctl_rd_A	1370416554	3082	0	0
key_intr_debounce_ctl_rd_A	1370416554	1688	0	0
key_invert_ctl_rd_A	1370416554	5010	0	0
pin_allowed_ctl_rd_A	1370416554	4770	0	0
pin_out_ctl_rd_A	1370416554	4017	0	0
pin_out_value_rd_A	1370416554	3977	0	0
regwen_rd_A	1370416554	1631	0	0
ulp_ac_debounce_ctl_rd_A	1370416554	1681	0	0
ulp_ctl_rd_A	1370416554	1811	0	0
ulp_lid_debounce_ctl_rd_A	1370416554	1816	0	0
ulp_pwrb_debounce_ctl_rd_A	1370416554	1770	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	10626	0	0
T9	125381	0	0	0
T11	0	4	0	0
T12	0	18	0	0
T26	107072	6	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T64	0	8	0	0
T71	0	4	0	0
T75	0	2	0	0
T130	0	15	0	0
T158	0	11	0	0
T159	0	26	0	0
T296	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	2018	0	0
T3	126864	0	0	0
T7	57973	0	0	0
T11	0	6	0	0
T17	910005	12	0	0
T18	102586	0	0	0
T19	83428	0	0	0
T20	342999	0	0	0
T24	62108	0	0	0
T26	0	21	0	0
T46	0	6	0	0
T51	324729	0	0	0
T52	79325	0	0	0
T53	123006	0	0	0
T70	0	12	0	0
T89	0	27	0	0
T188	0	11	0	0
T296	0	21	0	0
T297	0	7	0	0
T298	0	6	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	2474	0	0
T3	126864	0	0	0
T7	57973	0	0	0
T11	0	10	0	0
T17	910005	12	0	0
T18	102586	0	0	0
T19	83428	0	0	0
T20	342999	0	0	0
T24	62108	0	0	0
T26	0	18	0	0
T46	0	13	0	0
T51	324729	0	0	0
T52	79325	0	0	0
T53	123006	0	0	0
T70	0	14	0	0
T89	0	34	0	0
T188	0	7	0	0
T296	0	26	0	0
T297	0	14	0	0
T298	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3675	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	48	0	0
T5	120054	74	0	0
T6	121873	0	0	0
T9	0	54	0	0
T10	0	22	0	0
T11	0	9	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	9	0	0
T79	0	33	0	0
T97	0	68	0	0
T187	0	11	0	0
T254	0	36	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3709	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	59	0	0
T5	120054	50	0	0
T6	121873	0	0	0
T9	0	59	0	0
T10	0	25	0	0
T11	0	42	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	10	0	0
T79	0	42	0	0
T97	0	53	0	0
T187	0	13	0	0
T254	0	38	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3790	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	61	0	0
T5	120054	87	0	0
T6	121873	0	0	0
T9	0	86	0	0
T10	0	27	0	0
T11	0	28	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	8	0	0
T79	0	43	0	0
T97	0	59	0	0
T187	0	32	0	0
T254	0	36	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3665	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	55	0	0
T5	120054	68	0	0
T6	121873	0	0	0
T9	0	94	0	0
T10	0	35	0	0
T11	0	27	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	11	0	0
T79	0	35	0	0
T97	0	54	0	0
T187	0	22	0	0
T254	0	43	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3848	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	50	0	0
T5	120054	72	0	0
T6	121873	0	0	0
T9	0	55	0	0
T10	0	15	0	0
T11	0	36	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	14	0	0
T79	0	43	0	0
T97	0	48	0	0
T187	0	30	0	0
T254	0	41	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3817	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	51	0	0
T5	120054	79	0	0
T6	121873	0	0	0
T9	0	75	0	0
T10	0	36	0	0
T11	0	21	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	7	0	0
T79	0	44	0	0
T97	0	55	0	0
T187	0	22	0	0
T254	0	35	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4213	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	36	0	0
T5	120054	77	0	0
T6	121873	0	0	0
T9	0	86	0	0
T10	0	35	0	0
T11	0	32	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	12	0	0
T79	0	49	0	0
T97	0	75	0	0
T187	0	23	0	0
T254	0	37	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4058	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	49	0	0
T5	120054	72	0	0
T6	121873	0	0	0
T9	0	67	0	0
T10	0	20	0	0
T11	0	29	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	14	0	0
T79	0	32	0	0
T97	0	61	0	0
T187	0	32	0	0
T254	0	37	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1547	0	0
T11	607056	28	0	0
T12	325252	0	0	0
T35	214592	0	0	0
T59	221872	0	0	0
T68	61711	0	0	0
T69	317532	0	0	0
T72	125865	0	0	0
T76	202072	0	0	0
T89	0	26	0	0
T104	0	21	0	0
T111	342923	0	0	0
T112	100921	0	0	0
T120	0	27	0	0
T143	0	13	0	0
T201	0	3	0	0
T296	0	36	0	0
T299	0	22	0	0
T300	0	17	0	0
T301	0	12	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1653	0	0
T9	125381	0	0	0
T11	0	24	0	0
T26	107072	12	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T89	0	19	0	0
T104	0	21	0	0
T120	0	21	0	0
T201	0	28	0	0
T296	0	17	0	0
T299	0	18	0	0
T300	0	12	0	0
T301	0	12	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1587	0	0
T9	125381	0	0	0
T11	0	8	0	0
T26	107072	14	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T89	0	9	0	0
T104	0	28	0	0
T120	0	40	0	0
T201	0	8	0	0
T296	0	22	0	0
T299	0	19	0	0
T300	0	10	0	0
T301	0	9	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1512	0	0
T9	125381	0	0	0
T11	0	18	0	0
T26	107072	5	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T89	0	19	0	0
T104	0	7	0	0
T120	0	27	0	0
T201	0	16	0	0
T296	0	26	0	0
T299	0	15	0	0
T300	0	11	0	0
T301	0	22	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4344	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	52	0	0
T5	120054	93	0	0
T6	121873	0	0	0
T9	0	84	0	0
T10	0	34	0	0
T11	0	11	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	12	0	0
T79	0	30	0	0
T97	0	59	0	0
T187	0	27	0	0
T254	0	43	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4087	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	29	0	0
T5	120054	80	0	0
T6	121873	0	0	0
T9	0	72	0	0
T10	0	20	0	0
T11	0	26	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	16	0	0
T79	0	69	0	0
T97	0	46	0	0
T187	0	22	0	0
T254	0	41	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4210	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	31	0	0
T5	120054	63	0	0
T6	121873	0	0	0
T9	0	82	0	0
T10	0	23	0	0
T11	0	19	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	13	0	0
T79	0	30	0	0
T97	0	76	0	0
T187	0	18	0	0
T254	0	44	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4076	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	42	0	0
T5	120054	75	0	0
T6	121873	0	0	0
T9	0	65	0	0
T10	0	42	0	0
T11	0	50	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	19	0	0
T79	0	29	0	0
T97	0	48	0	0
T187	0	13	0	0
T254	0	42	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4061	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	51	0	0
T5	120054	95	0	0
T6	121873	0	0	0
T9	0	56	0	0
T10	0	18	0	0
T11	0	15	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T79	0	33	0	0
T97	0	52	0	0
T187	0	48	0	0
T254	0	28	0	0
T296	0	37	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4071	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	63	0	0
T5	120054	68	0	0
T6	121873	0	0	0
T9	0	58	0	0
T10	0	17	0	0
T11	0	18	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	12	0	0
T79	0	39	0	0
T97	0	57	0	0
T187	0	27	0	0
T254	0	43	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4020	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	47	0	0
T5	120054	77	0	0
T6	121873	0	0	0
T9	0	81	0	0
T10	0	16	0	0
T11	0	20	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	11	0	0
T79	0	32	0	0
T97	0	65	0	0
T187	0	29	0	0
T254	0	23	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4051	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	30	0	0
T5	120054	62	0	0
T6	121873	0	0	0
T9	0	81	0	0
T10	0	18	0	0
T11	0	29	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	11	0	0
T79	0	30	0	0
T97	0	67	0	0
T187	0	24	0	0
T254	0	54	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	2608	0	0
T1	121708	0	0	0
T2	29243	0	0	0
T4	140438	6	0	0
T5	120054	36	0	0
T6	121873	0	0	0
T9	0	54	0	0
T11	0	37	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T26	0	19	0	0
T79	0	13	0	0
T97	0	24	0	0
T153	0	2	0	0
T187	0	2	0	0
T254	0	11	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	2272	0	0
T9	125381	0	0	0
T11	0	25	0	0
T26	107072	20	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T84	0	11	0	0
T89	0	13	0	0
T120	0	33	0	0
T296	0	32	0	0
T299	0	21	0	0
T300	0	31	0	0
T301	0	22	0	0
T302	0	17	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3082	0	0
T2	29243	5	0	0
T3	126864	0	0	0
T11	0	32	0	0
T14	48955	0	0	0
T15	26646	0	0	0
T16	42596	0	0	0
T17	910005	0	0	0
T18	102586	0	0	0
T19	83428	0	0	0
T20	342999	0	0	0
T24	62108	0	0	0
T26	0	10	0	0
T41	0	1	0	0
T46	0	3	0	0
T49	0	5	0	0
T135	0	4	0	0
T157	0	2	0	0
T203	0	1	0	0
T296	0	21	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1688	0	0
T9	125381	0	0	0
T11	0	20	0	0
T26	107072	18	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T89	0	15	0	0
T104	0	30	0	0
T120	0	34	0	0
T201	0	11	0	0
T296	0	11	0	0
T299	0	31	0	0
T300	0	18	0	0
T301	0	8	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	5010	0	0
T7	57973	0	0	0
T8	428153	0	0	0
T11	0	10	0	0
T24	62108	39	0	0
T25	243800	0	0	0
T26	107072	75	0	0
T46	0	65	0	0
T51	324729	0	0	0
T52	79325	0	0	0
T53	123006	0	0	0
T70	0	85	0	0
T107	51349	0	0	0
T115	201151	0	0	0
T149	0	71	0	0
T229	0	31	0	0
T293	0	59	0	0
T303	0	64	0	0
T304	0	42	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4770	0	0
T9	125381	0	0	0
T11	0	124	0	0
T26	107072	14	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T70	0	74	0	0
T89	0	148	0	0
T147	0	77	0	0
T203	0	38	0	0
T296	0	23	0	0
T305	0	81	0	0
T306	0	82	0	0
T307	0	46	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	4017	0	0
T9	125381	0	0	0
T11	0	154	0	0
T26	107072	11	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T70	0	38	0	0
T89	0	170	0	0
T147	0	69	0	0
T203	0	38	0	0
T296	0	9	0	0
T305	0	72	0	0
T306	0	55	0	0
T307	0	37	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	3977	0	0
T9	125381	0	0	0
T11	0	165	0	0
T26	107072	9	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T70	0	106	0	0
T89	0	146	0	0
T147	0	86	0	0
T203	0	53	0	0
T296	0	28	0	0
T305	0	58	0	0
T306	0	54	0	0
T307	0	57	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1631	0	0
T9	125381	0	0	0
T11	0	8	0	0
T26	107072	9	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T89	0	28	0	0
T104	0	21	0	0
T120	0	22	0	0
T201	0	9	0	0
T296	0	20	0	0
T299	0	16	0	0
T300	0	21	0	0
T301	0	6	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1681	0	0
T9	125381	0	0	0
T11	0	33	0	0
T26	107072	10	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T35	0	15	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T62	0	5	0	0
T66	0	9	0	0
T78	0	9	0	0
T89	0	29	0	0
T116	0	8	0	0
T296	0	19	0	0
T308	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1811	0	0
T9	125381	0	0	0
T11	0	16	0	0
T26	107072	12	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T35	0	10	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T62	0	6	0	0
T66	0	8	0	0
T78	0	14	0	0
T116	0	2	0	0
T118	0	9	0	0
T296	0	35	0	0
T308	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1816	0	0
T9	125381	0	0	0
T11	0	22	0	0
T26	107072	8	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T35	0	11	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T66	0	5	0	0
T78	0	10	0	0
T89	0	31	0	0
T116	0	13	0	0
T118	0	2	0	0
T296	0	27	0	0
T308	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1370416554	1770	0	0
T9	125381	0	0	0
T11	0	17	0	0
T26	107072	10	0	0
T27	53408	0	0	0
T29	590625	0	0	0
T30	588892	0	0	0
T35	0	8	0	0
T54	91678	0	0	0
T55	37400	0	0	0
T56	108878	0	0	0
T57	716735	0	0	0
T60	39369	0	0	0
T62	0	2	0	0
T66	0	9	0	0
T78	0	5	0	0
T89	0	30	0	0
T116	0	13	0	0
T296	0	22	0	0
T309	0	6	0	0