Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T46,T32,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T46,T32

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T46,T32,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T46,T32
1	0	Covered	T4,T5,T2
1	1	Covered	T10,T46,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T46,T32,T47
0	1	Covered	T39,T103,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T47,T49
0	1	Covered	T46,T32,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T47,T49
1	-	Covered	T46,T32,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T46,T32
DetectSt	168	Covered	T46,T32,T47
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T46,T32,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T46,T32,T47
DebounceSt->IdleSt	163	Covered	T10,T32,T48
DetectSt->IdleSt	186	Covered	T39,T103,T104
DetectSt->StableSt	191	Covered	T46,T32,T47
IdleSt->DebounceSt	148	Covered	T10,T46,T32
StableSt->IdleSt	206	Covered	T46,T32,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T46,T32,T47
0	1	Covered	T10,T46,T32
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T46,T32,T47
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T46,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T46,T32,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T122,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T46,T32
DetectSt	-	-	-	-	1	-	-	Covered	T39,T103,T104
DetectSt	-	-	-	-	0	1	-	Covered	T46,T32,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T46,T32,T47
StableSt	-	-	-	-	-	-	0	Covered	T32,T47,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	290	0	0
CntIncr_A	8699631	200226	0	0
CntNoWrap_A	8699631	8017365	0	0
DetectStDropOut_A	8699631	4	0	0
DetectedOut_A	8699631	764	0	0
DetectedPulseOut_A	8699631	128	0	0
DisabledIdleSt_A	8699631	7810691	0	0
DisabledNoDetection_A	8699631	7813073	0	0
EnterDebounceSt_A	8699631	162	0	0
EnterDetectSt_A	8699631	132	0	0
EnterStableSt_A	8699631	128	0	0
PulseIsPulse_A	8699631	128	0	0
StayInStableSt	8699631	636	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	7188	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	128	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	290	0	0
T32	17946	2	0	0
T37	721	0	0	0
T39	0	6	0	0
T42	0	8	0	0
T44	11547	0	0	0
T46	3032	2	0	0
T47	0	4	0	0
T48	0	3	0	0
T49	0	6	0	0
T51	0	2	0	0
T52	0	4	0	0
T59	201326	0	0	0
T65	0	8	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	200226	0	0
T10	196046	917	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T32	0	5884	0	0
T34	20386	0	0	0
T39	0	19116	0	0
T42	0	208	0	0
T46	0	15	0	0
T47	0	176	0	0
T48	0	90	0	0
T49	0	49	0	0
T51	0	40	0	0
T52	0	105	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017365	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	4	0	0
T39	26418	1	0	0
T42	13233	0	0	0
T65	11296	0	0	0
T75	1330	0	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T109	525	0	0	0
T110	416	0	0	0
T111	608	0	0	0
T112	513	0	0	0
T113	406	0	0	0
T114	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	764	0	0
T32	17946	2	0	0
T37	721	0	0	0
T39	0	6	0	0
T42	0	14	0	0
T44	11547	0	0	0
T46	3032	1	0	0
T47	0	20	0	0
T48	0	1	0	0
T49	0	13	0	0
T51	0	9	0	0
T52	0	12	0	0
T59	201326	0	0	0
T65	0	28	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	128	0	0
T32	17946	1	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	0	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	2	0	0
T59	201326	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7810691	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7813073	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	162	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T32	0	2	0	0
T34	20386	0	0	0
T39	0	4	0	0
T42	0	4	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	132	0	0
T32	17946	1	0	0
T37	721	0	0	0
T39	0	3	0	0
T42	0	4	0	0
T44	11547	0	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	2	0	0
T59	201326	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	128	0	0
T32	17946	1	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	0	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	2	0	0
T59	201326	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	128	0	0
T32	17946	1	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	0	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	2	0	0
T59	201326	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	636	0	0
T23	386866	0	0	0
T32	17946	1	0	0
T37	721	0	0	0
T39	0	4	0	0
T42	0	10	0	0
T47	808	18	0	0
T48	695	0	0	0
T49	0	10	0	0
T51	0	8	0	0
T52	0	10	0	0
T59	201326	0	0	0
T65	0	24	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T117	0	3	0	0
T118	0	26	0	0
T119	503	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7188	0	0
T1	545	0	0	0
T2	9573	14	0	0
T3	949	4	0	0
T4	31438	11	0	0
T5	521	6	0	0
T6	14245	27	0	0
T7	1276	5	0	0
T8	0	1	0	0
T13	502	5	0	0
T14	417	1	0	0
T15	472	0	0	0
T61	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	128	0	0
T32	17946	1	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	0	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T51	0	1	0	0
T52	0	2	0	0
T59	201326	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T23
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T38
0	1	Covered	T60,T75,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T38
0	1	Unreachable
1	0	Covered	T3,T23,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T23
DetectSt	168	Covered	T3,T23,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T23,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T23,T38
DebounceSt->IdleSt	163	Covered	T7,T60,T75
DetectSt->IdleSt	186	Covered	T60,T75,T90
DetectSt->StableSt	191	Covered	T3,T23,T38
IdleSt->DebounceSt	148	Covered	T3,T7,T23
StableSt->IdleSt	206	Covered	T3,T23,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T23
0	1	Covered	T3,T7,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T23,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T23,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T60,T75
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T23
DetectSt	-	-	-	-	1	-	-	Covered	T60,T75,T90
DetectSt	-	-	-	-	0	1	-	Covered	T3,T23,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T23,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T23,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	197	0	0
CntIncr_A	8699631	116615	0	0
CntNoWrap_A	8699631	8017458	0	0
DetectStDropOut_A	8699631	19	0	0
DetectedOut_A	8699631	513799	0	0
DetectedPulseOut_A	8699631	56	0	0
DisabledIdleSt_A	8699631	6692839	0	0
DisabledNoDetection_A	8699631	6695267	0	0
EnterDebounceSt_A	8699631	123	0	0
EnterDetectSt_A	8699631	75	0	0
EnterStableSt_A	8699631	56	0	0
PulseIsPulse_A	8699631	56	0	0
StayInStableSt	8699631	513743	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	7188	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_sticky_sva.StableStDropOut_A	8699631	308468	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	197	0	0
T3	949	2	0	0
T6	14245	0	0	0
T7	1276	5	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	2	0	0
T26	507	0	0	0
T38	0	2	0	0
T42	0	2	0	0
T58	407	0	0	0
T60	0	3	0	0
T61	422	0	0	0
T65	0	2	0	0
T75	0	10	0	0
T76	0	2	0	0
T77	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	116615	0	0
T3	949	67	0	0
T6	14245	0	0	0
T7	1276	325	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	46159	0	0
T26	507	0	0	0
T38	0	39	0	0
T42	0	94	0	0
T58	407	0	0	0
T60	0	26	0	0
T61	422	0	0	0
T65	0	17	0	0
T75	0	342	0	0
T76	0	82	0	0
T77	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017458	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	546	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	870	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	19	0	0
T39	26418	0	0	0
T42	13233	0	0	0
T45	8550	0	0	0
T52	686	0	0	0
T60	665	1	0	0
T71	12966	0	0	0
T72	38723	0	0	0
T75	0	4	0	0
T83	0	3	0	0
T90	0	2	0	0
T125	0	2	0	0
T126	0	2	0	0
T127	0	2	0	0
T128	0	1	0	0
T129	0	2	0	0
T130	525	0	0	0
T131	539	0	0	0
T132	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	513799	0	0
T3	949	38	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	108364	0	0
T26	507	0	0	0
T38	0	111	0	0
T42	0	84	0	0
T58	407	0	0	0
T61	422	0	0	0
T65	0	49	0	0
T76	0	235	0	0
T77	0	149	0	0
T121	0	218	0	0
T122	0	122	0	0
T123	0	268024	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	56	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6692839	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	399	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	66	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6695267	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	400	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	67	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	123	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	5	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	2	0	0
T61	422	0	0	0
T65	0	1	0	0
T75	0	6	0	0
T76	0	1	0	0
T77	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	75	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T65	0	1	0	0
T75	0	4	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	56	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	56	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T65	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	513743	0	0
T3	949	37	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	108363	0	0
T26	507	0	0	0
T38	0	110	0	0
T42	0	83	0	0
T58	407	0	0	0
T61	422	0	0	0
T65	0	48	0	0
T76	0	234	0	0
T77	0	147	0	0
T121	0	217	0	0
T122	0	121	0	0
T123	0	268023	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7188	0	0
T1	545	0	0	0
T2	9573	14	0	0
T3	949	4	0	0
T4	31438	11	0	0
T5	521	6	0	0
T6	14245	27	0	0
T7	1276	5	0	0
T8	0	1	0	0
T13	502	5	0	0
T14	417	1	0	0
T15	472	0	0	0
T61	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	308468	0	0
T3	949	31	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	52	0	0
T26	507	0	0	0
T38	0	60	0	0
T42	0	27	0	0
T58	407	0	0	0
T61	422	0	0	0
T65	0	168	0	0
T76	0	133239	0	0
T77	0	928	0	0
T121	0	50	0	0
T122	0	187	0	0
T123	0	102	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T23
1	0	Covered	T5,T13,T14
1	1	Covered	T3,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T60
0	1	Covered	T3,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T60
0	1	Unreachable
1	0	Covered	T7,T23,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T23
DetectSt	168	Covered	T3,T7,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T23,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T23
DebounceSt->IdleSt	163	Covered	T38,T88,T90
DetectSt->IdleSt	186	Covered	T3,T88,T89
DetectSt->StableSt	191	Covered	T7,T23,T60
IdleSt->DebounceSt	148	Covered	T3,T7,T23
StableSt->IdleSt	206	Covered	T7,T23,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T23
0	1	Covered	T3,T7,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T23
IdleSt	0	-	-	-	-	-	-	Covered	T5,T13,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T88,T90
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T23
DetectSt	-	-	-	-	1	-	-	Covered	T3,T88,T89
DetectSt	-	-	-	-	0	1	-	Covered	T7,T23,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T23,T60
StableSt	-	-	-	-	-	-	0	Covered	T7,T23,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	177	0	0
CntIncr_A	8699631	121199	0	0
CntNoWrap_A	8699631	8017478	0	0
DetectStDropOut_A	8699631	11	0	0
DetectedOut_A	8699631	195713	0	0
DetectedPulseOut_A	8699631	58	0	0
DisabledIdleSt_A	8699631	6692839	0	0
DisabledNoDetection_A	8699631	6695267	0	0
EnterDebounceSt_A	8699631	109	0	0
EnterDetectSt_A	8699631	69	0	0
EnterStableSt_A	8699631	58	0	0
PulseIsPulse_A	8699631	58	0	0
StayInStableSt	8699631	195655	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_sticky_sva.StableStDropOut_A	8699631	844044	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	177	0	0
T3	949	2	0	0
T6	14245	0	0	0
T7	1276	6	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	2	0	0
T26	507	0	0	0
T38	0	2	0	0
T42	0	2	0	0
T58	407	0	0	0
T60	0	2	0	0
T61	422	0	0	0
T65	0	2	0	0
T75	0	4	0	0
T76	0	2	0	0
T77	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	121199	0	0
T3	949	98	0	0
T6	14245	0	0	0
T7	1276	240	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	48	0	0
T26	507	0	0	0
T38	0	74	0	0
T42	0	85	0	0
T58	407	0	0	0
T60	0	76	0	0
T61	422	0	0	0
T65	0	26	0	0
T75	0	178	0	0
T76	0	60552	0	0
T77	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017478	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	546	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	869	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	11	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T58	407	0	0	0
T61	422	0	0	0
T88	0	1	0	0
T89	0	1	0	0
T127	0	1	0	0
T133	0	1	0	0
T134	0	1	0	0
T135	0	1	0	0
T136	0	2	0	0
T137	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	195713	0	0
T7	1276	318	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	60	0	0
T26	507	0	0	0
T27	2961	0	0	0
T42	0	36	0	0
T58	407	0	0	0
T60	0	80	0	0
T61	422	0	0	0
T65	0	80	0	0
T75	0	543	0	0
T76	0	72915	0	0
T77	0	737	0	0
T121	0	72	0	0
T122	0	127	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	58	0	0
T7	1276	3	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T27	2961	0	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6692839	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	399	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	66	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6695267	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	400	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	67	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	109	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	3	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	2	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	69	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	3	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	58	0	0
T7	1276	3	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T27	2961	0	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	58	0	0
T7	1276	3	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T27	2961	0	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T65	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	195655	0	0
T7	1276	315	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	59	0	0
T26	507	0	0	0
T27	2961	0	0	0
T42	0	35	0	0
T58	407	0	0	0
T60	0	79	0	0
T61	422	0	0	0
T65	0	79	0	0
T75	0	541	0	0
T76	0	72914	0	0
T77	0	735	0	0
T121	0	71	0	0
T122	0	126	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	844044	0	0
T7	1276	205	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	154466	0	0
T26	507	0	0	0
T27	2961	0	0	0
T42	0	86	0	0
T58	407	0	0	0
T60	0	49	0	0
T61	422	0	0	0
T65	0	129	0	0
T75	0	129	0	0
T76	0	82	0	0
T77	0	173	0	0
T121	0	209	0	0
T122	0	188	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T23
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T23
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T23
0	1	Unreachable
1	0	Covered	T3,T7,T23

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T23
DetectSt	168	Covered	T3,T7,T23
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T7,T23

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T23
DebounceSt->IdleSt	163	Covered	T65,T76,T91
DetectSt->IdleSt	186	Covered	T82,T83,T84
DetectSt->StableSt	191	Covered	T3,T7,T23
IdleSt->DebounceSt	148	Covered	T3,T7,T23
StableSt->IdleSt	206	Covered	T3,T7,T23

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T23
0	1	Covered	T3,T7,T23
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T23
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T23
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T23
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T76,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T23
DetectSt	-	-	-	-	1	-	-	Covered	T82,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T23
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T7,T23
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T23
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	182	0	0
CntIncr_A	8699631	62505	0	0
CntNoWrap_A	8699631	8017473	0	0
DetectStDropOut_A	8699631	15	0	0
DetectedOut_A	8699631	333027	0	0
DetectedPulseOut_A	8699631	60	0	0
DisabledIdleSt_A	8699631	6692839	0	0
DisabledNoDetection_A	8699631	6695267	0	0
EnterDebounceSt_A	8699631	108	0	0
EnterDetectSt_A	8699631	75	0	0
EnterStableSt_A	8699631	60	0	0
PulseIsPulse_A	8699631	60	0	0
StayInStableSt	8699631	332967	0	0
gen_high_event_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_sticky_sva.StableStDropOut_A	8699631	633058	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	182	0	0
T3	949	2	0	0
T6	14245	0	0	0
T7	1276	6	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	2	0	0
T26	507	0	0	0
T38	0	2	0	0
T42	0	2	0	0
T58	407	0	0	0
T60	0	2	0	0
T61	422	0	0	0
T65	0	3	0	0
T75	0	4	0	0
T76	0	2	0	0
T77	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	62505	0	0
T3	949	24	0	0
T6	14245	0	0	0
T7	1276	276	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	82	0	0
T26	507	0	0	0
T38	0	44	0	0
T42	0	95	0	0
T58	407	0	0	0
T60	0	22	0	0
T61	422	0	0	0
T65	0	129	0	0
T75	0	134	0	0
T76	0	34	0	0
T77	0	96	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017473	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	546	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	869	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	15	0	0
T82	1027	2	0	0
T83	0	1	0	0
T84	0	3	0	0
T129	0	2	0	0
T138	0	4	0	0
T139	0	1	0	0
T140	0	2	0	0
T141	2736	0	0	0
T142	790	0	0	0
T143	502	0	0	0
T144	502	0	0	0
T145	842	0	0	0
T146	11553	0	0	0
T147	522	0	0	0
T148	26203	0	0	0
T149	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	333027	0	0
T3	949	18	0	0
T6	14245	0	0	0
T7	1276	400	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	146	0	0
T26	507	0	0	0
T38	0	83	0	0
T42	0	31	0	0
T58	407	0	0	0
T60	0	29	0	0
T61	422	0	0	0
T75	0	621	0	0
T77	0	433	0	0
T121	0	132	0	0
T122	0	234	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	60	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	3	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T75	0	2	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6692839	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	399	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	66	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6695267	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	400	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	67	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	108	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	3	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T65	0	3	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	75	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	3	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T75	0	2	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	60	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	3	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T75	0	2	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	60	0	0
T3	949	1	0	0
T6	14245	0	0	0
T7	1276	3	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	1	0	0
T26	507	0	0	0
T38	0	1	0	0
T42	0	1	0	0
T58	407	0	0	0
T60	0	1	0	0
T61	422	0	0	0
T75	0	2	0	0
T77	0	2	0	0
T121	0	1	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	332967	0	0
T3	949	17	0	0
T6	14245	0	0	0
T7	1276	397	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	145	0	0
T26	507	0	0	0
T38	0	82	0	0
T42	0	30	0	0
T58	407	0	0	0
T60	0	28	0	0
T61	422	0	0	0
T75	0	619	0	0
T77	0	431	0	0
T121	0	131	0	0
T122	0	233	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	633058	0	0
T3	949	100	0	0
T6	14245	0	0	0
T7	1276	113	0	0
T8	561	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T23	0	154354	0	0
T26	507	0	0	0
T38	0	90	0	0
T42	0	94	0	0
T58	407	0	0	0
T60	0	173	0	0
T61	422	0	0	0
T75	0	106	0	0
T77	0	609	0	0
T121	0	180	0	0
T122	0	53	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T38,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T38,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T38,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T10,T38,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T38,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T38,T43
0	1	Covered	T39,T40,T150
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T38,T43
1	-	Covered	T39,T40,T150

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T38,T43
DetectSt	168	Covered	T10,T38,T43
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T38,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T38,T43
DebounceSt->IdleSt	163	Covered	T78,T79,T151
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T38,T43
IdleSt->DebounceSt	148	Covered	T10,T38,T43
StableSt->IdleSt	206	Covered	T10,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T38,T43
0	1	Covered	T10,T38,T43
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T38,T43
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T38,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T38,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T151
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T38,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T38,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T40,T150
StableSt	-	-	-	-	-	-	0	Covered	T10,T38,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	88	0	0
CntIncr_A	8699631	2668	0	0
CntNoWrap_A	8699631	8017567	0	0
DetectStDropOut_A	8699631	0	0	0
DetectedOut_A	8699631	4811	0	0
DetectedPulseOut_A	8699631	42	0	0
DisabledIdleSt_A	8699631	7756846	0	0
DisabledNoDetection_A	8699631	7759215	0	0
EnterDebounceSt_A	8699631	46	0	0
EnterDetectSt_A	8699631	42	0	0
EnterStableSt_A	8699631	42	0	0
PulseIsPulse_A	8699631	42	0	0
StayInStableSt	8699631	4743	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	88	0	0
T10	196046	2	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	2	0	0
T111	0	2	0	0
T122	0	2	0	0
T150	0	2	0	0
T152	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2668	0	0
T10	196046	33	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	50	0	0
T39	0	26	0	0
T40	0	92	0	0
T43	0	86	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	31	0	0
T111	0	10	0	0
T122	0	97	0	0
T150	0	42	0	0
T152	0	12	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017567	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	4811	0	0
T10	196046	41	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	202	0	0
T39	0	90	0	0
T40	0	43	0	0
T43	0	356	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	75	0	0
T111	0	102	0	0
T122	0	43	0	0
T150	0	175	0	0
T152	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	42	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T111	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7756846	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7759215	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	46	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T111	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	42	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T111	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	42	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T111	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	42	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T111	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T152	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	4743	0	0
T10	196046	39	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	200	0	0
T39	0	89	0	0
T40	0	42	0	0
T43	0	354	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	73	0	0
T111	0	100	0	0
T122	0	41	0	0
T150	0	174	0	0
T152	0	63	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	16	0	0
T39	26418	1	0	0
T40	0	1	0	0
T42	13233	0	0	0
T65	11296	0	0	0
T75	1330	0	0	0
T109	525	0	0	0
T110	416	0	0	0
T111	608	0	0	0
T112	513	0	0	0
T113	406	0	0	0
T114	405	0	0	0
T127	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T41,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T41,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T41,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T37
1	0	Covered	T4,T5,T2
1	1	Covered	T1,T41,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T41,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T41,T37
0	1	Covered	T41,T43,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T41,T37
1	-	Covered	T41,T43,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T41,T37
DetectSt	168	Covered	T1,T41,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T41,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T41,T37
DebounceSt->IdleSt	163	Covered	T42,T154,T159
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T41,T37
IdleSt->DebounceSt	148	Covered	T1,T41,T37
StableSt->IdleSt	206	Covered	T41,T38,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T41,T37
0	1	Covered	T1,T41,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T41,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T41,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T41,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T154,T159
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T41,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T41,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T43,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T41,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	113	0	0
CntIncr_A	8699631	3674	0	0
CntNoWrap_A	8699631	8017542	0	0
DetectStDropOut_A	8699631	0	0	0
DetectedOut_A	8699631	5515	0	0
DetectedPulseOut_A	8699631	52	0	0
DisabledIdleSt_A	8699631	7998708	0	0
DisabledNoDetection_A	8699631	8001083	0	0
EnterDebounceSt_A	8699631	61	0	0
EnterDetectSt_A	8699631	52	0	0
EnterStableSt_A	8699631	52	0	0
PulseIsPulse_A	8699631	52	0	0
StayInStableSt	8699631	5437	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	2811	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	113	0	0
T1	545	2	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	0	4	0	0
T41	0	4	0	0
T42	0	5	0	0
T43	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3674	0	0
T1	545	48	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	56	0	0
T38	0	45	0	0
T40	0	184	0	0
T41	0	180	0	0
T42	0	187	0	0
T43	0	86	0	0
T160	0	69	0	0
T161	0	29	0	0
T162	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017542	0	0
T1	545	142	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	5515	0	0
T1	545	88	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	181	0	0
T38	0	45	0	0
T40	0	563	0	0
T41	0	256	0	0
T42	0	200	0	0
T43	0	211	0	0
T160	0	289	0	0
T161	0	42	0	0
T162	0	219	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	52	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7998708	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8001083	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	61	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	3	0	0
T43	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	52	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	52	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	52	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	5437	0	0
T1	545	86	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T37	0	179	0	0
T38	0	43	0	0
T40	0	560	0	0
T41	0	253	0	0
T42	0	197	0	0
T43	0	210	0	0
T160	0	287	0	0
T161	0	40	0	0
T162	0	217	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2811	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T5	521	5	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	2	0	0
T10	0	29	0	0
T11	0	1	0	0
T13	502	7	0	0
T14	417	2	0	0
T15	472	0	0	0
T16	405	0	0	0
T26	0	7	0	0
T54	0	3	0	0
T61	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	26	0	0
T32	17946	0	0	0
T40	0	1	0	0
T41	4428	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	11547	0	0	0
T46	3032	0	0	0
T67	517	0	0	0
T68	525	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0
T122	0	1	0	0
T150	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T163	0	1	0	0
T164	0	2	0	0
T165	422	0	0	0