Unified Coverage Report :: Module :: sysrst_ctrl_detect

Module : sysrst_ctrl_detect

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.09	100.00	95.01		100.00	95.45	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h	89.17	93.48	85.71		83.33	90.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h	90.61	95.65	85.71		83.33	95.00	93.33
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l	90.69	95.65	85.71		83.33	95.00	93.75
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l	96.66	97.83	90.48		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l	96.66	97.83	90.48		100.00	95.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre	97.99	100.00	94.74		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l	98.10	100.00	90.48		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre	99.05	100.00	100.00		100.00	95.24	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00
tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect	100.00	100.00	100.00		100.00	100.00	100.00

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
96.66	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
96.66	97.83

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
90.69	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.17	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
90.61	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
97.99	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T15
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T15

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T15
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T6
0	1	Covered	T4,T2,T10
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T6
0	1	Covered	T4,T2,T6
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T2,T6
1	-	Covered	T4,T2,T6

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
96.66	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
96.66	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
90.69	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T43,T39,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T8,T11,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T8,T11,T41

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
97.99	94.74

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T9,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T15,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T6,T9
0	1	Covered	T9,T12,T36
1	0	Covered	T9,T12,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T6,T9
0	1	Covered	T6,T9,T12
1	0	Covered	T9,T36,T81

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T6,T9
1	-	Covered	T6,T9,T12

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.67	93.33

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T23
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T23
0	1	Covered	T82,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T23
0	1	Unreachable
1	0	Covered	T3,T7,T23

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.17	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
90.61	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.10	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T10
1	0	Covered	T4,T5,T1
1	1	Covered	T1,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T85,T86,T87
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T10
0	1	Covered	T8,T41,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T10
1	-	Covered	T8,T41,T38

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T5,T13,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T5,T13,T14
1	1	Covered	T5,T13,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T23
1	0	Covered	T5,T13,T14
1	1	Covered	T3,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T60
0	1	Covered	T3,T88,T89
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T23,T60
0	1	Unreachable
1	0	Covered	T7,T23,T60

---

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.89	94.44

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T7,T23

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T23
1	0	Covered	T4,T5,T2
1	1	Covered	T3,T7,T23

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T38
0	1	Covered	T60,T75,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T38
0	1	Unreachable
1	0	Covered	T3,T23,T38

---

FSM Coverage for Module : sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T10
DetectSt	168	Covered	T1,T8,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T11
DebounceSt->IdleSt	163	Covered	T10,T32,T48
DetectSt->IdleSt	186	Covered	T3,T43,T60
DetectSt->StableSt	191	Covered	T1,T8,T11
IdleSt->DebounceSt	148	Covered	T1,T8,T10
StableSt->IdleSt	206	Covered	T8,T11,T41

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
96.66	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
96.66	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
90.69	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.89	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.17	90.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
90.61	95.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.10	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
99.05	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T8,T11
0	1	Covered	T1,T8,T10
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T39,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T3,T43,T60
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	0	0	-	Covered	T4,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T41
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.67	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
97.99	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
99.05	95.24

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T15,T6
0	1	Covered	T3,T15,T6
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T15,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T15,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T15,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T76,T91
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T15,T6
DetectSt	-	-	-	-	1	-	-	Covered	T9,T12,T36
DetectSt	-	-	-	-	0	1	-	Covered	T3,T15,T6
DetectSt	-	-	-	-	0	0	-	Covered	T15,T6,T9
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T7
StableSt	-	-	-	-	-	-	0	Covered	T3,T15,T6
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	226190406	17726	0	0
CntIncr_A	226190406	1559335	0	0
CntNoWrap_A	226190406	208441304	0	0
DetectStDropOut_A	226190406	1182	0	0
DetectedOut_A	226190406	1876274	0	0
DetectedPulseOut_A	226190406	6260	0	0
DisabledIdleSt_A	226190406	198319127	0	0
DisabledNoDetection_A	226190406	198377914	0	0
EnterDebounceSt_A	226190406	9180	0	0
EnterDetectSt_A	226190406	8566	0	0
EnterStableSt_A	226190406	6260	0	0
PulseIsPulse_A	226190406	6260	0	0
StayInStableSt	226190406	1869054	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	78296679	53869	0	0
gen_high_event_sva.HighLevelEvent_A	43498155	40100420	0	0
gen_high_level_sva.HighLevelEvent_A	147893727	136341428	0	0
gen_low_level_sva.LowLevelEvent_A	78296679	72180756	0	0
gen_not_sticky_sva.StableStDropOut_A	200091513	5104	0	0
gen_sticky_sva.StableStDropOut_A	26098893	1785570	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	17726	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	14	0	0
T5	521	0	0	0
T6	28490	54	0	0
T7	2552	0	0	0
T9	0	48	0	0
T10	0	4	0	0
T12	0	10	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	944	3	0	0
T16	405	0	0	0
T27	0	1	0	0
T32	17946	8	0	0
T33	0	4	0	0
T35	0	4	0	0
T37	721	0	0	0
T38	0	1	0	0
T39	0	6	0	0
T42	0	8	0	0
T44	11547	0	0	0
T46	3032	2	0	0
T47	0	4	0	0
T48	0	3	0	0
T49	0	6	0	0
T50	0	4	0	0
T51	0	2	0	0
T52	0	4	0	0
T59	201326	0	0	0
T65	0	8	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T92	422	0	0	0
T93	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	1559335	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	565	0	0
T5	521	0	0	0
T6	28490	1805	0	0
T7	2552	0	0	0
T9	0	1571	0	0
T10	196046	1053	0	0
T11	240873	0	0	0
T12	6527	275	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	944	41	0	0
T16	405	0	0	0
T24	497	0	0	0
T27	2961	24	0	0
T32	0	6044	0	0
T33	0	122	0	0
T34	20386	0	0	0
T35	0	322	0	0
T36	0	774	0	0
T38	0	20	0	0
T39	0	19116	0	0
T42	0	208	0	0
T46	0	15	0	0
T47	0	176	0	0
T48	0	90	0	0
T49	0	49	0	0
T50	0	46	0	0
T51	0	40	0	0
T52	0	105	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	208441304	0	0
T1	14170	3736	0	0
T2	248898	238060	0	0
T3	24674	14242	0	0
T4	817388	804699	0	0
T5	13546	3120	0	0
T6	370370	359282	0	0
T7	33176	22733	0	0
T13	13052	2626	0	0
T14	10842	416	0	0
T15	12272	1843	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	1182	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T9	9686	13	0	0
T10	0	2	0	0
T12	0	3	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T39	26418	1	0	0
T42	13233	0	0	0
T45	0	6	0	0
T65	11296	0	0	0
T75	1330	0	0	0
T94	0	3	0	0
T95	0	15	0	0
T96	0	25	0	0
T97	0	5	0	0
T98	0	1	0	0
T99	0	14	0	0
T100	0	13	0	0
T101	0	1	0	0
T102	0	4	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	10	0	0
T108	0	2	0	0
T109	525	0	0	0
T110	416	0	0	0
T111	608	0	0	0
T112	513	0	0	0
T113	406	0	0	0
T114	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	1876274	0	0
T6	28490	1658	0	0
T7	2552	0	0	0
T8	1122	0	0	0
T9	19372	0	0	0
T10	196046	0	0	0
T15	472	46	0	0
T16	810	0	0	0
T17	820	0	0	0
T26	1014	0	0	0
T32	17946	45	0	0
T33	0	110	0	0
T35	0	26	0	0
T36	0	1	0	0
T37	721	0	0	0
T39	0	6	0	0
T42	0	14	0	0
T44	11547	164	0	0
T46	3032	1	0	0
T47	0	20	0	0
T48	0	1	0	0
T49	0	13	0	0
T50	0	78	0	0
T51	0	36	0	0
T52	0	12	0	0
T58	814	0	0	0
T59	201326	0	0	0
T61	844	0	0	0
T65	0	28	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T71	0	915	0	0
T72	0	1270	0	0
T92	422	0	0	0
T93	422	0	0	0
T115	0	2117	0	0
T116	0	159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	6260	0	0
T6	28490	27	0	0
T7	2552	0	0	0
T8	1122	0	0	0
T9	19372	0	0	0
T10	196046	0	0	0
T15	472	1	0	0
T16	810	0	0	0
T17	820	0	0	0
T26	1014	0	0	0
T32	17946	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	4	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	7	0	0
T52	0	2	0	0
T58	814	0	0	0
T59	201326	0	0	0
T61	844	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T71	0	13	0	0
T72	0	11	0	0
T92	422	0	0	0
T93	422	0	0	0
T115	0	35	0	0
T116	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	198319127	0	0
T1	14170	2624	0	0
T2	248898	228737	0	0
T3	24674	13801	0	0
T4	817388	793760	0	0
T5	13546	3120	0	0
T6	370370	328416	0	0
T7	33176	20323	0	0
T13	13052	2626	0	0
T14	10842	416	0	0
T15	12272	1734	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	198377914	0	0
T1	14170	2642	0	0
T2	248898	228806	0	0
T3	24674	13827	0	0
T4	817388	794068	0	0
T5	13546	3146	0	0
T6	370370	328486	0	0
T7	33176	20349	0	0
T13	13052	2652	0	0
T14	10842	442	0	0
T15	12272	1758	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	9180	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	28490	27	0	0
T7	2552	0	0	0
T9	0	24	0	0
T10	196046	3	0	0
T11	240873	0	0	0
T12	6527	5	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	944	2	0	0
T16	405	0	0	0
T24	497	0	0	0
T27	2961	1	0	0
T32	0	5	0	0
T33	0	2	0	0
T34	20386	0	0	0
T35	0	2	0	0
T36	0	11	0	0
T38	0	1	0	0
T39	0	4	0	0
T42	0	4	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	8566	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	28490	27	0	0
T7	2552	0	0	0
T9	0	24	0	0
T10	0	2	0	0
T12	0	5	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	944	1	0	0
T16	405	0	0	0
T27	0	1	0	0
T32	17946	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	721	0	0	0
T39	0	3	0	0
T42	0	4	0	0
T44	11547	0	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	7	0	0
T52	0	2	0	0
T59	201326	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T71	0	13	0	0
T92	422	0	0	0
T93	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	6260	0	0
T6	28490	27	0	0
T7	2552	0	0	0
T8	1122	0	0	0
T9	19372	0	0	0
T10	196046	0	0	0
T15	472	1	0	0
T16	810	0	0	0
T17	820	0	0	0
T26	1014	0	0	0
T32	17946	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	4	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	7	0	0
T52	0	2	0	0
T58	814	0	0	0
T59	201326	0	0	0
T61	844	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T71	0	13	0	0
T72	0	11	0	0
T92	422	0	0	0
T93	422	0	0	0
T115	0	35	0	0
T116	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	6260	0	0
T6	28490	27	0	0
T7	2552	0	0	0
T8	1122	0	0	0
T9	19372	0	0	0
T10	196046	0	0	0
T15	472	1	0	0
T16	810	0	0	0
T17	820	0	0	0
T26	1014	0	0	0
T32	17946	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	1	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	4	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	2	0	0
T51	0	7	0	0
T52	0	2	0	0
T58	814	0	0	0
T59	201326	0	0	0
T61	844	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T71	0	13	0	0
T72	0	11	0	0
T92	422	0	0	0
T93	422	0	0	0
T115	0	35	0	0
T116	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	226190406	1869054	0	0
T6	28490	1631	0	0
T7	2552	0	0	0
T8	1122	0	0	0
T9	19372	0	0	0
T10	196046	0	0	0
T15	472	44	0	0
T16	810	0	0	0
T17	820	0	0	0
T23	386866	0	0	0
T26	1014	0	0	0
T32	17946	41	0	0
T33	0	108	0	0
T35	0	24	0	0
T37	721	0	0	0
T39	0	4	0	0
T42	0	10	0	0
T44	0	160	0	0
T47	808	18	0	0
T48	695	0	0	0
T49	0	10	0	0
T50	0	75	0	0
T51	0	29	0	0
T52	0	10	0	0
T58	814	0	0	0
T59	201326	0	0	0
T61	844	0	0	0
T65	0	24	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T71	0	900	0	0
T72	0	1253	0	0
T73	0	595	0	0
T115	0	2076	0	0
T116	0	151	0	0
T117	0	3	0	0
T118	0	26	0	0
T119	503	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78296679	53869	0	0
T1	4905	2	0	0
T2	86157	87	0	0
T3	8541	16	0	0
T4	220066	79	0	0
T5	4689	46	0	0
T6	128205	188	0	0
T7	11484	20	0	0
T8	0	10	0	0
T9	0	21	0	0
T10	0	56	0	0
T11	0	1	0	0
T13	4518	48	0	0
T14	3753	10	0	0
T15	4248	3	0	0
T16	810	1	0	0
T26	0	28	0	0
T53	0	6	0	0
T54	0	4	0	0
T61	0	22	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	43498155	40100420	0	0
T1	2725	725	0	0
T2	47865	45800	0	0
T3	4745	2745	0	0
T4	157190	154830	0	0
T5	2605	605	0	0
T6	71225	69135	0	0
T7	6380	4380	0	0
T13	2510	510	0	0
T14	2085	85	0	0
T15	2360	360	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	147893727	136341428	0	0
T1	9265	2465	0	0
T2	162741	155720	0	0
T3	16133	9333	0	0
T4	534446	526422	0	0
T5	8857	2057	0	0
T6	242165	235059	0	0
T7	21692	14892	0	0
T13	8534	1734	0	0
T14	7089	289	0	0
T15	8024	1224	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	78296679	72180756	0	0
T1	4905	1305	0	0
T2	86157	82440	0	0
T3	8541	4941	0	0
T4	282942	278694	0	0
T5	4689	1089	0	0
T6	128205	124443	0	0
T7	11484	7884	0	0
T13	4518	918	0	0
T14	3753	153	0	0
T15	4248	648	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	200091513	5104	0	0
T6	28490	27	0	0
T7	2552	0	0	0
T8	1122	0	0	0
T9	19372	0	0	0
T10	588138	0	0	0
T16	810	0	0	0
T17	820	0	0	0
T26	1014	0	0	0
T27	2961	0	0	0
T32	17946	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T37	721	0	0	0
T39	0	2	0	0
T42	0	4	0	0
T44	11547	4	0	0
T46	3032	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0
T50	0	1	0	0
T51	0	7	0	0
T52	0	2	0	0
T58	814	0	0	0
T59	201326	0	0	0
T61	844	0	0	0
T65	0	4	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T71	0	11	0	0
T72	0	5	0	0
T73	0	7	0	0
T92	422	0	0	0
T93	422	0	0	0
T115	0	29	0	0
T116	0	8	0	0
T120	0	11	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26098893	1785570	0	0
T3	1898	131	0	0
T6	28490	0	0	0
T7	3828	318	0	0
T8	1683	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T15	944	0	0	0
T16	1215	0	0	0
T17	1230	0	0	0
T23	0	308872	0	0
T26	1521	0	0	0
T27	2961	0	0	0
T38	0	150	0	0
T42	0	207	0	0
T58	1221	0	0	0
T60	0	222	0	0
T61	1266	0	0	0
T65	0	297	0	0
T75	0	235	0	0
T76	0	133321	0	0
T77	0	1710	0	0
T121	0	439	0	0
T122	0	428	0	0
T123	0	102	0	0