Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T11,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T8,T11,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Covered	T38,T43,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T41
1	-	Covered	T38,T43,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T41
DetectSt	168	Covered	T8,T11,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T41
DebounceSt->IdleSt	163	Covered	T78,T79
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T11,T41
IdleSt->DebounceSt	148	Covered	T8,T11,T41
StableSt->IdleSt	206	Covered	T41,T38,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T41
0	1	Covered	T8,T11,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T43,T42
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	78	0	0
CntIncr_A	8699631	31865	0	0
CntNoWrap_A	8699631	8017577	0	0
DetectStDropOut_A	8699631	0	0	0
DetectedOut_A	8699631	58062	0	0
DetectedPulseOut_A	8699631	38	0	0
DisabledIdleSt_A	8699631	7758270	0	0
DisabledNoDetection_A	8699631	7760643	0	0
EnterDebounceSt_A	8699631	40	0	0
EnterDetectSt_A	8699631	38	0	0
EnterStableSt_A	8699631	38	0	0
PulseIsPulse_A	8699631	38	0	0
StayInStableSt	8699631	58005	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	78	0	0
T8	561	2	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	2	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	4	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	31865	0	0
T8	561	16	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	29819	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	50	0	0
T39	0	103	0	0
T40	0	184	0	0
T41	0	90	0	0
T42	0	62	0	0
T43	0	86	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	20	0	0
T161	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017577	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	58062	0	0
T8	561	59	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	54855	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	40	0	0
T39	0	86	0	0
T40	0	86	0	0
T41	0	213	0	0
T42	0	42	0	0
T43	0	507	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	99	0	0
T161	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	2	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7758270	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7760643	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	40	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	2	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	2	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	2	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	2	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	58005	0	0
T8	561	57	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	54853	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	39	0	0
T39	0	82	0	0
T40	0	83	0	0
T41	0	211	0	0
T42	0	41	0	0
T43	0	506	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T111	0	96	0	0
T161	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	19	0	0
T35	25186	0	0	0
T38	13373	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	1237	1	0	0
T50	501	0	0	0
T51	13131	0	0	0
T86	0	2	0	0
T111	0	1	0	0
T153	0	1	0	0
T163	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T168	402	0	0	0
T169	438	0	0	0
T170	425	0	0	0
T171	404	0	0	0
T172	502	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T11,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T8,T11,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Covered	T43,T173,T104
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Covered	T8,T11,T41
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T41
1	-	Covered	T8,T11,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T41
DetectSt	168	Covered	T8,T11,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T41
DebounceSt->IdleSt	163	Covered	T39,T174,T175
DetectSt->IdleSt	186	Covered	T43,T173,T104
DetectSt->StableSt	191	Covered	T8,T11,T41
IdleSt->DebounceSt	148	Covered	T8,T11,T41
StableSt->IdleSt	206	Covered	T8,T11,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T41
0	1	Covered	T8,T11,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T174,T175
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	1	-	-	Covered	T43,T173,T104
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T41
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	156	0	0
CntIncr_A	8699631	34268	0	0
CntNoWrap_A	8699631	8017499	0	0
DetectStDropOut_A	8699631	3	0	0
DetectedOut_A	8699631	55513	0	0
DetectedPulseOut_A	8699631	71	0	0
DisabledIdleSt_A	8699631	7757419	0	0
DisabledNoDetection_A	8699631	7759787	0	0
EnterDebounceSt_A	8699631	82	0	0
EnterDetectSt_A	8699631	74	0	0
EnterStableSt_A	8699631	71	0	0
PulseIsPulse_A	8699631	71	0	0
StayInStableSt	8699631	55409	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	3192	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	156	0	0
T8	561	2	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	2	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	1	0	0
T41	0	6	0	0
T42	0	4	0	0
T43	0	4	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	2	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	34268	0	0
T8	561	16	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	29819	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	56	0	0
T38	0	104	0	0
T39	0	77	0	0
T41	0	208	0	0
T42	0	124	0	0
T43	0	172	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	97	0	0
T70	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017499	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3	0	0
T43	1237	1	0	0
T45	8550	0	0	0
T51	13131	0	0	0
T52	686	0	0	0
T60	665	0	0	0
T104	0	1	0	0
T130	525	0	0	0
T131	539	0	0	0
T170	425	0	0	0
T171	404	0	0	0
T172	502	0	0	0
T173	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	55513	0	0
T8	561	59	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	49738	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	43	0	0
T38	0	133	0	0
T41	0	330	0	0
T42	0	200	0	0
T43	0	60	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	44	0	0
T70	0	41	0	0
T80	0	115	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	71	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	1	0	0
T70	0	1	0	0
T80	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7757419	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7759787	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	82	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	1	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	74	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	1	0	0
T70	0	1	0	0
T80	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	71	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	1	0	0
T70	0	1	0	0
T80	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	71	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	1	0	0
T38	0	2	0	0
T41	0	3	0	0
T42	0	2	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	1	0	0
T70	0	1	0	0
T80	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	55409	0	0
T8	561	58	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	49737	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	42	0	0
T38	0	129	0	0
T41	0	326	0	0
T42	0	197	0	0
T43	0	58	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T65	0	42	0	0
T70	0	39	0	0
T80	0	112	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3192	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T5	521	5	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	1	0	0
T10	0	27	0	0
T13	502	5	0	0
T14	417	2	0	0
T15	472	0	0	0
T16	405	0	0	0
T26	0	7	0	0
T53	0	6	0	0
T54	0	1	0	0
T61	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T152	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T11,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T41
1	0	Covered	T4,T5,T1
1	1	Covered	T8,T11,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T41
0	1	Covered	T8,T41,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T41
1	-	Covered	T8,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T41
DetectSt	168	Covered	T8,T11,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T41
DebounceSt->IdleSt	163	Covered	T39,T86,T154
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T11,T41
IdleSt->DebounceSt	148	Covered	T8,T11,T41
StableSt->IdleSt	206	Covered	T8,T41,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T41
0	1	Covered	T8,T11,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T86,T154
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	113	0	0
CntIncr_A	8699631	76718	0	0
CntNoWrap_A	8699631	8017542	0	0
DetectStDropOut_A	8699631	0	0	0
DetectedOut_A	8699631	215864	0	0
DetectedPulseOut_A	8699631	53	0	0
DisabledIdleSt_A	8699631	7672487	0	0
DisabledNoDetection_A	8699631	7674862	0	0
EnterDebounceSt_A	8699631	61	0	0
EnterDetectSt_A	8699631	53	0	0
EnterStableSt_A	8699631	53	0	0
PulseIsPulse_A	8699631	53	0	0
StayInStableSt	8699631	215785	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	113	0	0
T8	561	2	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	2	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	2	0	0
T86	0	1	0	0
T162	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	76718	0	0
T8	561	16	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	29819	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	59	0	0
T39	0	26	0	0
T40	0	92	0	0
T41	0	90	0	0
T42	0	63	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	14	0	0
T86	0	64	0	0
T162	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017542	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	215864	0	0
T8	561	60	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	210645	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	42	0	0
T40	0	80	0	0
T41	0	173	0	0
T42	0	156	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	39	0	0
T152	0	42	0	0
T162	0	218	0	0
T176	0	120	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	53	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	1	0	0
T152	0	2	0	0
T162	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7672487	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7674862	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	61	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T162	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	53	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	1	0	0
T152	0	2	0	0
T162	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	53	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	1	0	0
T152	0	2	0	0
T162	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	53	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	1	0	0
T152	0	2	0	0
T162	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	215785	0	0
T8	561	59	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	210643	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	40	0	0
T40	0	79	0	0
T41	0	172	0	0
T42	0	155	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	37	0	0
T152	0	39	0	0
T162	0	216	0	0
T176	0	119	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	27	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T166	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T41,T37
1	0	Covered	T4,T5,T2
1	1	Covered	T8,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T41,T42
0	1	Covered	T178,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T41,T42
0	1	Covered	T111,T80,T152
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T41,T42
1	-	Covered	T111,T80,T152

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T41,T42
DetectSt	168	Covered	T8,T41,T42
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T41,T42
DebounceSt->IdleSt	163	Covered	T78,T79
DetectSt->IdleSt	186	Covered	T178,T179
DetectSt->StableSt	191	Covered	T8,T41,T42
IdleSt->DebounceSt	148	Covered	T8,T41,T42
StableSt->IdleSt	206	Covered	T41,T42,T111

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T41,T42
0	1	Covered	T8,T41,T42
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T41,T42
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T41,T42
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T178,T179
DetectSt	-	-	-	-	0	1	-	Covered	T8,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T111,T80,T152
StableSt	-	-	-	-	-	-	0	Covered	T8,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	80	0	0
CntIncr_A	8699631	2106	0	0
CntNoWrap_A	8699631	8017575	0	0
DetectStDropOut_A	8699631	2	0	0
DetectedOut_A	8699631	2885	0	0
DetectedPulseOut_A	8699631	37	0	0
DisabledIdleSt_A	8699631	7915755	0	0
DisabledNoDetection_A	8699631	7918134	0	0
EnterDebounceSt_A	8699631	41	0	0
EnterDetectSt_A	8699631	39	0	0
EnterStableSt_A	8699631	37	0	0
PulseIsPulse_A	8699631	37	0	0
StayInStableSt	8699631	2827	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	6821	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	80	0	0
T8	561	2	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	2	0	0
T111	0	4	0	0
T122	0	2	0	0
T152	0	2	0	0
T154	0	4	0	0
T176	0	2	0	0
T180	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2106	0	0
T8	561	16	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	90	0	0
T42	0	63	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	31	0	0
T111	0	20	0	0
T122	0	97	0	0
T152	0	12	0	0
T154	0	108	0	0
T176	0	78	0	0
T180	0	132	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017575	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2	0	0
T178	959	1	0	0
T179	0	1	0	0
T181	18540	0	0	0
T182	433	0	0	0
T183	678	0	0	0
T184	494	0	0	0
T185	607	0	0	0
T186	21253	0	0	0
T187	429	0	0	0
T188	496	0	0	0
T189	532	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2885	0	0
T8	561	41	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	424	0	0
T42	0	41	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	40	0	0
T111	0	44	0	0
T122	0	140	0	0
T152	0	67	0	0
T154	0	236	0	0
T176	0	86	0	0
T180	0	128	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	37	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	1	0	0
T111	0	2	0	0
T122	0	1	0	0
T152	0	1	0	0
T154	0	2	0	0
T176	0	1	0	0
T180	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7915755	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7918134	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	41	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	1	0	0
T111	0	2	0	0
T122	0	1	0	0
T152	0	1	0	0
T154	0	2	0	0
T176	0	1	0	0
T180	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	39	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	1	0	0
T111	0	2	0	0
T122	0	1	0	0
T152	0	1	0	0
T154	0	2	0	0
T176	0	1	0	0
T180	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	37	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	1	0	0
T111	0	2	0	0
T122	0	1	0	0
T152	0	1	0	0
T154	0	2	0	0
T176	0	1	0	0
T180	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	37	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	1	0	0
T111	0	2	0	0
T122	0	1	0	0
T152	0	1	0	0
T154	0	2	0	0
T176	0	1	0	0
T180	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2827	0	0
T8	561	39	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T41	0	422	0	0
T42	0	39	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T80	0	39	0	0
T111	0	41	0	0
T122	0	138	0	0
T152	0	66	0	0
T154	0	233	0	0
T176	0	84	0	0
T180	0	124	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6821	0	0
T1	545	0	0	0
T2	9573	11	0	0
T3	949	4	0	0
T4	31438	13	0	0
T5	521	5	0	0
T6	14245	30	0	0
T7	1276	5	0	0
T8	0	1	0	0
T13	502	4	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	0	1	0	0
T61	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	16	0	0
T65	11296	0	0	0
T73	14788	0	0	0
T74	8284	0	0	0
T75	1330	0	0	0
T80	0	1	0	0
T111	608	1	0	0
T112	513	0	0	0
T113	406	0	0	0
T114	405	0	0	0
T152	0	1	0	0
T154	0	1	0	0
T156	0	1	0	0
T157	0	2	0	0
T175	0	1	0	0
T180	0	2	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	422	0	0	0
T193	519	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T41,T38
1	0	Covered	T4,T5,T1
1	1	Covered	T11,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T38,T39
0	1	Covered	T85,T194
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T38,T39
0	1	Covered	T11,T38,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T38,T39
1	-	Covered	T11,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T38,T39
DetectSt	168	Covered	T11,T38,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T38,T39
DebounceSt->IdleSt	163	Covered	T38,T39,T195
DetectSt->IdleSt	186	Covered	T85,T194
DetectSt->StableSt	191	Covered	T11,T38,T39
IdleSt->DebounceSt	148	Covered	T11,T38,T39
StableSt->IdleSt	206	Covered	T11,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T38,T39
0	1	Covered	T11,T38,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T38,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T39,T195
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T85,T194
DetectSt	-	-	-	-	0	1	-	Covered	T11,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T11,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	121	0	0
CntIncr_A	8699631	77016	0	0
CntNoWrap_A	8699631	8017534	0	0
DetectStDropOut_A	8699631	2	0	0
DetectedOut_A	8699631	60938	0	0
DetectedPulseOut_A	8699631	54	0	0
DisabledIdleSt_A	8699631	7672171	0	0
DisabledNoDetection_A	8699631	7674543	0	0
EnterDebounceSt_A	8699631	66	0	0
EnterDetectSt_A	8699631	56	0	0
EnterStableSt_A	8699631	54	0	0
PulseIsPulse_A	8699631	54	0	0
StayInStableSt	8699631	60857	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	121	0	0
T11	240873	2	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	5	0	0
T39	0	5	0	0
T40	0	2	0	0
T42	0	2	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	4	0	0
T86	0	8	0	0
T122	0	6	0	0
T161	0	2	0	0
T195	0	1	0	0
T196	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	77016	0	0
T11	240873	29819	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	154	0	0
T39	0	129	0	0
T40	0	92	0	0
T42	0	62	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	28	0	0
T86	0	97	0	0
T122	0	242	0	0
T161	0	29	0	0
T195	0	98	0	0
T196	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017534	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2	0	0
T85	606	1	0	0
T120	6567	0	0	0
T162	717	0	0	0
T194	0	1	0	0
T197	976	0	0	0
T198	422	0	0	0
T199	38660	0	0	0
T200	495	0	0	0
T201	421	0	0	0
T202	456	0	0	0
T203	713	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	60938	0	0
T11	240873	54856	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	57	0	0
T39	0	87	0	0
T40	0	344	0	0
T42	0	260	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	113	0	0
T86	0	178	0	0
T122	0	449	0	0
T152	0	80	0	0
T161	0	100	0	0
T196	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	54	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	1	0	0
T86	0	4	0	0
T122	0	3	0	0
T152	0	1	0	0
T161	0	1	0	0
T196	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7672171	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7674543	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	66	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	3	0	0
T39	0	3	0	0
T40	0	1	0	0
T42	0	1	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	2	0	0
T86	0	4	0	0
T122	0	3	0	0
T161	0	1	0	0
T195	0	1	0	0
T196	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	56	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	2	0	0
T86	0	4	0	0
T122	0	3	0	0
T152	0	1	0	0
T161	0	1	0	0
T196	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	54	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	1	0	0
T86	0	4	0	0
T122	0	3	0	0
T152	0	1	0	0
T161	0	1	0	0
T196	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	54	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	1	0	0
T86	0	4	0	0
T122	0	3	0	0
T152	0	1	0	0
T161	0	1	0	0
T196	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	60857	0	0
T11	240873	54855	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	54	0	0
T39	0	84	0	0
T40	0	343	0	0
T42	0	258	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T85	0	111	0	0
T86	0	173	0	0
T122	0	445	0	0
T152	0	79	0	0
T161	0	98	0	0
T196	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	27	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T25	496	0	0	0
T34	20386	0	0	0
T36	7539	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T55	503	0	0	0
T56	431	0	0	0
T62	493	0	0	0
T86	0	3	0	0
T122	0	2	0	0
T152	0	1	0	0
T153	0	2	0	0
T154	0	1	0	0
T176	0	1	0	0
T196	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T11,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T41
1	0	Covered	T4,T5,T2
1	1	Covered	T10,T11,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T41
0	1	Covered	T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T41
0	1	Covered	T41,T43,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T41
1	-	Covered	T41,T43,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T41
DetectSt	168	Covered	T10,T11,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T11,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T41
DebounceSt->IdleSt	163	Covered	T78,T79
DetectSt->IdleSt	186	Covered	T86
DetectSt->StableSt	191	Covered	T10,T11,T41
IdleSt->DebounceSt	148	Covered	T10,T11,T41
StableSt->IdleSt	206	Covered	T10,T41,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T41
0	1	Covered	T10,T11,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T41
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T41
DetectSt	-	-	-	-	1	-	-	Covered	T86
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T43,T39
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	80	0	0
CntIncr_A	8699631	31943	0	0
CntNoWrap_A	8699631	8017575	0	0
DetectStDropOut_A	8699631	1	0	0
DetectedOut_A	8699631	3169	0	0
DetectedPulseOut_A	8699631	38	0	0
DisabledIdleSt_A	8699631	7759183	0	0
DisabledNoDetection_A	8699631	7761556	0	0
EnterDebounceSt_A	8699631	41	0	0
EnterDetectSt_A	8699631	39	0	0
EnterStableSt_A	8699631	38	0	0
PulseIsPulse_A	8699631	38	0	0
StayInStableSt	8699631	3108	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	6481	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	80	0	0
T10	196046	2	0	0
T11	240873	2	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T41	0	4	0	0
T42	0	2	0	0
T43	0	4	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	2	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	31943	0	0
T10	196046	33	0	0
T11	240873	29819	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	59	0	0
T39	0	52	0	0
T40	0	92	0	0
T41	0	180	0	0
T42	0	63	0	0
T43	0	172	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	31	0	0
T160	0	69	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017575	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1	0	0
T86	10634	1	0	0
T195	645	0	0	0
T204	413	0	0	0
T205	504	0	0	0
T206	423	0	0	0
T207	48783	0	0	0
T208	526	0	0	0
T209	805	0	0	0
T210	421	0	0	0
T211	10062	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3169	0	0
T10	196046	90	0	0
T11	240873	39	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	42	0	0
T39	0	131	0	0
T40	0	356	0	0
T41	0	121	0	0
T42	0	50	0	0
T43	0	103	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	75	0	0
T160	0	66	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7759183	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7761556	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	41	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	39	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T41	0	2	0	0
T42	0	1	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3108	0	0
T10	196046	88	0	0
T11	240873	37	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	40	0	0
T39	0	128	0	0
T40	0	354	0	0
T41	0	119	0	0
T42	0	49	0	0
T43	0	100	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	73	0	0
T160	0	65	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6481	0	0
T1	545	0	0	0
T2	9573	13	0	0
T3	949	0	0	0
T4	31438	9	0	0
T5	521	5	0	0
T6	14245	29	0	0
T7	1276	0	0	0
T8	0	1	0	0
T9	0	21	0	0
T13	502	6	0	0
T14	417	0	0	0
T15	472	1	0	0
T26	0	4	0	0
T61	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	15	0	0
T32	17946	0	0	0
T39	0	1	0	0
T41	4428	2	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	11547	0	0	0
T46	3032	0	0	0
T67	517	0	0	0
T68	525	0	0	0
T70	471	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T92	422	0	0	0
T93	422	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T160	0	1	0	0
T165	422	0	0	0
T167	0	1	0	0