Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T41
1	0	Covered	T4,T5,T2
1	1	Covered	T1,T10,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T41
0	1	Covered	T212,T213
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T41
0	1	Covered	T10,T41,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T41
1	-	Covered	T10,T41,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T41
DetectSt	168	Covered	T1,T10,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T10,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T41
DebounceSt->IdleSt	163	Covered	T173,T78,T79
DetectSt->IdleSt	186	Covered	T212,T213
DetectSt->StableSt	191	Covered	T1,T10,T41
IdleSt->DebounceSt	148	Covered	T1,T10,T41
StableSt->IdleSt	206	Covered	T10,T41,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T41
0	1	Covered	T1,T10,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T214,T213
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T41
DetectSt	-	-	-	-	1	-	-	Covered	T212,T213
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T41,T39
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	138	0	0
CntIncr_A	8699631	47760	0	0
CntNoWrap_A	8699631	8017517	0	0
DetectStDropOut_A	8699631	2	0	0
DetectedOut_A	8699631	6069	0	0
DetectedPulseOut_A	8699631	65	0	0
DisabledIdleSt_A	8699631	7913301	0	0
DisabledNoDetection_A	8699631	7915675	0	0
EnterDebounceSt_A	8699631	72	0	0
EnterDetectSt_A	8699631	67	0	0
EnterStableSt_A	8699631	65	0	0
PulseIsPulse_A	8699631	65	0	0
StayInStableSt	8699631	5977	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	138	0	0
T1	545	2	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	4	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T41	0	4	0	0
T42	0	2	0	0
T65	0	2	0	0
T80	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	47760	0	0
T1	545	48	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	66	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	45	0	0
T39	0	52	0	0
T41	0	180	0	0
T42	0	62	0	0
T65	0	97	0	0
T80	0	31	0	0
T160	0	69	0	0
T161	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017517	0	0
T1	545	142	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2	0	0
T212	1460	1	0	0
T213	0	1	0	0
T215	525	0	0	0
T216	407	0	0	0
T217	11551	0	0	0
T218	525	0	0	0
T219	522	0	0	0
T220	9698	0	0	0
T221	3218	0	0	0
T222	522	0	0	0
T223	637	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6069	0	0
T1	545	39	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	97	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	90	0	0
T39	0	113	0	0
T41	0	256	0	0
T42	0	368	0	0
T65	0	10	0	0
T80	0	147	0	0
T160	0	175	0	0
T161	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	65	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T65	0	1	0	0
T80	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7913301	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7915675	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	72	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T65	0	1	0	0
T80	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	67	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T65	0	1	0	0
T80	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	65	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T65	0	1	0	0
T80	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	65	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	1	0	0
T65	0	1	0	0
T80	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	5977	0	0
T1	545	37	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	94	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	88	0	0
T39	0	110	0	0
T41	0	253	0	0
T42	0	366	0	0
T65	0	9	0	0
T80	0	145	0	0
T160	0	174	0	0
T161	0	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	1	0	0
T86	0	2	0	0
T122	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T39,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T39,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T41
1	0	Covered	T4,T5,T2
1	1	Covered	T10,T39,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T39,T40
0	1	Covered	T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T39,T40
0	1	Covered	T10,T39,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T39,T40
1	-	Covered	T10,T39,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T39,T40
DetectSt	168	Covered	T10,T39,T40
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T39,T40
DebounceSt->IdleSt	163	Covered	T122,T78,T79
DetectSt->IdleSt	186	Covered	T86
DetectSt->StableSt	191	Covered	T10,T39,T40
IdleSt->DebounceSt	148	Covered	T10,T39,T40
StableSt->IdleSt	206	Covered	T10,T39,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T39,T40
0	1	Covered	T10,T39,T40
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T39,T40
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T39,T40
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T39,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T122
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T39,T40
DetectSt	-	-	-	-	1	-	-	Covered	T86
DetectSt	-	-	-	-	0	1	-	Covered	T10,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T39,T40
StableSt	-	-	-	-	-	-	0	Covered	T10,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	73	0	0
CntIncr_A	8699631	2168	0	0
CntNoWrap_A	8699631	8017582	0	0
DetectStDropOut_A	8699631	1	0	0
DetectedOut_A	8699631	2212	0	0
DetectedPulseOut_A	8699631	34	0	0
DisabledIdleSt_A	8699631	8000858	0	0
DisabledNoDetection_A	8699631	8003237	0	0
EnterDebounceSt_A	8699631	38	0	0
EnterDetectSt_A	8699631	35	0	0
EnterStableSt_A	8699631	34	0	0
PulseIsPulse_A	8699631	34	0	0
StayInStableSt	8699631	2160	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	6517	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	73	0	0
T10	196046	2	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	6	0	0
T122	0	1	0	0
T142	0	2	0	0
T153	0	2	0	0
T154	0	4	0	0
T167	0	2	0	0
T224	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2168	0	0
T10	196046	33	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	26	0	0
T40	0	184	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	84	0	0
T122	0	97	0	0
T142	0	71	0	0
T153	0	64	0	0
T154	0	108	0	0
T167	0	84	0	0
T224	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017582	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1	0	0
T86	10634	1	0	0
T195	645	0	0	0
T204	413	0	0	0
T205	504	0	0	0
T206	423	0	0	0
T207	48783	0	0	0
T208	526	0	0	0
T209	805	0	0	0
T210	421	0	0	0
T211	10062	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2212	0	0
T10	196046	16	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	87	0	0
T40	0	84	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	82	0	0
T142	0	46	0	0
T153	0	107	0	0
T154	0	41	0	0
T157	0	175	0	0
T167	0	255	0	0
T224	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	34	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	2	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	2	0	0
T167	0	1	0	0
T224	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8000858	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8003237	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	3	0	0
T122	0	1	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T167	0	1	0	0
T224	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	35	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	3	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	2	0	0
T167	0	1	0	0
T224	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	34	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	2	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	2	0	0
T167	0	1	0	0
T224	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	34	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	2	0	0
T142	0	1	0	0
T153	0	1	0	0
T154	0	2	0	0
T157	0	2	0	0
T167	0	1	0	0
T224	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2160	0	0
T10	196046	15	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	86	0	0
T40	0	81	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	78	0	0
T142	0	44	0	0
T153	0	106	0	0
T154	0	38	0	0
T157	0	172	0	0
T167	0	253	0	0
T224	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6517	0	0
T1	545	0	0	0
T2	9573	12	0	0
T3	949	0	0	0
T4	31438	10	0	0
T5	521	5	0	0
T6	14245	21	0	0
T7	1276	0	0	0
T8	0	1	0	0
T13	502	7	0	0
T14	417	2	0	0
T15	472	1	0	0
T26	0	4	0	0
T61	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	16	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T126	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T191	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T8,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T11
1	0	Covered	T4,T5,T2
1	1	Covered	T1,T8,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T86,T87,T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T11
0	1	Covered	T8,T11,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T11
1	-	Covered	T8,T11,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T11
DetectSt	168	Covered	T1,T8,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T11
DebounceSt->IdleSt	163	Covered	T122,T154,T78
DetectSt->IdleSt	186	Covered	T86,T87,T179
DetectSt->StableSt	191	Covered	T1,T8,T11
IdleSt->DebounceSt	148	Covered	T1,T8,T11
StableSt->IdleSt	206	Covered	T8,T11,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T11
0	1	Covered	T1,T8,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T122,T154,T214
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	1	-	-	Covered	T86,T87,T179
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T11,T38
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	137	0	0
CntIncr_A	8699631	76893	0	0
CntNoWrap_A	8699631	8017518	0	0
DetectStDropOut_A	8699631	5	0	0
DetectedOut_A	8699631	48714	0	0
DetectedPulseOut_A	8699631	61	0	0
DisabledIdleSt_A	8699631	7673206	0	0
DisabledNoDetection_A	8699631	7675581	0	0
EnterDebounceSt_A	8699631	71	0	0
EnterDetectSt_A	8699631	66	0	0
EnterStableSt_A	8699631	61	0	0
PulseIsPulse_A	8699631	61	0	0
StayInStableSt	8699631	48624	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	32	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	137	0	0
T1	545	2	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	2	0	0
T11	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	2	0	0
T85	0	4	0	0
T86	0	8	0	0
T122	0	3	0	0
T150	0	4	0	0
T152	0	2	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	76893	0	0
T1	545	48	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	16	0	0
T11	0	29819	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	45	0	0
T85	0	28	0	0
T86	0	151	0	0
T122	0	194	0	0
T150	0	84	0	0
T152	0	12	0	0
T161	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017518	0	0
T1	545	142	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	5	0	0
T86	10634	1	0	0
T87	0	1	0	0
T179	0	1	0	0
T195	645	0	0	0
T204	413	0	0	0
T205	504	0	0	0
T206	423	0	0	0
T207	48783	0	0	0
T208	526	0	0	0
T209	805	0	0	0
T210	421	0	0	0
T211	10062	0	0	0
T227	0	1	0	0
T228	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	48714	0	0
T1	545	38	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	59	0	0
T11	0	41	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T85	0	77	0	0
T86	0	497	0	0
T122	0	91	0	0
T150	0	127	0	0
T152	0	65	0	0
T161	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	61	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T85	0	2	0	0
T86	0	3	0	0
T122	0	1	0	0
T150	0	2	0	0
T152	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7673206	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7675581	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	71	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T85	0	2	0	0
T86	0	4	0	0
T122	0	2	0	0
T150	0	2	0	0
T152	0	1	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	66	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T85	0	2	0	0
T86	0	4	0	0
T122	0	1	0	0
T150	0	2	0	0
T152	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	61	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T85	0	2	0	0
T86	0	3	0	0
T122	0	1	0	0
T150	0	2	0	0
T152	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	61	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	1	0	0
T11	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T38	0	1	0	0
T85	0	2	0	0
T86	0	3	0	0
T122	0	1	0	0
T150	0	2	0	0
T152	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	48624	0	0
T1	545	36	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T8	0	58	0	0
T11	0	40	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T85	0	74	0	0
T86	0	492	0	0
T122	0	90	0	0
T150	0	124	0	0
T152	0	63	0	0
T161	0	40	0	0
T176	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	32	0	0
T8	561	1	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T26	507	0	0	0
T27	2961	0	0	0
T38	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T153	0	2	0	0
T166	0	2	0	0
T180	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T41
1	0	Covered	T4,T5,T2
1	1	Covered	T10,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T38,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T38,T39
0	1	Covered	T10,T111,T86
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T38,T39
1	-	Covered	T10,T111,T86

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T38,T39
DetectSt	168	Covered	T10,T38,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T38,T39
DebounceSt->IdleSt	163	Covered	T163,T78,T79
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T38,T39
IdleSt->DebounceSt	148	Covered	T10,T38,T39
StableSt->IdleSt	206	Covered	T10,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T38,T39
0	1	Covered	T10,T38,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T38,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T163
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T38,T39
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T111,T86
StableSt	-	-	-	-	-	-	0	Covered	T10,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	69	0	0
CntIncr_A	8699631	1907	0	0
CntNoWrap_A	8699631	8017586	0	0
DetectStDropOut_A	8699631	0	0	0
DetectedOut_A	8699631	2397	0	0
DetectedPulseOut_A	8699631	33	0	0
DisabledIdleSt_A	8699631	7999560	0	0
DisabledNoDetection_A	8699631	8001933	0	0
EnterDebounceSt_A	8699631	36	0	0
EnterDetectSt_A	8699631	33	0	0
EnterStableSt_A	8699631	33	0	0
PulseIsPulse_A	8699631	33	0	0
StayInStableSt	8699631	2346	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	6483	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	69	0	0
T10	196046	2	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	2	0	0
T86	0	2	0	0
T88	0	2	0	0
T111	0	2	0	0
T154	0	2	0	0
T195	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1907	0	0
T10	196046	33	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	50	0	0
T39	0	77	0	0
T42	0	62	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	97	0	0
T86	0	10	0	0
T88	0	12	0	0
T111	0	10	0	0
T154	0	54	0	0
T195	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017586	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2397	0	0
T10	196046	92	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	49	0	0
T39	0	43	0	0
T42	0	40	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	43	0	0
T86	0	39	0	0
T88	0	67	0	0
T111	0	7	0	0
T154	0	97	0	0
T195	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	33	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T111	0	1	0	0
T154	0	1	0	0
T195	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7999560	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8001933	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	36	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T111	0	1	0	0
T154	0	1	0	0
T195	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	33	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T111	0	1	0	0
T154	0	1	0	0
T195	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	33	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T111	0	1	0	0
T154	0	1	0	0
T195	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	33	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	1	0	0
T86	0	1	0	0
T88	0	1	0	0
T111	0	1	0	0
T154	0	1	0	0
T195	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2346	0	0
T10	196046	91	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T38	0	47	0	0
T39	0	41	0	0
T42	0	38	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T65	0	41	0	0
T86	0	38	0	0
T88	0	65	0	0
T111	0	6	0	0
T154	0	96	0	0
T195	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	6483	0	0
T1	545	0	0	0
T2	9573	9	0	0
T3	949	0	0	0
T4	31438	14	0	0
T5	521	3	0	0
T6	14245	27	0	0
T7	1276	0	0	0
T8	0	1	0	0
T13	502	4	0	0
T14	417	1	0	0
T15	472	1	0	0
T26	0	6	0	0
T61	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	15	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T86	0	1	0	0
T111	0	1	0	0
T127	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T225	0	1	0	0
T226	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T10,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T10,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T41
1	0	Covered	T4,T5,T2
1	1	Covered	T1,T10,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T41
0	1	Covered	T229
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T10,T39
0	1	Covered	T10,T41,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T10,T39
1	-	Covered	T10,T41,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T10,T41
DetectSt	168	Covered	T1,T10,T41
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T10,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T10,T41
DebounceSt->IdleSt	163	Covered	T150,T176,T173
DetectSt->IdleSt	186	Covered	T229
DetectSt->StableSt	191	Covered	T1,T10,T41
IdleSt->DebounceSt	148	Covered	T1,T10,T41
StableSt->IdleSt	206	Covered	T10,T41,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T10,T41
0	1	Covered	T1,T10,T41
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T41
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T10,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T10,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T176,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T10,T41
DetectSt	-	-	-	-	1	-	-	Covered	T229
DetectSt	-	-	-	-	0	1	-	Covered	T1,T10,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T1,T10,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	106	0	0
CntIncr_A	8699631	46639	0	0
CntNoWrap_A	8699631	8017549	0	0
DetectStDropOut_A	8699631	1	0	0
DetectedOut_A	8699631	4049	0	0
DetectedPulseOut_A	8699631	49	0	0
DisabledIdleSt_A	8699631	7916297	0	0
DisabledNoDetection_A	8699631	7918677	0	0
EnterDebounceSt_A	8699631	57	0	0
EnterDetectSt_A	8699631	50	0	0
EnterStableSt_A	8699631	49	0	0
PulseIsPulse_A	8699631	49	0	0
StayInStableSt	8699631	3977	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	106	0	0
T1	545	2	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	2	0	0
T41	0	2	0	0
T42	0	6	0	0
T65	0	2	0	0
T85	0	2	0	0
T111	0	2	0	0
T122	0	4	0	0
T150	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	46639	0	0
T1	545	48	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	33	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	77	0	0
T41	0	59	0	0
T42	0	188	0	0
T65	0	97	0	0
T85	0	14	0	0
T111	0	10	0	0
T122	0	145	0	0
T150	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017549	0	0
T1	545	142	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1	0	0
T78	8241	0	0	0
T229	584	1	0	0
T231	30776	0	0	0
T232	5108	0	0	0
T233	416	0	0	0
T234	437	0	0	0
T235	765	0	0	0
T236	506	0	0	0
T237	527	0	0	0
T238	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	4049	0	0
T1	545	39	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	15	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	43	0	0
T41	0	1	0	0
T42	0	263	0	0
T65	0	153	0	0
T85	0	57	0	0
T111	0	58	0	0
T122	0	555	0	0
T150	0	122	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	49	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T65	0	1	0	0
T85	0	1	0	0
T111	0	1	0	0
T122	0	2	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7916297	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7918677	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	57	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T65	0	1	0	0
T85	0	1	0	0
T111	0	1	0	0
T122	0	2	0	0
T150	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	50	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T65	0	1	0	0
T85	0	1	0	0
T111	0	1	0	0
T122	0	2	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	49	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T65	0	1	0	0
T85	0	1	0	0
T111	0	1	0	0
T122	0	2	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	49	0	0
T1	545	1	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	1	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T65	0	1	0	0
T85	0	1	0	0
T111	0	1	0	0
T122	0	2	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3977	0	0
T1	545	37	0	0
T2	9573	0	0	0
T3	949	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	14	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T39	0	41	0	0
T42	0	259	0	0
T65	0	151	0	0
T85	0	56	0	0
T111	0	57	0	0
T122	0	551	0	0
T150	0	121	0	0
T153	0	138	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	26	0	0
T10	196046	1	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T41	0	1	0	0
T42	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T85	0	1	0	0
T111	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0
T163	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T10,T11,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T10,T11,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T4,T5,T2
1	1	Covered	T10,T11,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T37
0	1	Covered	T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T11,T37
0	1	Covered	T37,T43,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T11,T37
1	-	Covered	T37,T43,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T11,T37
DetectSt	168	Covered	T10,T11,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T11,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T11,T37
DebounceSt->IdleSt	163	Covered	T239,T78,T79
DetectSt->IdleSt	186	Covered	T80
DetectSt->StableSt	191	Covered	T10,T11,T37
IdleSt->DebounceSt	148	Covered	T10,T11,T37
StableSt->IdleSt	206	Covered	T10,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T11,T37
0	1	Covered	T10,T11,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T11,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T11,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T239
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T11,T37
DetectSt	-	-	-	-	1	-	-	Covered	T80
DetectSt	-	-	-	-	0	1	-	Covered	T10,T11,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T37,T43,T39
StableSt	-	-	-	-	-	-	0	Covered	T10,T11,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	81	0	0
CntIncr_A	8699631	31879	0	0
CntNoWrap_A	8699631	8017574	0	0
DetectStDropOut_A	8699631	1	0	0
DetectedOut_A	8699631	2639	0	0
DetectedPulseOut_A	8699631	38	0	0
DisabledIdleSt_A	8699631	7760500	0	0
DisabledNoDetection_A	8699631	7762874	0	0
EnterDebounceSt_A	8699631	42	0	0
EnterDetectSt_A	8699631	39	0	0
EnterStableSt_A	8699631	38	0	0
PulseIsPulse_A	8699631	38	0	0
StayInStableSt	8699631	2578	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8699631	7188	0	0
gen_low_level_sva.LowLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	81	0	0
T10	196046	2	0	0
T11	240873	2	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	2	0	0
T85	0	2	0	0
T111	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	31879	0	0
T10	196046	33	0	0
T11	240873	29819	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	56	0	0
T38	0	50	0	0
T39	0	26	0	0
T42	0	63	0	0
T43	0	86	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	31	0	0
T85	0	14	0	0
T111	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8017574	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1	0	0
T66	499	0	0	0
T80	619	1	0	0
T116	26309	0	0	0
T160	838	0	0	0
T240	403	0	0	0
T241	11092	0	0	0
T242	674	0	0	0
T243	522	0	0	0
T244	406	0	0	0
T245	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2639	0	0
T10	196046	41	0	0
T11	240873	38	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	84	0	0
T38	0	48	0	0
T39	0	89	0	0
T42	0	49	0	0
T43	0	81	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T85	0	111	0	0
T111	0	120	0	0
T150	0	138	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T85	0	1	0	0
T111	0	1	0	0
T150	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7760500	0	0
T1	545	4	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7762874	0	0
T1	545	4	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	42	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T111	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	39	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T80	0	1	0	0
T85	0	1	0	0
T111	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T85	0	1	0	0
T111	0	1	0	0
T150	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	38	0	0
T10	196046	1	0	0
T11	240873	1	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T85	0	1	0	0
T111	0	1	0	0
T150	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2578	0	0
T10	196046	39	0	0
T11	240873	36	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T37	0	83	0	0
T38	0	46	0	0
T39	0	88	0	0
T42	0	48	0	0
T43	0	80	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T85	0	109	0	0
T111	0	118	0	0
T150	0	135	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7188	0	0
T1	545	0	0	0
T2	9573	14	0	0
T3	949	4	0	0
T4	31438	11	0	0
T5	521	6	0	0
T6	14245	27	0	0
T7	1276	5	0	0
T8	0	1	0	0
T13	502	5	0	0
T14	417	1	0	0
T15	472	0	0	0
T61	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	15	0	0
T23	386866	0	0	0
T33	17682	0	0	0
T37	721	1	0	0
T38	13373	0	0	0
T39	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T47	808	0	0	0
T48	695	0	0	0
T49	595	0	0	0
T64	494	0	0	0
T69	522	0	0	0
T86	0	1	0	0
T119	503	0	0	0
T150	0	1	0	0
T158	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T225	0	1	0	0