Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T9,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T6,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T6,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T6,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T15,T6,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T15,T6,T9
0	1	Covered	T9,T12,T45
1	0	Covered	T9,T12,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T15,T6,T44
0	1	Covered	T6,T44,T71
1	0	Covered	T36,T81,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T15,T6,T36
1	-	Covered	T6,T44,T71

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T6,T9
DetectSt	168	Covered	T15,T6,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T15,T6,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T15,T6,T9
DebounceSt->IdleSt	163	Covered	T246,T247,T248
DetectSt->IdleSt	186	Covered	T9,T12,T36
DetectSt->StableSt	191	Covered	T15,T6,T36
IdleSt->DebounceSt	148	Covered	T15,T6,T9
StableSt->IdleSt	206	Covered	T6,T36,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T15,T6,T9
0	1	Covered	T15,T6,T9
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T15,T6,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T15,T6,T9
IdleSt	0	-	-	-	-	-	-	Covered	T6,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T15,T6,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T246,T247,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T6,T9
DetectSt	-	-	-	-	1	-	-	Covered	T9,T12,T36
DetectSt	-	-	-	-	0	1	-	Covered	T15,T6,T36
DetectSt	-	-	-	-	0	0	-	Covered	T15,T6,T9
StableSt	-	-	-	-	-	-	1	Covered	T6,T36,T44
StableSt	-	-	-	-	-	-	0	Covered	T15,T6,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	2989	0	0
CntIncr_A	8699631	100103	0	0
CntNoWrap_A	8699631	8014666	0	0
DetectStDropOut_A	8699631	192	0	0
DetectedOut_A	8699631	79219	0	0
DetectedPulseOut_A	8699631	1005	0	0
DisabledIdleSt_A	8699631	7565383	0	0
DisabledNoDetection_A	8699631	7567582	0	0
EnterDebounceSt_A	8699631	1517	0	0
EnterDetectSt_A	8699631	1472	0	0
EnterStableSt_A	8699631	1005	0	0
PulseIsPulse_A	8699631	1005	0	0
StayInStableSt	8699631	78076	0	0
gen_high_event_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	864	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2989	0	0
T6	14245	52	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	48	0	0
T12	0	10	0	0
T15	472	2	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	22	0	0
T44	0	8	0	0
T45	0	28	0	0
T50	0	2	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	24	0	0
T72	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	100103	0	0
T6	14245	1742	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1571	0	0
T12	0	275	0	0
T15	472	21	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	774	0	0
T44	0	276	0	0
T45	0	1262	0	0
T50	0	21	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	504	0	0
T72	0	720	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8014666	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13772	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	69	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	192	0	0
T9	9686	13	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	3	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T45	0	6	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T94	0	3	0	0
T95	0	15	0	0
T96	0	25	0	0
T97	0	5	0	0
T99	0	14	0	0
T246	0	3	0	0
T249	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	79219	0	0
T6	14245	1578	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T15	472	46	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1	0	0
T44	0	164	0	0
T50	0	75	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	858	0	0
T72	0	1073	0	0
T73	0	604	0	0
T115	0	1715	0	0
T120	0	256	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1005	0	0
T6	14245	26	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T15	472	1	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1	0	0
T44	0	4	0	0
T50	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	12	0	0
T72	0	8	0	0
T73	0	8	0	0
T115	0	29	0	0
T120	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7565383	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	7560	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7567582	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	7562	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	4	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1517	0	0
T6	14245	26	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	24	0	0
T12	0	5	0	0
T15	472	1	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	4	0	0
T45	0	14	0	0
T50	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	12	0	0
T72	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1472	0	0
T6	14245	26	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	24	0	0
T12	0	5	0	0
T15	472	1	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	4	0	0
T45	0	14	0	0
T50	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	12	0	0
T72	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1005	0	0
T6	14245	26	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T15	472	1	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1	0	0
T44	0	4	0	0
T50	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	12	0	0
T72	0	8	0	0
T73	0	8	0	0
T115	0	29	0	0
T120	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1005	0	0
T6	14245	26	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T15	472	1	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1	0	0
T44	0	4	0	0
T50	0	1	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	12	0	0
T72	0	8	0	0
T73	0	8	0	0
T115	0	29	0	0
T120	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	78076	0	0
T6	14245	1552	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T15	472	44	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	160	0	0
T50	0	73	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	844	0	0
T72	0	1059	0	0
T73	0	595	0	0
T115	0	1680	0	0
T120	0	245	0	0
T250	0	2540	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	864	0	0
T6	14245	26	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	4	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	10	0	0
T72	0	2	0	0
T73	0	7	0	0
T115	0	23	0	0
T120	0	11	0	0
T250	0	21	0	0
T251	0	23	0	0
T252	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T15,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T15,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T15,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T6,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T15,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T15,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T10
0	1	Covered	T4,T10,T98
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T32,T33
0	1	Covered	T6,T32,T33
1	0	Covered	T78,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T32,T33
1	-	Covered	T6,T32,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T15,T6
DetectSt	168	Covered	T4,T6,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T32,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T6,T10
DebounceSt->IdleSt	163	Covered	T15,T38,T51
DetectSt->IdleSt	186	Covered	T4,T10,T27
DetectSt->StableSt	191	Covered	T6,T32,T33
IdleSt->DebounceSt	148	Covered	T4,T15,T6
StableSt->IdleSt	206	Covered	T6,T32,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T15,T6
0	1	Covered	T4,T15,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T15,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T6,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T38,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T15,T6
DetectSt	-	-	-	-	1	-	-	Covered	T4,T10,T98
DetectSt	-	-	-	-	0	1	-	Covered	T6,T27,T32
DetectSt	-	-	-	-	0	0	-	Covered	T4,T6,T10
StableSt	-	-	-	-	-	-	1	Covered	T6,T32,T33
StableSt	-	-	-	-	-	-	0	Covered	T6,T32,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	899	0	0
CntIncr_A	8699631	43451	0	0
CntNoWrap_A	8699631	8016756	0	0
DetectStDropOut_A	8699631	41	0	0
DetectedOut_A	8699631	14498	0	0
DetectedPulseOut_A	8699631	362	0	0
DisabledIdleSt_A	8699631	7649553	0	0
DisabledNoDetection_A	8699631	7651238	0	0
EnterDebounceSt_A	8699631	494	0	0
EnterDetectSt_A	8699631	409	0	0
EnterStableSt_A	8699631	362	0	0
PulseIsPulse_A	8699631	362	0	0
StayInStableSt	8699631	14099	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	323	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	899	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	14	0	0
T5	521	0	0	0
T6	14245	2	0	0
T7	1276	0	0	0
T10	0	4	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	1	0	0
T27	0	1	0	0
T32	0	6	0	0
T33	0	4	0	0
T35	0	4	0	0
T38	0	1	0	0
T50	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	43451	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	565	0	0
T5	521	0	0	0
T6	14245	63	0	0
T7	1276	0	0	0
T10	0	136	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	20	0	0
T27	0	24	0	0
T32	0	160	0	0
T33	0	122	0	0
T35	0	322	0	0
T38	0	20	0	0
T50	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8016756	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30938	0	0
T5	521	120	0	0
T6	14245	13822	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	70	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	41	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T98	0	1	0	0
T100	0	13	0	0
T101	0	1	0	0
T102	0	4	0	0
T106	0	1	0	0
T107	0	10	0	0
T108	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	14498	0	0
T6	14245	80	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T32	0	43	0	0
T33	0	110	0	0
T35	0	26	0	0
T50	0	3	0	0
T51	0	27	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	57	0	0
T72	0	197	0	0
T115	0	402	0	0
T116	0	159	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	362	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	2	0	0
T50	0	1	0	0
T51	0	6	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	1	0	0
T72	0	3	0	0
T115	0	6	0	0
T116	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7649553	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	28204	0	0
T5	521	120	0	0
T6	14245	12246	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7651238	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	28204	0	0
T5	521	121	0	0
T6	14245	12249	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	26	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	494	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	1	0	0
T27	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	2	0	0
T38	0	1	0	0
T50	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	409	0	0
T1	545	0	0	0
T2	9573	0	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T27	0	1	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	2	0	0
T50	0	1	0	0
T51	0	6	0	0
T71	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	362	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	2	0	0
T50	0	1	0	0
T51	0	6	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	1	0	0
T72	0	3	0	0
T115	0	6	0	0
T116	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	362	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	2	0	0
T50	0	1	0	0
T51	0	6	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	1	0	0
T72	0	3	0	0
T115	0	6	0	0
T116	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	14099	0	0
T6	14245	79	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T32	0	40	0	0
T33	0	108	0	0
T35	0	24	0	0
T50	0	2	0	0
T51	0	21	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	56	0	0
T72	0	194	0	0
T115	0	396	0	0
T116	0	151	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	323	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T32	0	3	0	0
T33	0	2	0	0
T35	0	2	0	0
T50	0	1	0	0
T51	0	6	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	1	0	0
T72	0	3	0	0
T115	0	6	0	0
T116	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T9,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T12
0	1	Covered	T9,T12,T36
1	0	Covered	T9,T12,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T44,T45
0	1	Covered	T6,T44,T45
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T44,T45
1	-	Covered	T6,T44,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T12
DetectSt	168	Covered	T6,T9,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T12
DebounceSt->IdleSt	163	Covered	T246,T247,T248
DetectSt->IdleSt	186	Covered	T9,T12,T36
DetectSt->StableSt	191	Covered	T6,T44,T45
IdleSt->DebounceSt	148	Covered	T6,T9,T12
StableSt->IdleSt	206	Covered	T6,T44,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T9,T12
0	1	Covered	T6,T9,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T246,T247,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T9,T12,T36
DetectSt	-	-	-	-	0	1	-	Covered	T6,T44,T45
DetectSt	-	-	-	-	0	0	-	Covered	T6,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T6,T44,T45
StableSt	-	-	-	-	-	-	0	Covered	T6,T44,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	3073	0	0
CntIncr_A	8699631	105978	0	0
CntNoWrap_A	8699631	8014582	0	0
DetectStDropOut_A	8699631	260	0	0
DetectedOut_A	8699631	81514	0	0
DetectedPulseOut_A	8699631	1044	0	0
DisabledIdleSt_A	8699631	7563294	0	0
DisabledNoDetection_A	8699631	7565495	0	0
EnterDebounceSt_A	8699631	1551	0	0
EnterDetectSt_A	8699631	1523	0	0
EnterStableSt_A	8699631	1044	0	0
PulseIsPulse_A	8699631	1044	0	0
StayInStableSt	8699631	80334	0	0
gen_high_event_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	908	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3073	0	0
T6	14245	10	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	12	0	0
T10	196046	0	0	0
T12	0	26	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	54	0	0
T44	0	42	0	0
T45	0	48	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	24	0	0
T72	0	32	0	0
T73	0	36	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	105978	0	0
T6	14245	325	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	392	0	0
T10	196046	0	0	0
T12	0	718	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1908	0	0
T44	0	1281	0	0
T45	0	1416	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	648	0	0
T72	0	1216	0	0
T73	0	1224	0	0
T74	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8014582	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13814	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	260	0	0
T9	9686	1	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	7	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T36	0	5	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T71	0	6	0	0
T95	0	7	0	0
T96	0	9	0	0
T97	0	7	0	0
T252	0	8	0	0
T253	0	7	0	0
T254	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	81514	0	0
T6	14245	253	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	2478	0	0
T45	0	2123	0	0
T58	407	0	0	0
T61	422	0	0	0
T72	0	2602	0	0
T73	0	2722	0	0
T74	0	181	0	0
T94	0	2018	0	0
T120	0	96	0	0
T241	0	1841	0	0
T250	0	2567	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1044	0	0
T6	14245	5	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	21	0	0
T45	0	24	0	0
T58	407	0	0	0
T61	422	0	0	0
T72	0	16	0	0
T73	0	18	0	0
T74	0	1	0	0
T94	0	32	0	0
T120	0	11	0	0
T241	0	29	0	0
T250	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7563294	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	7944	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7565495	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	7946	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1551	0	0
T6	14245	5	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	6	0	0
T10	196046	0	0	0
T12	0	13	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	27	0	0
T44	0	21	0	0
T45	0	24	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	12	0	0
T72	0	16	0	0
T73	0	18	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1523	0	0
T6	14245	5	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	6	0	0
T10	196046	0	0	0
T12	0	13	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	27	0	0
T44	0	21	0	0
T45	0	24	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	12	0	0
T72	0	16	0	0
T73	0	18	0	0
T74	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1044	0	0
T6	14245	5	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	21	0	0
T45	0	24	0	0
T58	407	0	0	0
T61	422	0	0	0
T72	0	16	0	0
T73	0	18	0	0
T74	0	1	0	0
T94	0	32	0	0
T120	0	11	0	0
T241	0	29	0	0
T250	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1044	0	0
T6	14245	5	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	21	0	0
T45	0	24	0	0
T58	407	0	0	0
T61	422	0	0	0
T72	0	16	0	0
T73	0	18	0	0
T74	0	1	0	0
T94	0	32	0	0
T120	0	11	0	0
T241	0	29	0	0
T250	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	80334	0	0
T6	14245	248	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	2456	0	0
T45	0	2099	0	0
T58	407	0	0	0
T61	422	0	0	0
T72	0	2575	0	0
T73	0	2702	0	0
T74	0	179	0	0
T94	0	1982	0	0
T120	0	85	0	0
T241	0	1810	0	0
T250	0	2540	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	908	0	0
T6	14245	5	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T44	0	20	0	0
T45	0	24	0	0
T58	407	0	0	0
T61	422	0	0	0
T72	0	5	0	0
T73	0	16	0	0
T94	0	28	0	0
T120	0	11	0	0
T241	0	27	0	0
T250	0	21	0	0
T255	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T2,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T10
0	1	Covered	T4,T2,T32
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T34,T44
0	1	Covered	T10,T34,T33
1	0	Covered	T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T34,T44
1	-	Covered	T10,T34,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T10
DetectSt	168	Covered	T4,T2,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T10,T34,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T2,T10
DebounceSt->IdleSt	163	Covered	T2,T33,T35
DetectSt->IdleSt	186	Covered	T4,T2,T32
DetectSt->StableSt	191	Covered	T10,T34,T44
IdleSt->DebounceSt	148	Covered	T4,T2,T10
StableSt->IdleSt	206	Covered	T10,T34,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T10
0	1	Covered	T4,T2,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T2,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T2,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T33,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T10
DetectSt	-	-	-	-	1	-	-	Covered	T4,T2,T32
DetectSt	-	-	-	-	0	1	-	Covered	T10,T34,T44
DetectSt	-	-	-	-	0	0	-	Covered	T4,T2,T10
StableSt	-	-	-	-	-	-	1	Covered	T10,T34,T33
StableSt	-	-	-	-	-	-	0	Covered	T10,T34,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	876	0	0
CntIncr_A	8699631	45667	0	0
CntNoWrap_A	8699631	8016779	0	0
DetectStDropOut_A	8699631	53	0	0
DetectedOut_A	8699631	14991	0	0
DetectedPulseOut_A	8699631	355	0	0
DisabledIdleSt_A	8699631	7634119	0	0
DisabledNoDetection_A	8699631	7635852	0	0
EnterDebounceSt_A	8699631	464	0	0
EnterDetectSt_A	8699631	413	0	0
EnterStableSt_A	8699631	355	0	0
PulseIsPulse_A	8699631	355	0	0
StayInStableSt	8699631	14582	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	876	0	0
T1	545	0	0	0
T2	9573	15	0	0
T3	949	0	0	0
T4	31438	4	0	0
T5	521	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	4	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	4	0	0
T33	0	10	0	0
T34	0	4	0	0
T35	0	11	0	0
T44	0	2	0	0
T51	0	6	0	0
T72	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	45667	0	0
T1	545	0	0	0
T2	9573	709	0	0
T3	949	0	0	0
T4	31438	160	0	0
T5	521	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	80	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	294	0	0
T33	0	338	0	0
T34	0	136	0	0
T35	0	809	0	0
T44	0	79	0	0
T51	0	302	0	0
T72	0	560	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8016779	0	0
T1	545	144	0	0
T2	9573	9142	0	0
T3	949	548	0	0
T4	31438	30948	0	0
T5	521	120	0	0
T6	14245	13824	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	53	0	0
T1	545	0	0	0
T2	9573	7	0	0
T3	949	0	0	0
T4	31438	2	0	0
T5	521	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	2	0	0
T104	0	1	0	0
T106	0	3	0	0
T116	0	2	0	0
T256	0	2	0	0
T257	0	11	0	0
T258	0	1	0	0
T259	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	14991	0	0
T10	196046	56	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T33	0	167	0	0
T34	20386	120	0	0
T35	0	141	0	0
T44	0	48	0	0
T51	0	82	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T72	0	302	0	0
T73	0	143	0	0
T74	0	36	0	0
T241	0	60	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	355	0	0
T10	196046	2	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T33	0	4	0	0
T34	20386	2	0	0
T35	0	5	0	0
T44	0	1	0	0
T51	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T72	0	7	0	0
T73	0	2	0	0
T74	0	1	0	0
T241	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7634119	0	0
T1	545	144	0	0
T2	9573	6042	0	0
T3	949	548	0	0
T4	31438	28204	0	0
T5	521	120	0	0
T6	14245	13571	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7635852	0	0
T1	545	145	0	0
T2	9573	6042	0	0
T3	949	549	0	0
T4	31438	28204	0	0
T5	521	121	0	0
T6	14245	13574	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	464	0	0
T1	545	0	0	0
T2	9573	8	0	0
T3	949	0	0	0
T4	31438	2	0	0
T5	521	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	6	0	0
T44	0	1	0	0
T51	0	4	0	0
T72	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	413	0	0
T1	545	0	0	0
T2	9573	7	0	0
T3	949	0	0	0
T4	31438	2	0	0
T5	521	0	0	0
T6	14245	0	0	0
T7	1276	0	0	0
T10	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	2	0	0
T35	0	5	0	0
T44	0	1	0	0
T51	0	2	0	0
T72	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	355	0	0
T10	196046	2	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T33	0	4	0	0
T34	20386	2	0	0
T35	0	5	0	0
T44	0	1	0	0
T51	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T72	0	7	0	0
T73	0	2	0	0
T74	0	1	0	0
T241	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	355	0	0
T10	196046	2	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T33	0	4	0	0
T34	20386	2	0	0
T35	0	5	0	0
T44	0	1	0	0
T51	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T72	0	7	0	0
T73	0	2	0	0
T74	0	1	0	0
T241	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	14582	0	0
T10	196046	54	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T33	0	163	0	0
T34	20386	118	0	0
T35	0	136	0	0
T44	0	46	0	0
T51	0	80	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T72	0	288	0	0
T73	0	139	0	0
T74	0	35	0	0
T241	0	56	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	299	0	0
T10	196046	2	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T33	0	4	0	0
T34	20386	2	0	0
T35	0	5	0	0
T51	0	2	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T56	431	0	0	0
T74	0	1	0	0
T199	0	12	0	0
T250	0	2	0	0
T260	0	6	0	0
T261	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T9,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T36
1	1	Covered	T6,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T12
0	1	Covered	T73,T74,T241
1	0	Covered	T73,T74,T241

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T12
0	1	Covered	T6,T9,T12
1	0	Covered	T81,T262

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T12
1	-	Covered	T6,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T12
DetectSt	168	Covered	T6,T9,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T12
DebounceSt->IdleSt	163	Covered	T246,T247,T248
DetectSt->IdleSt	186	Covered	T73,T74,T241
DetectSt->StableSt	191	Covered	T6,T9,T12
IdleSt->DebounceSt	148	Covered	T6,T9,T12
StableSt->IdleSt	206	Covered	T6,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T9,T12
0	1	Covered	T6,T9,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T246,T247,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T73,T74,T241
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T12
DetectSt	-	-	-	-	0	0	-	Covered	T6,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	3091	0	0
CntIncr_A	8699631	104658	0	0
CntNoWrap_A	8699631	8014564	0	0
DetectStDropOut_A	8699631	268	0	0
DetectedOut_A	8699631	70419	0	0
DetectedPulseOut_A	8699631	934	0	0
DisabledIdleSt_A	8699631	7572184	0	0
DisabledNoDetection_A	8699631	7574430	0	0
EnterDebounceSt_A	8699631	1570	0	0
EnterDetectSt_A	8699631	1522	0	0
EnterStableSt_A	8699631	934	0	0
PulseIsPulse_A	8699631	934	0	0
StayInStableSt	8699631	69393	0	0
gen_high_event_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	833	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	3091	0	0
T6	14245	44	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	42	0	0
T10	196046	0	0	0
T12	0	32	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	22	0	0
T44	0	30	0	0
T45	0	26	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	50	0	0
T72	0	18	0	0
T73	0	52	0	0
T74	0	42	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	104658	0	0
T6	14245	1584	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1197	0	0
T10	196046	0	0	0
T12	0	880	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	484	0	0
T44	0	1065	0	0
T45	0	1105	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	1150	0	0
T72	0	657	0	0
T73	0	3394	0	0
T74	0	1454	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8014564	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13780	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	268	0	0
T73	14788	8	0	0
T74	8284	20	0	0
T80	619	0	0	0
T95	0	8	0	0
T96	0	23	0	0
T99	0	4	0	0
T115	18895	0	0	0
T120	0	12	0	0
T160	838	0	0	0
T240	403	0	0	0
T241	11092	8	0	0
T242	674	0	0	0
T243	522	0	0	0
T244	406	0	0	0
T252	0	3	0	0
T253	0	6	0	0
T255	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	70419	0	0
T6	14245	1580	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1956	0	0
T10	196046	0	0	0
T12	0	1142	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1228	0	0
T44	0	594	0	0
T45	0	96	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	1523	0	0
T72	0	1118	0	0
T94	0	41	0	0
T115	0	1234	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	934	0	0
T6	14245	22	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	21	0	0
T10	196046	0	0	0
T12	0	16	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	15	0	0
T45	0	13	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	25	0	0
T72	0	9	0	0
T94	0	4	0	0
T115	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7572184	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	7283	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7574430	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	7284	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1570	0	0
T6	14245	22	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	21	0	0
T10	196046	0	0	0
T12	0	16	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	15	0	0
T45	0	13	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	25	0	0
T72	0	9	0	0
T73	0	26	0	0
T74	0	21	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1522	0	0
T6	14245	22	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	21	0	0
T10	196046	0	0	0
T12	0	16	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	15	0	0
T45	0	13	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	25	0	0
T72	0	9	0	0
T73	0	26	0	0
T74	0	21	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	934	0	0
T6	14245	22	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	21	0	0
T10	196046	0	0	0
T12	0	16	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	15	0	0
T45	0	13	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	25	0	0
T72	0	9	0	0
T94	0	4	0	0
T115	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	934	0	0
T6	14245	22	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	21	0	0
T10	196046	0	0	0
T12	0	16	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	15	0	0
T45	0	13	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	25	0	0
T72	0	9	0	0
T94	0	4	0	0
T115	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	69393	0	0
T6	14245	1557	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1934	0	0
T10	196046	0	0	0
T12	0	1126	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1217	0	0
T44	0	579	0	0
T45	0	83	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	1495	0	0
T72	0	1105	0	0
T94	0	37	0	0
T115	0	1218	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	833	0	0
T6	14245	21	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	20	0	0
T10	196046	0	0	0
T12	0	16	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	11	0	0
T44	0	15	0	0
T45	0	13	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	22	0	0
T72	0	5	0	0
T94	0	4	0	0
T115	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T6
0	1	Covered	T263,T264,T265
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T6
0	1	Covered	T4,T2,T6
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T2,T6
1	-	Covered	T4,T2,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T6
DetectSt	168	Covered	T4,T2,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T2,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T2,T6
DebounceSt->IdleSt	163	Covered	T4,T12,T51
DetectSt->IdleSt	186	Covered	T263,T264,T265
DetectSt->StableSt	191	Covered	T4,T2,T6
IdleSt->DebounceSt	148	Covered	T4,T2,T6
StableSt->IdleSt	206	Covered	T4,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T6
0	1	Covered	T4,T2,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T2,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T12,T51
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T263,T264,T265
DetectSt	-	-	-	-	0	1	-	Covered	T4,T2,T6
DetectSt	-	-	-	-	0	0	-	Covered	T4,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T4,T2,T6
StableSt	-	-	-	-	-	-	0	Covered	T4,T2,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	885	0	0
CntIncr_A	8699631	47280	0	0
CntNoWrap_A	8699631	8016770	0	0
DetectStDropOut_A	8699631	42	0	0
DetectedOut_A	8699631	15382	0	0
DetectedPulseOut_A	8699631	370	0	0
DisabledIdleSt_A	8699631	7650338	0	0
DisabledNoDetection_A	8699631	7652117	0	0
EnterDebounceSt_A	8699631	469	0	0
EnterDetectSt_A	8699631	416	0	0
EnterStableSt_A	8699631	370	0	0
PulseIsPulse_A	8699631	370	0	0
StayInStableSt	8699631	14990	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	346	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	885	0	0
T1	545	0	0	0
T2	9573	2	0	0
T3	949	0	0	0
T4	31438	15	0	0
T5	521	0	0	0
T6	14245	2	0	0
T7	1276	0	0	0
T9	0	2	0	0
T12	0	5	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	8	0	0
T35	0	10	0	0
T36	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	47280	0	0
T1	545	0	0	0
T2	9573	80	0	0
T3	949	0	0	0
T4	31438	554	0	0
T5	521	0	0	0
T6	14245	90	0	0
T7	1276	0	0	0
T9	0	78	0	0
T12	0	111	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	141	0	0
T33	0	138	0	0
T34	0	496	0	0
T35	0	835	0	0
T36	0	153	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8016770	0	0
T1	545	144	0	0
T2	9573	9155	0	0
T3	949	548	0	0
T4	31438	30937	0	0
T5	521	120	0	0
T6	14245	13822	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	42	0	0
T89	1395	0	0	0
T159	594	0	0	0
T180	875	0	0	0
T191	0	3	0	0
T257	0	11	0	0
T263	17705	3	0	0
T264	12009	1	0	0
T265	0	12	0	0
T266	0	1	0	0
T267	0	7	0	0
T268	0	3	0	0
T269	0	1	0	0
T270	702	0	0	0
T271	409	0	0	0
T272	1446	0	0	0
T273	502	0	0	0
T274	414	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	15382	0	0
T1	545	0	0	0
T2	9573	12	0	0
T3	949	0	0	0
T4	31438	33	0	0
T5	521	0	0	0
T6	14245	53	0	0
T7	1276	0	0	0
T9	0	76	0	0
T12	0	124	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	6	0	0
T33	0	94	0	0
T34	0	18	0	0
T35	0	34	0	0
T36	0	215	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	370	0	0
T1	545	0	0	0
T2	9573	1	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	5	0	0
T36	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7650338	0	0
T1	545	144	0	0
T2	9573	6042	0	0
T3	949	548	0	0
T4	31438	28204	0	0
T5	521	120	0	0
T6	14245	12245	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7652117	0	0
T1	545	145	0	0
T2	9573	6042	0	0
T3	949	549	0	0
T4	31438	28204	0	0
T5	521	121	0	0
T6	14245	12247	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	469	0	0
T1	545	0	0	0
T2	9573	1	0	0
T3	949	0	0	0
T4	31438	8	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T9	0	1	0	0
T12	0	3	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	5	0	0
T36	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	416	0	0
T1	545	0	0	0
T2	9573	1	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	5	0	0
T36	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	370	0	0
T1	545	0	0	0
T2	9573	1	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	5	0	0
T36	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	370	0	0
T1	545	0	0	0
T2	9573	1	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	5	0	0
T36	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	14990	0	0
T1	545	0	0	0
T2	9573	11	0	0
T3	949	0	0	0
T4	31438	26	0	0
T5	521	0	0	0
T6	14245	52	0	0
T7	1276	0	0	0
T9	0	75	0	0
T12	0	122	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	5	0	0
T33	0	92	0	0
T34	0	14	0	0
T35	0	29	0	0
T36	0	212	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	346	0	0
T1	545	0	0	0
T2	9573	1	0	0
T3	949	0	0	0
T4	31438	7	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T9	0	1	0	0
T12	0	2	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	5	0	0
T36	0	3	0	0