Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T9,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T12
1	0	Covered	T6,T9,T12
1	1	Covered	T6,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T12
0	1	Covered	T9,T73,T95
1	0	Covered	T9,T12,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T36,T44
0	1	Covered	T6,T36,T44
1	0	Covered	T9,T79

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T36
1	-	Covered	T6,T36,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T12
DetectSt	168	Covered	T6,T9,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T12
DebounceSt->IdleSt	163	Covered	T246,T247,T248
DetectSt->IdleSt	186	Covered	T9,T12,T73
DetectSt->StableSt	191	Covered	T6,T9,T36
IdleSt->DebounceSt	148	Covered	T6,T9,T12
StableSt->IdleSt	206	Covered	T6,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T9,T12
0	1	Covered	T6,T9,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T6,T9,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T246,T247,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T9,T12,T73
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T36
DetectSt	-	-	-	-	0	0	-	Covered	T6,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T6,T36,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	2793	0	0
CntIncr_A	8699631	99800	0	0
CntNoWrap_A	8699631	8014862	0	0
DetectStDropOut_A	8699631	181	0	0
DetectedOut_A	8699631	70987	0	0
DetectedPulseOut_A	8699631	907	0	0
DisabledIdleSt_A	8699631	7573057	0	0
DisabledNoDetection_A	8699631	7575296	0	0
EnterDebounceSt_A	8699631	1414	0	0
EnterDetectSt_A	8699631	1380	0	0
EnterStableSt_A	8699631	907	0	0
PulseIsPulse_A	8699631	907	0	0
StayInStableSt	8699631	69983	0	0
gen_high_event_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	808	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	2793	0	0
T6	14245	30	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	10	0	0
T10	196046	0	0	0
T12	0	6	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	50	0	0
T44	0	16	0	0
T45	0	4	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	20	0	0
T72	0	30	0	0
T73	0	50	0	0
T74	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	99800	0	0
T6	14245	1095	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	326	0	0
T10	196046	0	0	0
T12	0	166	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1200	0	0
T44	0	568	0	0
T45	0	170	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	490	0	0
T72	0	885	0	0
T73	0	3263	0	0
T74	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8014862	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	13794	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	181	0	0
T9	9686	1	0	0
T10	196046	0	0	0
T11	240873	0	0	0
T12	6527	0	0	0
T24	497	0	0	0
T27	2961	0	0	0
T34	20386	0	0	0
T53	281091	0	0	0
T54	422	0	0	0
T55	503	0	0	0
T73	0	9	0	0
T95	0	4	0	0
T96	0	10	0	0
T99	0	13	0	0
T146	0	1	0	0
T246	0	4	0	0
T254	0	8	0	0
T275	0	3	0	0
T276	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	70987	0	0
T6	14245	1818	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1921	0	0
T44	0	313	0	0
T45	0	14	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	300	0	0
T72	0	1841	0	0
T74	0	202	0	0
T115	0	1002	0	0
T241	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	907	0	0
T6	14245	15	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	25	0	0
T44	0	8	0	0
T45	0	2	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	10	0	0
T72	0	15	0	0
T74	0	1	0	0
T115	0	15	0	0
T241	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7573057	0	0
T1	545	144	0	0
T2	9573	9157	0	0
T3	949	548	0	0
T4	31438	30952	0	0
T5	521	120	0	0
T6	14245	6728	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7575296	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	6729	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1414	0	0
T6	14245	15	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	5	0	0
T10	196046	0	0	0
T12	0	3	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	25	0	0
T44	0	8	0	0
T45	0	2	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	10	0	0
T72	0	15	0	0
T73	0	25	0	0
T74	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	1380	0	0
T6	14245	15	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	5	0	0
T10	196046	0	0	0
T12	0	3	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	25	0	0
T44	0	8	0	0
T45	0	2	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	10	0	0
T72	0	15	0	0
T73	0	25	0	0
T74	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	907	0	0
T6	14245	15	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	25	0	0
T44	0	8	0	0
T45	0	2	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	10	0	0
T72	0	15	0	0
T74	0	1	0	0
T115	0	15	0	0
T241	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	907	0	0
T6	14245	15	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	1	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	25	0	0
T44	0	8	0	0
T45	0	2	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	10	0	0
T72	0	15	0	0
T74	0	1	0	0
T115	0	15	0	0
T241	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	69983	0	0
T6	14245	1802	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	1896	0	0
T44	0	305	0	0
T45	0	12	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	290	0	0
T72	0	1820	0	0
T74	0	200	0	0
T115	0	985	0	0
T120	0	1588	0	0
T241	0	37	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	808	0	0
T6	14245	14	0	0
T7	1276	0	0	0
T8	561	0	0	0
T9	9686	0	0	0
T10	196046	0	0	0
T16	405	0	0	0
T17	410	0	0	0
T26	507	0	0	0
T36	0	25	0	0
T44	0	8	0	0
T45	0	2	0	0
T58	407	0	0	0
T61	422	0	0	0
T71	0	10	0	0
T72	0	9	0	0
T115	0	13	0	0
T120	0	25	0	0
T241	0	4	0	0
T250	0	21	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T2,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T4,T2,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T2,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T2,T6
1	0	Covered	T4,T2,T6
1	1	Covered	T4,T2,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T6
0	1	Covered	T32,T35,T51
1	0	Covered	T78,T79

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T2,T6
0	1	Covered	T4,T2,T6
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T2,T6
1	-	Covered	T4,T2,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T2,T6
DetectSt	168	Covered	T4,T2,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T4,T2,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T2,T6
DebounceSt->IdleSt	163	Covered	T2,T51,T72
DetectSt->IdleSt	186	Covered	T32,T35,T51
DetectSt->StableSt	191	Covered	T4,T2,T6
IdleSt->DebounceSt	148	Covered	T4,T2,T6
StableSt->IdleSt	206	Covered	T4,T2,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T2,T6
0	1	Covered	T4,T2,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T2,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T2,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T78,T79
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T2,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T51,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T2,T6
DetectSt	-	-	-	-	1	-	-	Covered	T32,T35,T51
DetectSt	-	-	-	-	0	1	-	Covered	T4,T2,T6
DetectSt	-	-	-	-	0	0	-	Covered	T4,T2,T6
StableSt	-	-	-	-	-	-	1	Covered	T4,T2,T6
StableSt	-	-	-	-	-	-	0	Covered	T4,T2,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8699631	841	0	0
CntIncr_A	8699631	44349	0	0
CntNoWrap_A	8699631	8016814	0	0
DetectStDropOut_A	8699631	78	0	0
DetectedOut_A	8699631	13124	0	0
DetectedPulseOut_A	8699631	316	0	0
DisabledIdleSt_A	8699631	7667430	0	0
DisabledNoDetection_A	8699631	7669230	0	0
EnterDebounceSt_A	8699631	445	0	0
EnterDetectSt_A	8699631	397	0	0
EnterStableSt_A	8699631	316	0	0
PulseIsPulse_A	8699631	316	0	0
StayInStableSt	8699631	12763	0	0
gen_high_level_sva.HighLevelEvent_A	8699631	8020084	0	0
gen_not_sticky_sva.StableStDropOut_A	8699631	269	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	841	0	0
T1	545	0	0	0
T2	9573	5	0	0
T3	949	0	0	0
T4	31438	20	0	0
T5	521	0	0	0
T6	14245	2	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	2	0	0
T33	0	4	0	0
T34	0	8	0	0
T35	0	8	0	0
T36	0	8	0	0
T51	0	18	0	0
T72	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	44349	0	0
T1	545	0	0	0
T2	9573	225	0	0
T3	949	0	0	0
T4	31438	410	0	0
T5	521	0	0	0
T6	14245	57	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	147	0	0
T33	0	158	0	0
T34	0	268	0	0
T35	0	697	0	0
T36	0	240	0	0
T51	0	1246	0	0
T72	0	441	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8016814	0	0
T1	545	144	0	0
T2	9573	9152	0	0
T3	949	548	0	0
T4	31438	30932	0	0
T5	521	120	0	0
T6	14245	13822	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	78	0	0
T23	386866	0	0	0
T32	17946	1	0	0
T35	0	4	0	0
T37	721	0	0	0
T47	808	0	0	0
T48	695	0	0	0
T51	0	8	0	0
T59	201326	0	0	0
T65	0	2	0	0
T68	525	0	0	0
T69	522	0	0	0
T70	471	0	0	0
T102	0	2	0	0
T119	503	0	0	0
T211	0	2	0	0
T277	0	2	0	0
T278	0	4	0	0
T279	0	2	0	0
T280	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	13124	0	0
T1	545	0	0	0
T2	9573	21	0	0
T3	949	0	0	0
T4	31438	400	0	0
T5	521	0	0	0
T6	14245	87	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T33	0	74	0	0
T34	0	246	0	0
T36	0	250	0	0
T72	0	222	0	0
T74	0	41	0	0
T115	0	64	0	0
T116	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	316	0	0
T1	545	0	0	0
T2	9573	2	0	0
T3	949	0	0	0
T4	31438	10	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	4	0	0
T72	0	5	0	0
T74	0	1	0	0
T115	0	1	0	0
T116	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7667430	0	0
T1	545	144	0	0
T2	9573	6042	0	0
T3	949	548	0	0
T4	31438	28204	0	0
T5	521	120	0	0
T6	14245	12007	0	0
T7	1276	875	0	0
T13	502	101	0	0
T14	417	16	0	0
T15	472	71	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	7669230	0	0
T1	545	145	0	0
T2	9573	6042	0	0
T3	949	549	0	0
T4	31438	28204	0	0
T5	521	121	0	0
T6	14245	12009	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	445	0	0
T1	545	0	0	0
T2	9573	3	0	0
T3	949	0	0	0
T4	31438	10	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	0	4	0	0
T51	0	10	0	0
T72	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	397	0	0
T1	545	0	0	0
T2	9573	2	0	0
T3	949	0	0	0
T4	31438	10	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T32	0	1	0	0
T33	0	2	0	0
T34	0	4	0	0
T35	0	4	0	0
T36	0	4	0	0
T51	0	8	0	0
T72	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	316	0	0
T1	545	0	0	0
T2	9573	2	0	0
T3	949	0	0	0
T4	31438	10	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	4	0	0
T72	0	5	0	0
T74	0	1	0	0
T115	0	1	0	0
T116	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	316	0	0
T1	545	0	0	0
T2	9573	2	0	0
T3	949	0	0	0
T4	31438	10	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	4	0	0
T72	0	5	0	0
T74	0	1	0	0
T115	0	1	0	0
T116	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	12763	0	0
T1	545	0	0	0
T2	9573	19	0	0
T3	949	0	0	0
T4	31438	390	0	0
T5	521	0	0	0
T6	14245	86	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T33	0	72	0	0
T34	0	242	0	0
T36	0	246	0	0
T72	0	215	0	0
T74	0	40	0	0
T115	0	63	0	0
T116	0	150	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	8020084	0	0
T1	545	145	0	0
T2	9573	9160	0	0
T3	949	549	0	0
T4	31438	30966	0	0
T5	521	121	0	0
T6	14245	13827	0	0
T7	1276	876	0	0
T13	502	102	0	0
T14	417	17	0	0
T15	472	72	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8699631	269	0	0
T1	545	0	0	0
T2	9573	2	0	0
T3	949	0	0	0
T4	31438	10	0	0
T5	521	0	0	0
T6	14245	1	0	0
T7	1276	0	0	0
T13	502	0	0	0
T14	417	0	0	0
T15	472	0	0	0
T33	0	2	0	0
T34	0	4	0	0
T36	0	4	0	0
T72	0	3	0	0
T74	0	1	0	0
T115	0	1	0	0
T116	0	10	0	0