Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	95.12	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	4	58	93.55

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	4	27	87.10	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2024

1

T1

4

T3

9

T4

22

auto[1]

619

1

T3

3

T4

6

T19

4

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1967

1

T1

3

T3

9

T4

28

auto[1]

676

1

T1

1

T3

3

T19

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2016

1

T1

4

T3

12

T4

21

auto[1]

627

1

T4

7

T19

11

T20

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2004

1

T1

3

T3

12

T4

23

auto[1]

639

1

T1

1

T4

5

T19

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2376

1

T1

3

T3

12

T4

27

auto[1]

267

1

T1

1

T4

1

T273

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2411

1

T1

4

T3

12

T4

16

auto[1]

232

1

T4

12

T24

7

T63

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2422

1

T1

4

T3

9

T4

23

auto[1]

221

1

T3

3

T4

5

T11

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2332

1

T1

4

T3

9

T4

22

auto[1]

311

1

T3

3

T4

6

T11

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2402

1

T1

4

T3

12

T4

27

auto[1]

241

1

T4

1

T24

8

T63

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1956

1

T1

3

T3

12

T4

23

auto[1]

687

1

T1

1

T4

5

T20

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	4	27	87.10	4
Automatically Generated Cross Bins	31	4	27	87.10	4
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	808	1			T19	11		T20	3		T8	5
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	77	1			T1	1		T160	5		T366	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	50	1			T24	5		T160	5		T194	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	18	1			T356	1		T68	4		T194	3
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	99	1			T11	2		T24	5		T242	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	11	1			T244	3		T367	2		T253	1
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	40	1			T275	19		T356	5		T278	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	33	1			T275	30		T195	3		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	63	1			T279	2		T242	9		T274	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	22	1			T68	1		T368	5		T224	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	13	1			T242	8		T278	3		T281	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	3	1			T369	3		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	37	1			T3	3		T11	2		T352	8
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	6	1			T370	1		T371	5		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T372	1		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[1]	2	1			T368	2		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	70	1			T24	4		T274	3		T194	5
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	17	1			T244	3		T373	2		T223	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	31	1			T24	3		T63	4		T278	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	2	1			T4	1		T372	1		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	36	1			T4	6		T244	4		T223	2
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	6	1			T366	1		T369	4		T374	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	28	1			T4	5		T63	1		T373	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	3	1			T195	3		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T352	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	2	1			T195	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T371	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

76

1

T25

16

T77

1

T242

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

134

1

T63

1

T244

6

T274

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

51

1

T10

1

T74

10

T132

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

119

1

T24

4

T25

8

T63

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

68

1

T26

4

T27

3

T80

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

40

1

T4

5

T26

4

T375

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

33

1

T246

4

T316

3

T254

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

100

1

T4

1

T132

10

T275

15

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

73

1

T4

6

T40

6

T24

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T79

1

T68

7

T368

8

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

15

1

T93

2

T25

1

T26

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

24

1

T24

3

T175

1

T240

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T40

3

T27

1

T64

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

29

1

T20

1

T40

3

T94

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

23

1

T93

2

T27

1

T348

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

112

1

T8

3

T376

8

T160

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

55

1

T3

3

T242

8

T79

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

105

1

T11

2

T52

6

T122

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T24

5

T52

4

T76

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

62

1

T94

5

T240

3

T160

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

18

1

T8

2

T348

2

T351

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

39

1

T1

1

T77

1

T368

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T375

2

T321

2

T354

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

57

1

T19

7

T122

8

T366

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T77

2

T242

8

T370

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

25

1

T349

4

T81

5

T377

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T11

2

T33

1

T77

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

18

1

T20

1

T77

1

T376

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

19

1

T19

4

T349

1

T272

4

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T20

1

T132

2

T326

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T93

2

T375

1

T348

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded