Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1149

1

T2

26

T12

10

T8

25

auto[1]

1170

1

T2

34

T12

10

T8

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

559

1

T2

16

T12

6

T8

9

from_0to1

555

1

T2

16

T12

6

T8

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1162

1

T2

31

T12

10

T8

22

auto[1]

1157

1

T2

29

T12

10

T8

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T2

26

T12

12

T8

17

auto[1]

1190

1

T2

34

T12

8

T8

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T2

3

T8

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T2

2

T8

2

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T8

2

T33

3

T77

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T2

2

T12

2

T33

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T2

2

T12

2

T60

2

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T2

1

T8

4

T61

2

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T2

2

T33

4

T37

2

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T12

2

T8

2

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T12

2

T8

2

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T2

4

T8

1

T33

2

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T2

5

T12

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

81

1

T12

1

T8

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T2

1

T12

1

T33

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T2

5

T8

1

T33

2

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T2

1

T12

1

T33

4

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T2

4

T8

1

T60

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1183

1

T2

31

T12

9

T8

18

auto[1]

1136

1

T2

29

T12

11

T8

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

570

1

T2

15

T12

5

T8

10

from_0to1

567

1

T2

14

T12

6

T8

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1203

1

T2

35

T12

7

T8

18

auto[1]

1116

1

T2

25

T12

13

T8

22

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1187

1

T2

28

T12

9

T8

15

auto[1]

1132

1

T2

32

T12

11

T8

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T2

1

T8

2

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T2

2

T12

1

T8

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T2

4

T33

2

T37

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T12

1

T8

1

T33

3

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T2

1

T33

2

T175

1

auto[0]

from_0to1

auto[0]

auto[1]

86

1

T2

3

T12

1

T8

1

auto[0]

from_0to1

auto[1]

auto[0]

82

1

T8

2

T60

1

T33

1

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T2

1

T12

2

T8

2

auto[1]

from_1to0

auto[0]

auto[0]

81

1

T2

1

T60

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T2

3

T12

1

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T2

2

T12

2

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T2

2

T8

3

T33

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T61

1

T33

1

T168

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T2

3

T8

2

T60

2

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T2

2

T12

2

T8

4

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T2

4

T12

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184

1

T2

27

T12

11

T8

22

auto[1]

1135

1

T2

33

T12

9

T8

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

564

1

T2

15

T12

3

T8

10

from_0to1

566

1

T2

15

T12

3

T8

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1142

1

T2

27

T12

10

T8

23

auto[1]

1177

1

T2

33

T12

10

T8

17

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1112

1

T2

29

T12

10

T8

17

auto[1]

1207

1

T2

31

T12

10

T8

23

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T2

1

T12

1

T8

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T2

2

T33

2

T168

2

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T2

1

T61

1

T33

3

auto[0]

from_1to0

auto[1]

auto[1]

83

1

T2

1

T12

1

T8

2

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T8

2

T60

1

T33

5

auto[0]

from_0to1

auto[0]

auto[1]

87

1

T2

3

T8

4

T33

7

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T2

2

T61

1

T33

3

auto[0]

from_0to1

auto[1]

auto[1]

83

1

T2

3

T12

2

T8

3

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T8

2

T60

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T2

3

T8

3

T60

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T2

6

T12

1

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T2

1

T8

1

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

73

1

T2

1

T12

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T2

1

T60

1

T61

3

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T2

1

T33

1

T37

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T2

4

T8

1

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1130

1

T2

30

T12

12

T8

23

auto[1]

1189

1

T2

30

T12

8

T8

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

557

1

T2

14

T12

2

T8

12

from_0to1

556

1

T2

13

T12

2

T8

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T2

39

T12

11

T8

21

auto[1]

1156

1

T2

21

T12

9

T8

19

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1143

1

T2

29

T12

8

T8

21

auto[1]

1176

1

T2

31

T12

12

T8

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T8

4

T60

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T2

5

T8

1

T33

2

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T2

1

T8

2

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T2

1

T60

1

T33

4

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T2

4

T12

1

T8

4

auto[0]

from_0to1

auto[0]

auto[1]

78

1

T2

1

T12

1

T8

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T2

2

T8

2

T33

3

auto[0]

from_0to1

auto[1]

auto[1]

57

1

T2

1

T8

1

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T2

1

T8

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

84

1

T2

4

T8

2

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

88

1

T2

1

T12

1

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T2

1

T12

1

T8

1

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T2

2

T60

1

T33

3

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T2

1

T60

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T2

2

T8

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T8

2

T60

1

T61

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T2

25

T12

6

T8

22

auto[1]

1212

1

T2

35

T12

14

T8

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

556

1

T2

14

T12

5

T8

10

from_0to1

556

1

T2

14

T12

4

T8

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1172

1

T2

33

T12

9

T8

25

auto[1]

1147

1

T2

27

T12

11

T8

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T2

32

T12

8

T8

12

auto[1]

1188

1

T2

28

T12

12

T8

28

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T2

4

T8

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

75

1

T2

1

T8

1

T33

3

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T60

1

T33

1

T175

1

auto[0]

from_1to0

auto[1]

auto[1]

79

1

T2

1

T12

2

T8

2

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T2

3

T8

1

T61

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T2

2

T8

2

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T12

1

T8

2

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T2

1

T33

3

T37

1

auto[1]

from_1to0

auto[0]

auto[0]

77

1

T2

1

T60

1

T33

3

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T2

1

T12

1

T8

3

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T2

5

T12

1

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T2

1

T12

1

T8

2

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T2

1

T8

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T2

3

T12

3

T8

2

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T61

1

T33

4

T168

1

auto[1]

from_0to1

auto[1]

auto[1]

73

1

T2

4

T8

2

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1163

1

T2

33

T12

13

T8

22

auto[1]

1156

1

T2

27

T12

7

T8

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

567

1

T2

16

T12

5

T8

10

from_0to1

558

1

T2

16

T12

5

T8

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T2

21

T12

7

T8

17

auto[1]

1198

1

T2

39

T12

13

T8

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1198

1

T2

33

T12

8

T8

21

auto[1]

1121

1

T2

27

T12

12

T8

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T2

3

T12

1

T8

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T2

1

T12

1

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T2

4

T12

1

T8

3

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T2

3

T8

2

T33

3

auto[0]

from_0to1

auto[0]

auto[0]

77

1

T2

2

T33

1

T168

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T2

2

T60

1

T33

4

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T2

3

T12

1

T8

2

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T2

1

T12

2

T8

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T2

2

T8

1

T61

1

auto[1]

from_1to0

auto[0]

auto[1]

63

1

T2

2

T12

1

T8

1

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T2

1

T60

2

T33

7

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T12

1

T8

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T2

1

T8

2

T33

1

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T2

1

T8

2

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T2

3

T12

2

T8

2

auto[1]

from_0to1

auto[1]

auto[1]

76

1

T2

3

T60

1

T33

4

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1196

1

T2

30

T12

9

T8

23

auto[1]

1123

1

T2

30

T12

11

T8

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

535

1

T2

15

T12

4

T8

9

from_0to1

531

1

T2

16

T12

3

T8

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1121

1

T2

33

T12

9

T8

22

auto[1]

1198

1

T2

27

T12

11

T8

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1164

1

T2

37

T12

7

T8

16

auto[1]

1155

1

T2

23

T12

13

T8

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T2

2

T8

1

T33

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T2

2

T8

3

T61

2

auto[0]

from_1to0

auto[1]

auto[0]

80

1

T2

4

T60

1

T61

2

auto[0]

from_1to0

auto[1]

auto[1]

90

1

T2

2

T12

1

T8

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T2

1

T8

1

T33

5

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T2

2

T8

2

T33

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T12

1

T175

2

T73

3

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T2

1

T8

4

T61

1

auto[1]

from_1to0

auto[0]

auto[0]

48

1

T2

2

T33

2

T73

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T12

1

T8

2

T33

2

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T2

1

T12

2

T8

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T2

2

T8

1

T61

1

auto[1]

from_0to1

auto[0]

auto[0]

79

1

T2

5

T8

1

T60

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T2

2

T12

1

T8

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T2

4

T60

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T2

1

T12

1

T168

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1145

1

T2

28

T12

10

T8

18

auto[1]

1174

1

T2

32

T12

10

T8

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

550

1

T2

13

T12

5

T8

9

from_0to1

556

1

T2

12

T12

6

T8

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1192

1

T2

34

T12

13

T8

20

auto[1]

1127

1

T2

26

T12

7

T8

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1176

1

T2

34

T12

12

T8

25

auto[1]

1143

1

T2

26

T12

8

T8

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T12

1

T8

1

T60

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T2

2

T12

1

T8

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T12

1

T8

1

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T2

5

T8

1

T33

5

auto[0]

from_0to1

auto[0]

auto[0]

82

1

T2

2

T12

1

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T8

1

T60

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T2

2

T8

3

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

80

1

T12

3

T61

1

T33

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T2

3

T12

1

T8

2

auto[1]

from_1to0

auto[0]

auto[1]

68

1

T2

2

T60

1

T61

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T2

1

T8

2

T60

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T12

1

T8

1

T60

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T2

2

T12

2

T8

3

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T2

1

T8

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T2

3

T8

1

T33

5

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T2

2

T60

2

T168

1