Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156844	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119708

1

T6

22

T1

302

T2

532

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	142872	1			T6	22		T1	247		T2	606
values[0x0]	66005	1			T6	11		T1	308		T2	255
values[0x1]	67675	1			T6	12		T1	313		T2	302

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127315	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149237

1

T6

23

T1

367

T2

645

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1014	1			T3	4		T14	2		T15	1
valid_sources[0x01]	1067	1			T6	3		T2	2		T12	1
valid_sources[0x02]	1080	1			T2	13		T14	1		T4	4
valid_sources[0x03]	1042	1			T2	7		T3	6		T4	4
valid_sources[0x04]	3264	1			T2	3		T3	4		T4	4
valid_sources[0x05]	1005	1			T2	7		T4	6		T20	1
valid_sources[0x06]	985	1			T2	7		T3	6		T4	4
valid_sources[0x07]	1689	1			T6	2		T2	17		T3	1
valid_sources[0x08]	1065	1			T2	4		T13	1		T3	4
valid_sources[0x09]	809	1			T2	5		T3	7		T4	3
valid_sources[0x0a]	928	1			T2	4		T12	3		T3	4
valid_sources[0x0b]	914	1			T2	3		T12	1		T3	4
valid_sources[0x0c]	807	1			T2	3		T3	8		T4	2
valid_sources[0x0d]	1191	1			T3	2		T4	3		T20	3
valid_sources[0x0e]	916	1			T2	1		T12	1		T3	2
valid_sources[0x0f]	960	1			T2	3		T12	1		T3	5
valid_sources[0x10]	1180	1			T2	21		T12	1		T15	1
valid_sources[0x11]	1990	1			T6	1		T2	1		T12	3
valid_sources[0x12]	792	1			T2	4		T12	1		T3	7
valid_sources[0x13]	1261	1			T3	2		T4	3		T19	2
valid_sources[0x14]	837	1			T2	5		T3	11		T15	2
valid_sources[0x15]	893	1			T2	6		T12	2		T3	5
valid_sources[0x16]	909	1			T2	2		T3	3		T4	5
valid_sources[0x17]	1026	1			T2	9		T3	5		T4	4
valid_sources[0x18]	744	1			T2	5		T4	5		T19	1
valid_sources[0x19]	890	1			T2	8		T3	2		T4	5
valid_sources[0x1a]	880	1			T2	1		T12	1		T3	9
valid_sources[0x1b]	788	1			T2	3		T12	2		T3	5
valid_sources[0x1c]	910	1			T2	3		T3	6		T4	4
valid_sources[0x1d]	1822	1			T2	6		T3	11		T4	3
valid_sources[0x1e]	856	1			T12	1		T3	3		T4	5
valid_sources[0x1f]	842	1			T6	2		T2	2		T3	2
valid_sources[0x20]	738	1			T3	1		T14	1		T4	2
valid_sources[0x21]	799	1			T2	2		T3	3		T4	3
valid_sources[0x22]	1578	1			T2	1		T12	1		T3	2
valid_sources[0x23]	1124	1			T2	5		T12	1		T3	9
valid_sources[0x24]	982	1			T12	1		T4	2		T5	2
valid_sources[0x25]	873	1			T2	7		T12	1		T13	1
valid_sources[0x26]	916	1			T12	4		T3	1		T4	6
valid_sources[0x27]	846	1			T2	5		T12	1		T3	8
valid_sources[0x28]	1808	1			T2	7		T12	1		T3	7
valid_sources[0x29]	979	1			T2	8		T3	5		T4	2
valid_sources[0x2a]	1759	1			T2	4		T3	2		T4	5
valid_sources[0x2b]	1045	1			T2	5		T12	1		T3	6
valid_sources[0x2c]	1395	1			T2	3		T3	5		T4	3
valid_sources[0x2d]	931	1			T2	6		T3	4		T4	5
valid_sources[0x2e]	858	1			T3	3		T14	1		T4	3
valid_sources[0x2f]	1166	1			T2	15		T3	7		T14	2
valid_sources[0x30]	823	1			T2	5		T12	2		T13	1
valid_sources[0x31]	1755	1			T6	5		T2	9		T3	2
valid_sources[0x32]	973	1			T2	7		T3	5		T4	2
valid_sources[0x33]	1202	1			T6	2		T3	4		T4	2
valid_sources[0x34]	921	1			T2	13		T3	3		T4	6
valid_sources[0x35]	1002	1			T2	2		T3	7		T4	4
valid_sources[0x36]	920	1			T2	6		T3	6		T4	3
valid_sources[0x37]	1026	1			T2	5		T12	2		T3	1
valid_sources[0x38]	1303	1			T2	7		T12	1		T3	3
valid_sources[0x39]	1051	1			T2	9		T3	3		T4	6
valid_sources[0x3a]	1019	1			T2	6		T3	1		T4	5
valid_sources[0x3b]	2010	1			T2	4		T3	1		T4	4
valid_sources[0x3c]	825	1			T2	7		T3	1		T14	1
valid_sources[0x3d]	954	1			T6	5		T2	3		T14	1
valid_sources[0x3e]	1002	1			T12	1		T3	7		T4	6
valid_sources[0x3f]	1079	1			T2	3		T4	3		T19	1
valid_sources[0x40]	929	1			T2	5		T4	2		T7	1
valid_sources[0x41]	1014	1			T2	17		T12	2		T3	7
valid_sources[0x42]	949	1			T2	13		T3	4		T4	5
valid_sources[0x43]	1214	1			T2	6		T3	4		T4	4
valid_sources[0x44]	1336	1			T2	10		T3	2		T4	2
valid_sources[0x45]	1665	1			T2	6		T3	2		T4	3
valid_sources[0x46]	993	1			T3	2		T19	1		T20	3
valid_sources[0x47]	921	1			T6	1		T2	4		T3	1
valid_sources[0x48]	957	1			T6	1		T2	1		T3	1
valid_sources[0x49]	1422	1			T2	5		T3	1		T4	2
valid_sources[0x4a]	895	1			T12	1		T3	8		T4	3
valid_sources[0x4b]	881	1			T2	8		T12	1		T4	1
valid_sources[0x4c]	951	1			T3	9		T4	5		T5	18
valid_sources[0x4d]	931	1			T3	2		T4	2		T19	1
valid_sources[0x4e]	837	1			T3	2		T4	6		T19	2
valid_sources[0x4f]	982	1			T12	1		T3	5		T4	5
valid_sources[0x50]	1200	1			T2	1		T3	3		T4	3
valid_sources[0x51]	1623	1			T2	15		T20	1		T8	4
valid_sources[0x52]	863	1			T2	3		T12	4		T3	2
valid_sources[0x53]	844	1			T6	2		T2	1		T3	7
valid_sources[0x54]	1490	1			T6	1		T2	6		T12	3
valid_sources[0x55]	806	1			T3	6		T4	3		T19	2
valid_sources[0x56]	1006	1			T3	8		T14	2		T4	5
valid_sources[0x57]	763	1			T2	3		T12	1		T3	1
valid_sources[0x58]	1907	1			T2	2		T3	2		T4	2
valid_sources[0x59]	1243	1			T2	5		T3	3		T14	1
valid_sources[0x5a]	772	1			T2	4		T3	2		T14	1
valid_sources[0x5b]	2560	1			T14	1		T15	1		T4	4
valid_sources[0x5c]	999	1			T2	4		T12	1		T3	2
valid_sources[0x5d]	950	1			T2	1		T3	3		T4	4
valid_sources[0x5e]	1029	1			T3	3		T4	4		T19	1
valid_sources[0x5f]	910	1			T2	5		T12	1		T3	1
valid_sources[0x60]	889	1			T12	2		T3	8		T14	1
valid_sources[0x61]	830	1			T2	8		T3	2		T4	1
valid_sources[0x62]	1307	1			T2	2		T3	1		T4	4
valid_sources[0x63]	900	1			T12	1		T3	1		T4	4
valid_sources[0x64]	865	1			T6	2		T2	1		T12	1
valid_sources[0x65]	797	1			T2	1		T12	1		T3	1
valid_sources[0x66]	922	1			T2	1		T3	4		T4	6
valid_sources[0x67]	1024	1			T2	2		T13	5		T3	3
valid_sources[0x68]	960	1			T2	7		T12	2		T13	1
valid_sources[0x69]	887	1			T2	10		T12	1		T3	1
valid_sources[0x6a]	783	1			T6	2		T2	11		T4	3
valid_sources[0x6b]	1056	1			T2	3		T12	2		T3	8
valid_sources[0x6c]	1671	1			T1	868		T2	3		T3	3
valid_sources[0x6d]	827	1			T3	5		T4	4		T7	1
valid_sources[0x6e]	1008	1			T2	9		T3	2		T4	11
valid_sources[0x6f]	756	1			T2	8		T3	1		T14	1
valid_sources[0x70]	1458	1			T2	2		T3	2		T4	1
valid_sources[0x71]	1527	1			T12	4		T3	3		T4	5
valid_sources[0x72]	980	1			T2	3		T3	3		T4	5
valid_sources[0x73]	779	1			T2	8		T3	2		T4	8
valid_sources[0x74]	874	1			T4	5		T19	1		T20	3
valid_sources[0x75]	838	1			T2	4		T3	2		T4	4
valid_sources[0x76]	899	1			T2	16		T4	1		T19	3
valid_sources[0x77]	786	1			T2	3		T3	1		T4	3
valid_sources[0x78]	1631	1			T3	8		T14	2		T4	2
valid_sources[0x79]	904	1			T3	4		T15	2		T4	6
valid_sources[0x7a]	853	1			T2	7		T12	1		T3	4
valid_sources[0x7b]	831	1			T3	2		T4	1		T19	1
valid_sources[0x7c]	936	1			T3	6		T4	2		T19	3
valid_sources[0x7d]	744	1			T2	2		T12	4		T3	1
valid_sources[0x7e]	1044	1			T2	1		T3	4		T4	3
valid_sources[0x7f]	2321	1			T2	1		T3	6		T15	1
valid_sources[0x80]	881	1			T2	6		T4	6		T20	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

65629

1

T6

12

T1

126

T2

323

values[0x0]

all_enables

biggest_size

31693

1

T6

7

T1

117

T2

122

values[0x1]

all_enables

biggest_size

22386

1

T6

3

T1

59

T2

87