Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T13,T15

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T2,T13,T15

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T15,T5

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T15
1	0	Covered	T6,T1,T2
1	1	Covered	T2,T13,T15

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T5
0	1	Covered	T8,T67,T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T5
0	1	Covered	T2,T15,T5
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T15,T5
1	-	Covered	T2,T15,T5

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T15
DetectSt	168	Covered	T2,T15,T5
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T15,T5

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T15,T5
DebounceSt->IdleSt	163	Covered	T13,T15,T5
DetectSt->IdleSt	186	Covered	T8,T67,T78
DetectSt->StableSt	191	Covered	T2,T15,T5
IdleSt->DebounceSt	148	Covered	T2,T13,T15
StableSt->IdleSt	206	Covered	T2,T15,T5

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T15
0	1	Covered	T2,T13,T15
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T5
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T15
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T15,T5
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T15,T5
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T15
DetectSt	-	-	-	-	1	-	-	Covered	T8,T67,T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T15,T5
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T15,T5
StableSt	-	-	-	-	-	-	0	Covered	T2,T15,T5
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	298	0	0
CntIncr_A	7939905	173346	0	0
CntNoWrap_A	7939905	7282449	0	0
DetectStDropOut_A	7939905	6	0	0
DetectedOut_A	7939905	812	0	0
DetectedPulseOut_A	7939905	128	0	0
DisabledIdleSt_A	7939905	7102359	0	0
DisabledNoDetection_A	7939905	7104647	0	0
EnterDebounceSt_A	7939905	170	0	0
EnterDetectSt_A	7939905	134	0	0
EnterStableSt_A	7939905	128	0	0
PulseIsPulse_A	7939905	128	0	0
StayInStableSt	7939905	684	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	7284	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	128	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	298	0	0
T2	14606	6	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	7	0	0
T7	516679	0	0	0
T8	0	6	0	0
T10	0	10	0	0
T12	501	0	0	0
T13	691	2	0	0
T14	539	0	0	0
T15	727	3	0	0
T28	0	1	0	0
T41	0	3	0	0
T42	0	5	0	0
T44	0	4	0	0
T47	934	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	173346	0	0
T2	14606	134	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	169	0	0
T7	516679	0	0	0
T8	0	17728	0	0
T10	0	238	0	0
T12	501	0	0	0
T13	691	106	0	0
T14	539	0	0	0
T15	727	111	0	0
T28	0	40	0	0
T41	0	107	0	0
T42	0	163	0	0
T44	0	91	0	0
T47	934	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282449	0	0
T1	8369	7958	0	0
T2	14606	4979	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92543	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	288	0	0
T14	539	138	0	0
T15	727	323	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6	0	0
T8	49691	1	0	0
T9	777	0	0	0
T10	16230	0	0	0
T11	11085	0	0	0
T40	21978	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T67	0	1	0	0
T75	427	0	0	0
T78	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	812	0	0
T2	14606	18	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	22	0	0
T7	516679	0	0	0
T8	0	14	0	0
T10	0	31	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	4	0	0
T37	0	3	0	0
T41	0	2	0	0
T42	0	9	0	0
T44	0	17	0	0
T47	934	0	0	0
T95	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	128	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	3	0	0
T7	516679	0	0	0
T8	0	2	0	0
T10	0	5	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	934	0	0	0
T95	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7102359	0	0
T1	8369	7958	0	0
T2	14606	4734	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92218	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	122	0	0
T14	539	138	0	0
T15	727	133	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7104647	0	0
T1	8369	7960	0	0
T2	14606	4757	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92232	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	123	0	0
T14	539	139	0	0
T15	727	133	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	170	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	4	0	0
T7	516679	0	0	0
T8	0	4	0	0
T10	0	5	0	0
T12	501	0	0	0
T13	691	2	0	0
T14	539	0	0	0
T15	727	2	0	0
T28	0	1	0	0
T41	0	2	0	0
T42	0	3	0	0
T44	0	2	0	0
T47	934	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	134	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	3	0	0
T7	516679	0	0	0
T8	0	3	0	0
T10	0	5	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	934	0	0	0
T95	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	128	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	3	0	0
T7	516679	0	0	0
T8	0	2	0	0
T10	0	5	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	934	0	0	0
T95	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	128	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	3	0	0
T7	516679	0	0	0
T8	0	2	0	0
T10	0	5	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	934	0	0	0
T95	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	684	0	0
T2	14606	15	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	19	0	0
T7	516679	0	0	0
T8	0	12	0	0
T10	0	26	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	3	0	0
T37	0	2	0	0
T41	0	1	0	0
T42	0	7	0	0
T44	0	15	0	0
T47	934	0	0	0
T95	0	8	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7284	0	0
T1	8369	29	0	0
T2	14606	58	0	0
T3	12699	32	0	0
T4	13206	32	0	0
T5	97815	28	0	0
T6	495	6	0	0
T12	501	5	0	0
T13	691	3	0	0
T14	539	5	0	0
T15	727	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	128	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	3	0	0
T7	516679	0	0	0
T8	0	2	0	0
T10	0	5	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	1	0	0
T37	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	934	0	0	0
T95	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T6,T1,T2
1	1	Covered	T2,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Covered	T9,T56,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T8,T9
0	1	Unreachable
1	0	Covered	T8,T9,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T8
DetectSt	168	Covered	T2,T8,T9
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T8,T9
DebounceSt->IdleSt	163	Covered	T7,T28,T97
DetectSt->IdleSt	186	Covered	T9,T56,T73
DetectSt->StableSt	191	Covered	T2,T8,T9
IdleSt->DebounceSt	148	Covered	T2,T7,T8
StableSt->IdleSt	206	Covered	T2,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T8,T9
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T97,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T9,T56,T73
DetectSt	-	-	-	-	0	1	-	Covered	T2,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T54
StableSt	-	-	-	-	-	-	0	Covered	T2,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	181	0	0
CntIncr_A	7939905	65532	0	0
CntNoWrap_A	7939905	7282566	0	0
DetectStDropOut_A	7939905	19	0	0
DetectedOut_A	7939905	155087	0	0
DetectedPulseOut_A	7939905	57	0	0
DisabledIdleSt_A	7939905	5208943	0	0
DisabledNoDetection_A	7939905	5211297	0	0
EnterDebounceSt_A	7939905	105	0	0
EnterDetectSt_A	7939905	76	0	0
EnterStableSt_A	7939905	57	0	0
PulseIsPulse_A	7939905	57	0	0
StayInStableSt	7939905	155030	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	7284	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_sticky_sva.StableStDropOut_A	7939905	1271637	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	181	0	0
T2	14606	2	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	5	0	0
T8	0	2	0	0
T9	0	4	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	2	0	0
T37	0	2	0	0
T47	934	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	12	0	0
T64	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	65532	0	0
T2	14606	70	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	195	0	0
T8	0	92	0	0
T9	0	48	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	63	0	0
T37	0	29	0	0
T47	934	0	0	0
T54	0	35	0	0
T55	0	44	0	0
T56	0	492	0	0
T64	0	28468	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282566	0	0
T1	8369	7958	0	0
T2	14606	4983	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	19	0	0
T9	777	1	0	0
T10	16230	0	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T40	21978	0	0	0
T56	0	5	0	0
T60	504	0	0	0
T61	519	0	0	0
T73	0	3	0	0
T75	427	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T97	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	3	0	0
T103	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	155087	0	0
T2	14606	441	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	398	0	0
T9	0	53	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	157	0	0
T47	934	0	0	0
T54	0	48	0	0
T55	0	394	0	0
T56	0	335	0	0
T64	0	72188	0	0
T70	0	428	0	0
T73	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	57	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T64	0	2	0	0
T70	0	2	0	0
T73	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	5208943	0	0
T1	8369	7958	0	0
T2	14606	4363	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	5211297	0	0
T1	8369	7960	0	0
T2	14606	4386	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	105	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	5	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	2	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	6	0	0
T64	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	76	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	6	0	0
T64	0	2	0	0
T70	0	2	0	0
T73	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	57	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T64	0	2	0	0
T70	0	2	0	0
T73	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	57	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T64	0	2	0	0
T70	0	2	0	0
T73	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	155030	0	0
T2	14606	440	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	397	0	0
T9	0	52	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	156	0	0
T47	934	0	0	0
T54	0	47	0	0
T55	0	393	0	0
T56	0	334	0	0
T64	0	72186	0	0
T70	0	426	0	0
T73	0	18	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7284	0	0
T1	8369	29	0	0
T2	14606	58	0	0
T3	12699	32	0	0
T4	13206	32	0	0
T5	97815	28	0	0
T6	495	6	0	0
T12	501	5	0	0
T13	691	3	0	0
T14	539	5	0	0
T15	727	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1271637	0	0
T2	14606	92	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	215	0	0
T9	0	165	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	322	0	0
T47	934	0	0	0
T54	0	101	0	0
T55	0	262	0	0
T56	0	115	0	0
T64	0	208	0	0
T70	0	934	0	0
T73	0	150	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T2,T12

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T2,T12
1	1	Covered	T6,T2,T12

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T6,T2,T12
1	1	Covered	T2,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T8,T56,T73
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Unreachable
1	0	Covered	T7,T9,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T8
DetectSt	168	Covered	T2,T7,T8
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T8
DebounceSt->IdleSt	163	Covered	T28,T54,T56
DetectSt->IdleSt	186	Covered	T8,T56,T73
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T2,T7,T8
StableSt->IdleSt	206	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T2,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T54,T56,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T56,T73
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T55
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	175	0	0
CntIncr_A	7939905	603443	0	0
CntNoWrap_A	7939905	7282572	0	0
DetectStDropOut_A	7939905	15	0	0
DetectedOut_A	7939905	728571	0	0
DetectedPulseOut_A	7939905	47	0	0
DisabledIdleSt_A	7939905	5208943	0	0
DisabledNoDetection_A	7939905	5211297	0	0
EnterDebounceSt_A	7939905	113	0	0
EnterDetectSt_A	7939905	62	0	0
EnterStableSt_A	7939905	47	0	0
PulseIsPulse_A	7939905	47	0	0
StayInStableSt	7939905	728524	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_sticky_sva.StableStDropOut_A	7939905	601130	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	175	0	0
T2	14606	2	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	2	0	0
T8	0	6	0	0
T9	0	2	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	2	0	0
T37	0	4	0	0
T47	934	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	13	0	0
T64	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	603443	0	0
T2	14606	22	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	52675	0	0
T8	0	90	0	0
T9	0	43	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	62	0	0
T37	0	208	0	0
T47	934	0	0	0
T54	0	40	0	0
T55	0	32	0	0
T56	0	200	0	0
T64	0	363	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282572	0	0
T1	8369	7958	0	0
T2	14606	4983	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	15	0	0
T8	49691	3	0	0
T9	777	0	0	0
T10	16230	0	0	0
T11	11085	0	0	0
T30	0	1	0	0
T40	21978	0	0	0
T56	0	3	0	0
T60	504	0	0	0
T61	519	0	0	0
T71	0	1	0	0
T73	0	1	0	0
T75	427	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	728571	0	0
T2	14606	98	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	463258	0	0
T9	0	194	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T30	0	65292	0	0
T47	934	0	0	0
T55	0	188	0	0
T64	0	56	0	0
T70	0	1051	0	0
T73	0	158	0	0
T96	0	17	0	0
T97	0	35	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	47	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T30	0	1	0	0
T47	934	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T73	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	5208943	0	0
T1	8369	7958	0	0
T2	14606	4363	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	5211297	0	0
T1	8369	7960	0	0
T2	14606	4386	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	113	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	2	0	0
T37	0	4	0	0
T47	934	0	0	0
T54	0	2	0	0
T55	0	1	0	0
T56	0	10	0	0
T64	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T30	0	2	0	0
T47	934	0	0	0
T55	0	1	0	0
T56	0	3	0	0
T64	0	1	0	0
T70	0	2	0	0
T73	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	47	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T30	0	1	0	0
T47	934	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T73	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	47	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T30	0	1	0	0
T47	934	0	0	0
T55	0	1	0	0
T64	0	1	0	0
T70	0	2	0	0
T73	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	728524	0	0
T2	14606	97	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	463257	0	0
T9	0	193	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T30	0	65291	0	0
T47	934	0	0	0
T55	0	187	0	0
T64	0	55	0	0
T70	0	1049	0	0
T73	0	157	0	0
T96	0	16	0	0
T97	0	34	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	601130	0	0
T2	14606	492	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	297	0	0
T9	0	93	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T30	0	54	0	0
T47	934	0	0	0
T55	0	478	0	0
T64	0	100348	0	0
T70	0	216	0	0
T73	0	188	0	0
T96	0	71	0	0
T97	0	180	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T7,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T2,T7,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T7,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T6,T1,T2
1	1	Covered	T2,T7,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Covered	T64,T70,T71
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T9
0	1	Unreachable
1	0	Covered	T7,T9,T54

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T8
DetectSt	168	Covered	T2,T7,T9
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T7,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T9
DebounceSt->IdleSt	163	Covered	T8,T28,T64
DetectSt->IdleSt	186	Covered	T64,T70,T71
DetectSt->StableSt	191	Covered	T2,T7,T9
IdleSt->DebounceSt	148	Covered	T2,T7,T8
StableSt->IdleSt	206	Covered	T2,T7,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T8
0	1	Covered	T2,T7,T8
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T9
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T64,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T8
DetectSt	-	-	-	-	1	-	-	Covered	T64,T70,T71
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T54
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	181	0	0
CntIncr_A	7939905	333864	0	0
CntNoWrap_A	7939905	7282566	0	0
DetectStDropOut_A	7939905	12	0	0
DetectedOut_A	7939905	206198	0	0
DetectedPulseOut_A	7939905	52	0	0
DisabledIdleSt_A	7939905	5208943	0	0
DisabledNoDetection_A	7939905	5211297	0	0
EnterDebounceSt_A	7939905	117	0	0
EnterDetectSt_A	7939905	64	0	0
EnterStableSt_A	7939905	52	0	0
PulseIsPulse_A	7939905	52	0	0
StayInStableSt	7939905	206146	0	0
gen_high_event_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_sticky_sva.StableStDropOut_A	7939905	1175826	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	181	0	0
T2	14606	2	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	2	0	0
T8	0	3	0	0
T9	0	2	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	2	0	0
T37	0	2	0	0
T47	934	0	0	0
T54	0	2	0	0
T55	0	2	0	0
T56	0	4	0	0
T64	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	333864	0	0
T2	14606	54	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	88	0	0
T8	0	204	0	0
T9	0	28	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	62	0	0
T37	0	56	0	0
T47	934	0	0	0
T54	0	52	0	0
T55	0	84	0	0
T56	0	66	0	0
T64	0	237	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282566	0	0
T1	8369	7958	0	0
T2	14606	4983	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	12	0	0
T46	4921	0	0	0
T64	110834	1	0	0
T70	1908	2	0	0
T71	0	1	0	0
T77	20605	0	0	0
T108	0	2	0	0
T109	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	2	0	0
T113	422	0	0	0
T114	499	0	0	0
T115	427	0	0	0
T116	666	0	0	0
T117	509	0	0	0
T118	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	206198	0	0
T2	14606	436	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	705	0	0
T9	0	197	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	232	0	0
T47	934	0	0	0
T54	0	97	0	0
T55	0	563	0	0
T56	0	359	0	0
T64	0	282	0	0
T70	0	407	0	0
T73	0	299	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	52	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T64	0	1	0	0
T70	0	2	0	0
T73	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	5208943	0	0
T1	8369	7958	0	0
T2	14606	4363	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	5211297	0	0
T1	8369	7960	0	0
T2	14606	4386	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	117	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T8	0	3	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T28	0	2	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T64	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	64	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T64	0	2	0	0
T70	0	4	0	0
T73	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	52	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T64	0	1	0	0
T70	0	2	0	0
T73	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	52	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	1	0	0
T9	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	1	0	0
T47	934	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T64	0	1	0	0
T70	0	2	0	0
T73	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	206146	0	0
T2	14606	435	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	704	0	0
T9	0	196	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	231	0	0
T47	934	0	0	0
T54	0	96	0	0
T55	0	562	0	0
T56	0	357	0	0
T64	0	281	0	0
T70	0	405	0	0
T73	0	297	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1175826	0	0
T2	14606	125	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	515450	0	0
T9	0	121	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T37	0	238	0	0
T47	934	0	0	0
T54	0	56	0	0
T55	0	55	0	0
T56	0	620	0	0
T64	0	102	0	0
T70	0	364	0	0
T73	0	68	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T28,T33,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T28,T33,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T28,T33,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T28
1	0	Covered	T6,T1,T2
1	1	Covered	T28,T33,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T33,T38
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T33,T38
0	1	Covered	T27,T78,T119
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T33,T38
1	-	Covered	T27,T78,T119

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T33,T38
DetectSt	168	Covered	T28,T33,T38
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T28,T33,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T33,T38
DebounceSt->IdleSt	163	Covered	T30,T120,T121
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T28,T33,T38
IdleSt->DebounceSt	148	Covered	T28,T33,T38
StableSt->IdleSt	206	Covered	T28,T33,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T33,T38
0	1	Covered	T28,T33,T38
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T33,T38
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T33,T38
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T33,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T120,T121
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T33,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T28,T33,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T27,T78
StableSt	-	-	-	-	-	-	0	Covered	T28,T33,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	62	0	0
CntIncr_A	7939905	48269	0	0
CntNoWrap_A	7939905	7282685	0	0
DetectStDropOut_A	7939905	0	0	0
DetectedOut_A	7939905	1927	0	0
DetectedPulseOut_A	7939905	29	0	0
DisabledIdleSt_A	7939905	6924175	0	0
DisabledNoDetection_A	7939905	6926481	0	0
EnterDebounceSt_A	7939905	33	0	0
EnterDetectSt_A	7939905	29	0	0
EnterStableSt_A	7939905	29	0	0
PulseIsPulse_A	7939905	29	0	0
StayInStableSt	7939905	1881	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T27	0	4	0	0
T28	8338	2	0	0
T30	0	3	0	0
T32	0	2	0	0
T33	0	2	0	0
T35	15959	0	0	0
T38	0	2	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	2	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	2	0	0
T122	0	2	0	0
T123	0	4	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	48269	0	0
T27	0	64	0	0
T28	8338	28	0	0
T30	0	194	0	0
T32	0	22	0	0
T33	0	14	0	0
T35	15959	0	0	0
T38	0	72	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	96	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	16	0	0
T122	0	13	0	0
T123	0	150	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282685	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1927	0	0
T27	0	147	0	0
T28	8338	17	0	0
T30	0	51	0	0
T32	0	42	0	0
T33	0	41	0	0
T35	15959	0	0	0
T38	0	41	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	71	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	42	0	0
T122	0	39	0	0
T123	0	263	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	29	0	0
T27	0	2	0	0
T28	8338	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	15959	0	0	0
T38	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	1	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6924175	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92392	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6926481	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92405	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	33	0	0
T27	0	2	0	0
T28	8338	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	15959	0	0	0
T38	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	1	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	29	0	0
T27	0	2	0	0
T28	8338	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	15959	0	0	0
T38	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	1	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	29	0	0
T27	0	2	0	0
T28	8338	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	15959	0	0	0
T38	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	1	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	29	0	0
T27	0	2	0	0
T28	8338	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	15959	0	0	0
T38	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	1	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T123	0	2	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1881	0	0
T27	0	144	0	0
T28	8338	16	0	0
T30	0	49	0	0
T32	0	40	0	0
T33	0	39	0	0
T35	15959	0	0	0
T38	0	39	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T78	0	70	0	0
T92	738	0	0	0
T93	10267	0	0	0
T119	0	41	0	0
T122	0	37	0	0
T123	0	260	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	11	0	0
T27	35167	1	0	0
T36	1197	0	0	0
T45	5318	0	0	0
T76	7184	0	0	0
T78	0	1	0	0
T100	0	1	0	0
T119	0	1	0	0
T123	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0
T129	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	21229	0	0	0
T133	406	0	0	0
T134	403	0	0	0
T135	431	0	0	0
T136	424	0	0	0
T137	490	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T5,T10,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T10,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T129,T138
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T10,T38,T36
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T10,T28
1	-	Covered	T10,T38,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T10,T28
DetectSt	168	Covered	T5,T10,T28
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T5,T10,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T10,T28
DebounceSt->IdleSt	163	Covered	T10,T139,T65
DetectSt->IdleSt	186	Covered	T129,T138
DetectSt->StableSt	191	Covered	T5,T10,T28
IdleSt->DebounceSt	148	Covered	T5,T10,T28
StableSt->IdleSt	206	Covered	T5,T10,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T10,T28
0	1	Covered	T5,T10,T28
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T28
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T10,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T10,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T139
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	1	-	-	Covered	T129,T138
DetectSt	-	-	-	-	0	1	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T28,T38
StableSt	-	-	-	-	-	-	0	Covered	T5,T10,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	121	0	0
CntIncr_A	7939905	92586	0	0
CntNoWrap_A	7939905	7282626	0	0
DetectStDropOut_A	7939905	2	0	0
DetectedOut_A	7939905	29252	0	0
DetectedPulseOut_A	7939905	57	0	0
DisabledIdleSt_A	7939905	7061801	0	0
DisabledNoDetection_A	7939905	7064103	0	0
EnterDebounceSt_A	7939905	62	0	0
EnterDetectSt_A	7939905	59	0	0
EnterStableSt_A	7939905	57	0	0
PulseIsPulse_A	7939905	57	0	0
StayInStableSt	7939905	29170	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	2711	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	121	0	0
T5	97815	4	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	3	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	2	0	0
T30	0	4	0	0
T32	0	2	0	0
T35	0	2	0	0
T36	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	92586	0	0
T5	97815	109	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	131	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	28	0	0
T30	0	194	0	0
T32	0	22	0	0
T35	0	3374	0	0
T36	0	196	0	0
T38	0	72	0	0
T39	0	35	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	192	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282626	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92546	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2	0	0
T129	703	1	0	0
T138	0	1	0	0
T140	30222	0	0	0
T141	858	0	0	0
T142	522	0	0	0
T143	4402	0	0	0
T144	491	0	0	0
T145	695	0	0	0
T146	3421	0	0	0
T147	504	0	0	0
T148	405	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	29252	0	0
T5	97815	100	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	59	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	18	0	0
T30	0	184	0	0
T32	0	7	0	0
T35	0	7084	0	0
T36	0	297	0	0
T38	0	56	0	0
T39	0	37	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	79	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	57	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7061801	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92203	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7064103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92215	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	59	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	57	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	57	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	29170	0	0
T5	97815	96	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	58	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	17	0	0
T30	0	182	0	0
T32	0	6	0	0
T35	0	7082	0	0
T36	0	294	0	0
T38	0	55	0	0
T39	0	35	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	76	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2711	0	0
T1	8369	0	0	0
T2	14606	50	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	15	0	0
T6	495	4	0	0
T8	0	44	0	0
T12	501	4	0	0
T13	691	0	0	0
T14	539	6	0	0
T15	727	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	6	0	0
T75	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	31	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T30	0	2	0	0
T32	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T72	0	1	0	0
T78	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T119	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0