Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T28,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T28,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T28,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T28,T37
0	1	Covered	T10,T27,T123
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T28,T37
1	-	Covered	T10,T27,T123

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T33
DetectSt	168	Covered	T10,T28,T37
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T28,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T28,T37
DebounceSt->IdleSt	163	Covered	T33,T151,T65
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T10,T28,T37
IdleSt->DebounceSt	148	Covered	T10,T28,T33
StableSt->IdleSt	206	Covered	T10,T28,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T28,T33
0	1	Covered	T10,T28,T33
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T28,T37
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T33
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T28,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T151
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T10,T28,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T28,T27
StableSt	-	-	-	-	-	-	0	Covered	T10,T28,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	53	0	0
CntIncr_A	7939905	1455	0	0
CntNoWrap_A	7939905	7282694	0	0
DetectStDropOut_A	7939905	0	0	0
DetectedOut_A	7939905	2425	0	0
DetectedPulseOut_A	7939905	25	0	0
DisabledIdleSt_A	7939905	6965659	0	0
DisabledNoDetection_A	7939905	6967960	0	0
EnterDebounceSt_A	7939905	28	0	0
EnterDetectSt_A	7939905	25	0	0
EnterStableSt_A	7939905	25	0	0
PulseIsPulse_A	7939905	25	0	0
StayInStableSt	7939905	2390	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	53	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	4	0	0
T28	0	2	0	0
T33	0	1	0	0
T37	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	2	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	2	0	0
T149	0	2	0	0
T152	0	2	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1455	0	0
T10	16230	84	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	64	0	0
T28	0	28	0	0
T33	0	14	0	0
T37	0	53	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	54	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	75	0	0
T149	0	74	0	0
T152	0	64	0	0
T153	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282694	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2425	0	0
T10	16230	175	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	106	0	0
T28	0	19	0	0
T37	0	42	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	39	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	230	0	0
T149	0	263	0	0
T151	0	252	0	0
T152	0	40	0	0
T153	0	154	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	25	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6965659	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92203	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6967960	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92215	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	28	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T33	0	1	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	1	0	0
T149	0	1	0	0
T152	0	1	0	0
T153	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	25	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	25	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	25	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	1	0	0
T149	0	1	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2390	0	0
T10	16230	174	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	104	0	0
T28	0	18	0	0
T37	0	40	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T79	0	37	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	229	0	0
T149	0	261	0	0
T151	0	250	0	0
T152	0	38	0	0
T153	0	153	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	14	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T110	0	1	0	0
T121	0	2	0	0
T123	0	1	0	0
T141	0	1	0	0
T151	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T5,T10,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T10,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T39,T150,T156
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T10,T27,T36
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T10,T28
1	-	Covered	T10,T27,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T10,T28
DetectSt	168	Covered	T5,T10,T28
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T5,T10,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T10,T28
DebounceSt->IdleSt	163	Covered	T79,T121,T129
DetectSt->IdleSt	186	Covered	T39,T150,T156
DetectSt->StableSt	191	Covered	T5,T10,T28
IdleSt->DebounceSt	148	Covered	T5,T10,T28
StableSt->IdleSt	206	Covered	T5,T10,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T10,T28
0	1	Covered	T5,T10,T28
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T28
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T10,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T10,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T121,T129,T138
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	1	-	-	Covered	T39,T150,T156
DetectSt	-	-	-	-	0	1	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T28,T27
StableSt	-	-	-	-	-	-	0	Covered	T5,T10,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	133	0	0
CntIncr_A	7939905	95962	0	0
CntNoWrap_A	7939905	7282614	0	0
DetectStDropOut_A	7939905	3	0	0
DetectedOut_A	7939905	66765	0	0
DetectedPulseOut_A	7939905	61	0	0
DisabledIdleSt_A	7939905	7011046	0	0
DisabledNoDetection_A	7939905	7013343	0	0
EnterDebounceSt_A	7939905	70	0	0
EnterDetectSt_A	7939905	64	0	0
EnterStableSt_A	7939905	61	0	0
PulseIsPulse_A	7939905	61	0	0
StayInStableSt	7939905	66665	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	3034	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	133	0	0
T5	97815	4	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	4	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	6	0	0
T28	0	2	0	0
T29	0	2	0	0
T30	0	4	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	4	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	95962	0	0
T5	97815	109	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	168	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	96	0	0
T28	0	28	0	0
T29	0	47	0	0
T30	0	194	0	0
T36	0	98	0	0
T38	0	72	0	0
T39	0	135	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	26	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282614	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92546	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	3	0	0
T39	12872	1	0	0
T150	0	1	0	0
T156	0	1	0	0
T157	430	0	0	0
T158	407	0	0	0
T159	404	0	0	0
T160	14764	0	0	0
T161	425	0	0	0
T162	227819	0	0	0
T163	440	0	0	0
T164	1502	0	0	0
T165	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	66765	0	0
T5	97815	178	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	381	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	108	0	0
T28	0	19	0	0
T29	0	256	0	0
T30	0	96	0	0
T36	0	550	0	0
T38	0	41	0	0
T39	0	41	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	51	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	61	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7011046	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92203	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7013343	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92215	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	70	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	64	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	61	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	61	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	66665	0	0
T5	97815	174	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	378	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	104	0	0
T28	0	18	0	0
T29	0	254	0	0
T30	0	93	0	0
T36	0	549	0	0
T38	0	39	0	0
T39	0	39	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T122	0	48	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	3034	0	0
T1	8369	0	0	0
T2	14606	52	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	26	0	0
T6	495	6	0	0
T8	0	60	0	0
T12	501	5	0	0
T13	691	0	0	0
T14	539	5	0	0
T15	727	0	0	0
T47	0	4	0	0
T49	0	1	0	0
T50	0	4	0	0
T51	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	21	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T30	0	1	0	0
T36	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	0	1	0	0
T127	0	1	0	0
T150	0	1	0	0
T153	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T5,T10,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T10,T28
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T10,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T33,T36,T120
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T37,T27,T36
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T10,T28
1	-	Covered	T37,T27,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T10,T28
DetectSt	168	Covered	T5,T10,T28
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T5,T10,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T10,T28
DebounceSt->IdleSt	163	Covered	T33,T79,T152
DetectSt->IdleSt	186	Covered	T33,T36,T120
DetectSt->StableSt	191	Covered	T5,T10,T28
IdleSt->DebounceSt	148	Covered	T5,T10,T28
StableSt->IdleSt	206	Covered	T5,T10,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T10,T28
0	1	Covered	T5,T10,T28
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T28
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T10,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T10,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T152,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	1	-	-	Covered	T33,T36,T120
DetectSt	-	-	-	-	0	1	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T37,T27
StableSt	-	-	-	-	-	-	0	Covered	T5,T10,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	125	0	0
CntIncr_A	7939905	112407	0	0
CntNoWrap_A	7939905	7282622	0	0
DetectStDropOut_A	7939905	4	0	0
DetectedOut_A	7939905	7775	0	0
DetectedPulseOut_A	7939905	55	0	0
DisabledIdleSt_A	7939905	6932541	0	0
DisabledNoDetection_A	7939905	6934842	0	0
EnterDebounceSt_A	7939905	67	0	0
EnterDetectSt_A	7939905	59	0	0
EnterStableSt_A	7939905	55	0	0
PulseIsPulse_A	7939905	55	0	0
StayInStableSt	7939905	7690	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	125	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	6	0	0
T28	0	2	0	0
T29	0	2	0	0
T32	0	2	0	0
T33	0	3	0	0
T35	0	2	0	0
T36	0	6	0	0
T37	0	2	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	112407	0	0
T5	97815	50	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	47	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	96	0	0
T28	0	28	0	0
T29	0	47	0	0
T32	0	22	0	0
T33	0	28	0	0
T35	0	3374	0	0
T36	0	294	0	0
T37	0	53	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282622	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92548	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	4	0	0
T25	42788	0	0	0
T33	12098	1	0	0
T36	0	1	0	0
T38	651	0	0	0
T56	1512	0	0	0
T95	32440	0	0	0
T120	0	1	0	0
T156	0	1	0	0
T167	526	0	0	0
T168	503	0	0	0
T169	2088	0	0	0
T170	521	0	0	0
T171	445	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7775	0	0
T5	97815	54	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	54	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	184	0	0
T28	0	18	0	0
T29	0	12	0	0
T32	0	72	0	0
T35	0	3669	0	0
T36	0	208	0	0
T37	0	44	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T172	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	55	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6932541	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92203	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6934842	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92215	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	67	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	59	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	55	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	55	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	1	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	3	0	0
T28	0	1	0	0
T29	0	1	0	0
T32	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7690	0	0
T5	97815	52	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	52	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T27	0	180	0	0
T28	0	17	0	0
T29	0	11	0	0
T32	0	70	0	0
T35	0	3667	0	0
T36	0	205	0	0
T37	0	43	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T172	0	85	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	24	0	0
T27	35167	2	0	0
T29	0	1	0	0
T36	0	1	0	0
T37	15214	1	0	0
T45	5318	0	0	0
T78	0	1	0	0
T119	0	1	0	0
T132	21229	0	0	0
T149	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	39681	0	0	0
T176	919	0	0	0
T177	426	0	0	0
T178	414	0	0	0
T179	422	0	0	0
T180	404	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T31,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T31,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T28
0	1	Covered	T154
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T28
0	1	Covered	T10,T31,T27
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T31,T28
1	-	Covered	T10,T31,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T31,T28
DetectSt	168	Covered	T10,T31,T28
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T31,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T31,T28
DebounceSt->IdleSt	163	Covered	T173,T65,T181
DetectSt->IdleSt	186	Covered	T154
DetectSt->StableSt	191	Covered	T10,T31,T28
IdleSt->DebounceSt	148	Covered	T10,T31,T28
StableSt->IdleSt	206	Covered	T10,T31,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T31,T28
0	1	Covered	T10,T31,T28
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T31,T28
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T31,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T31,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T173
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T31,T28
DetectSt	-	-	-	-	1	-	-	Covered	T154
DetectSt	-	-	-	-	0	1	-	Covered	T10,T31,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T31,T28
StableSt	-	-	-	-	-	-	0	Covered	T10,T31,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	84	0	0
CntIncr_A	7939905	5147	0	0
CntNoWrap_A	7939905	7282663	0	0
DetectStDropOut_A	7939905	1	0	0
DetectedOut_A	7939905	2659	0	0
DetectedPulseOut_A	7939905	40	0	0
DisabledIdleSt_A	7939905	7181930	0	0
DisabledNoDetection_A	7939905	7184234	0	0
EnterDebounceSt_A	7939905	44	0	0
EnterDetectSt_A	7939905	41	0	0
EnterStableSt_A	7939905	40	0	0
PulseIsPulse_A	7939905	40	0	0
StayInStableSt	7939905	2601	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	6926	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	84	0	0
T10	16230	4	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	4	0	0
T28	0	2	0	0
T29	0	2	0	0
T31	0	4	0	0
T36	0	4	0	0
T37	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	2	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	4	0	0
T173	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	5147	0	0
T10	16230	168	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	64	0	0
T28	0	28	0	0
T29	0	47	0	0
T31	0	160	0	0
T36	0	196	0	0
T37	0	53	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	96	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	22	0	0
T173	0	51	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282663	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1	0	0
T154	3230	1	0	0
T156	92006	0	0	0
T182	644	0	0	0
T183	502	0	0	0
T184	7633	0	0	0
T185	434	0	0	0
T186	527	0	0	0
T187	18745	0	0	0
T188	22420	0	0	0
T189	432	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2659	0	0
T10	16230	244	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	30	0	0
T28	0	18	0	0
T29	0	43	0	0
T31	0	85	0	0
T36	0	86	0	0
T37	0	117	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	39	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	83	0	0
T174	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	40	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	2	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7181930	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92361	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7184234	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92374	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	44	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	2	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	41	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	2	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	40	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	2	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	40	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	2	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2601	0	0
T10	16230	241	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	28	0	0
T28	0	17	0	0
T29	0	41	0	0
T31	0	82	0	0
T36	0	84	0	0
T37	0	115	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	37	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	81	0	0
T174	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6926	0	0
T1	8369	25	0	0
T2	14606	52	0	0
T3	12699	31	0	0
T4	13206	31	0	0
T5	97815	13	0	0
T6	495	8	0	0
T7	0	5	0	0
T12	501	4	0	0
T13	691	0	0	0
T14	539	4	0	0
T15	727	0	0	0
T19	0	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	21	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T31	0	1	0	0
T36	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T123	0	2	0	0
T150	0	2	0	0
T152	0	1	0	0
T154	0	1	0	0
T174	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T28,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T38
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T28,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T28,T37
0	1	Covered	T191,T192,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T28,T37
0	1	Covered	T10,T37,T27
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T28,T37
1	-	Covered	T10,T37,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T37
DetectSt	168	Covered	T10,T28,T37
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T28,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T28,T37
DebounceSt->IdleSt	163	Covered	T10,T65
DetectSt->IdleSt	186	Covered	T191,T192,T84
DetectSt->StableSt	191	Covered	T10,T28,T37
IdleSt->DebounceSt	148	Covered	T10,T28,T37
StableSt->IdleSt	206	Covered	T10,T28,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T28,T37
0	1	Covered	T10,T28,T37
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T28,T37
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T37
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T28,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T10
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T37
DetectSt	-	-	-	-	1	-	-	Covered	T191,T192,T84
DetectSt	-	-	-	-	0	1	-	Covered	T10,T28,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T28,T37
StableSt	-	-	-	-	-	-	0	Covered	T10,T28,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	126	0	0
CntIncr_A	7939905	120677	0	0
CntNoWrap_A	7939905	7282621	0	0
DetectStDropOut_A	7939905	4	0	0
DetectedOut_A	7939905	73692	0	0
DetectedPulseOut_A	7939905	58	0	0
DisabledIdleSt_A	7939905	6926759	0	0
DisabledNoDetection_A	7939905	6929063	0	0
EnterDebounceSt_A	7939905	64	0	0
EnterDetectSt_A	7939905	62	0	0
EnterStableSt_A	7939905	58	0	0
PulseIsPulse_A	7939905	58	0	0
StayInStableSt	7939905	73610	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	126	0	0
T10	16230	3	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	4	0	0
T28	0	2	0	0
T30	0	2	0	0
T32	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T39	0	4	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	4	0	0
T172	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	120677	0	0
T10	16230	131	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	64	0	0
T28	0	28	0	0
T30	0	97	0	0
T32	0	22	0	0
T34	0	19	0	0
T37	0	106	0	0
T39	0	135	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	26	0	0
T172	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282621	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	4	0	0
T84	0	1	0	0
T119	568	0	0	0
T191	34155	1	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	18179	0	0	0
T195	27902	0	0	0
T196	35206	0	0	0
T197	524	0	0	0
T198	506	0	0	0
T199	9226	0	0	0
T200	451	0	0	0
T201	1427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	73692	0	0
T10	16230	59	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	96	0	0
T28	0	18	0	0
T30	0	213	0	0
T32	0	73	0	0
T34	0	54	0	0
T37	0	140	0	0
T39	0	79	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	62	0	0
T172	0	64	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	58	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	2	0	0
T172	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6926759	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6929063	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	64	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	2	0	0
T172	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	2	0	0
T172	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	58	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	2	0	0
T172	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	58	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	2	0	0
T172	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	73610	0	0
T10	16230	58	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	94	0	0
T28	0	17	0	0
T30	0	212	0	0
T32	0	71	0	0
T34	0	52	0	0
T37	0	137	0	0
T39	0	75	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	59	0	0
T172	0	61	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	33	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T30	0	1	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T119	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T172	0	1	0	0
T190	0	1	0	0
T202	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T5,T10,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T6,T1,T2
1	1	Covered	T5,T10,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T121,T141
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T10,T28
0	1	Covered	T35,T36,T122
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T10,T28
1	-	Covered	T35,T36,T122

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T10,T28
DetectSt	168	Covered	T5,T10,T28
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T5,T10,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T10,T28
DebounceSt->IdleSt	163	Covered	T119,T152,T120
DetectSt->IdleSt	186	Covered	T121,T141
DetectSt->StableSt	191	Covered	T5,T10,T28
IdleSt->DebounceSt	148	Covered	T5,T10,T28
StableSt->IdleSt	206	Covered	T5,T10,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T10,T28
0	1	Covered	T5,T10,T28
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T10,T28
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T10,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T10,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T119,T152,T120
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	1	-	-	Covered	T121,T141
DetectSt	-	-	-	-	0	1	-	Covered	T5,T10,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T5,T10,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	100	0	0
CntIncr_A	7939905	58763	0	0
CntNoWrap_A	7939905	7282647	0	0
DetectStDropOut_A	7939905	2	0	0
DetectedOut_A	7939905	3347	0	0
DetectedPulseOut_A	7939905	46	0	0
DisabledIdleSt_A	7939905	6905326	0	0
DisabledNoDetection_A	7939905	6907617	0	0
EnterDebounceSt_A	7939905	53	0	0
EnterDetectSt_A	7939905	48	0	0
EnterStableSt_A	7939905	46	0	0
PulseIsPulse_A	7939905	46	0	0
StayInStableSt	7939905	3274	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	6546	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	100	0	0
T5	97815	2	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	4	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	2	0	0
T30	0	2	0	0
T35	0	4	0	0
T36	0	2	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	2	0	0
T122	0	2	0	0
T149	0	2	0	0
T150	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	58763	0	0
T5	97815	50	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	131	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	28	0	0
T30	0	97	0	0
T35	0	6748	0	0
T36	0	98	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	96	0	0
T122	0	13	0	0
T149	0	74	0	0
T150	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282647	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92548	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2	0	0
T121	7490	1	0	0
T141	0	1	0	0
T203	689	0	0	0
T204	5900	0	0	0
T205	31611	0	0	0
T206	510	0	0	0
T207	2747	0	0	0
T208	429	0	0	0
T209	506	0	0	0
T210	7811	0	0	0
T211	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	3347	0	0
T5	97815	54	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	624	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	17	0	0
T30	0	149	0	0
T35	0	93	0	0
T36	0	310	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	207	0	0
T122	0	39	0	0
T149	0	38	0	0
T150	0	82	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	46	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6905326	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92203	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6907617	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92215	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	53	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	48	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	46	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	46	0	0
T5	97815	1	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	2	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	1	0	0
T30	0	1	0	0
T35	0	2	0	0
T36	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	1	0	0
T122	0	1	0	0
T149	0	1	0	0
T150	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	3274	0	0
T5	97815	52	0	0
T7	516679	0	0	0
T8	49691	0	0	0
T10	0	620	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T28	0	16	0	0
T30	0	147	0	0
T35	0	90	0	0
T36	0	309	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T78	0	205	0	0
T122	0	38	0	0
T149	0	36	0	0
T150	0	79	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6546	0	0
T1	8369	28	0	0
T2	14606	50	0	0
T3	12699	25	0	0
T4	13206	24	0	0
T5	97815	13	0	0
T6	495	7	0	0
T12	501	4	0	0
T13	691	0	0	0
T14	539	7	0	0
T15	727	0	0	0
T19	0	15	0	0
T49	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	18	0	0
T35	15959	1	0	0
T36	0	1	0	0
T43	5320	0	0	0
T54	947	0	0	0
T58	493	0	0	0
T59	493	0	0	0
T72	0	1	0	0
T84	0	1	0	0
T122	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T190	0	1	0	0
T212	687	0	0	0
T213	424	0	0	0
T214	402	0	0	0
T215	525	0	0	0
T216	402	0	0	0