Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T8,T10,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T6,T1,T2
1	1	Covered	T8,T10,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T28
0	1	Covered	T217,T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T28
0	1	Covered	T10,T31,T35
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T31,T28
1	-	Covered	T10,T31,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T10,T31
DetectSt	168	Covered	T10,T31,T28
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T31,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T31,T28
DebounceSt->IdleSt	163	Covered	T8,T217,T65
DetectSt->IdleSt	186	Covered	T217,T100
DetectSt->StableSt	191	Covered	T10,T31,T28
IdleSt->DebounceSt	148	Covered	T8,T10,T31
StableSt->IdleSt	206	Covered	T10,T31,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T31,T28
0	1	Covered	T8,T10,T31
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T31,T28
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T10,T31
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T31,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T217
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T10,T31
DetectSt	-	-	-	-	1	-	-	Covered	T217,T100
DetectSt	-	-	-	-	0	1	-	Covered	T10,T31,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T31,T28
StableSt	-	-	-	-	-	-	0	Covered	T10,T31,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	126	0	0
CntIncr_A	7939905	76273	0	0
CntNoWrap_A	7939905	7282621	0	0
DetectStDropOut_A	7939905	2	0	0
DetectedOut_A	7939905	68162	0	0
DetectedPulseOut_A	7939905	60	0	0
DisabledIdleSt_A	7939905	7102669	0	0
DisabledNoDetection_A	7939905	7104972	0	0
EnterDebounceSt_A	7939905	65	0	0
EnterDetectSt_A	7939905	62	0	0
EnterStableSt_A	7939905	60	0	0
PulseIsPulse_A	7939905	60	0	0
StayInStableSt	7939905	68078	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	35	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	126	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T29	0	2	0	0
T31	0	4	0	0
T33	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	76273	0	0
T8	49691	6289	0	0
T9	777	0	0	0
T10	16230	84	0	0
T11	11085	0	0	0
T27	0	32	0	0
T28	0	28	0	0
T31	0	160	0	0
T33	0	14	0	0
T35	0	3374	0	0
T36	0	98	0	0
T37	0	53	0	0
T38	0	72	0	0
T40	21978	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T75	427	0	0	0
T88	404	0	0	0
T89	412	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282621	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2	0	0
T100	0	1	0	0
T217	23681	1	0	0
T218	499	0	0	0
T219	495	0	0	0
T220	506	0	0	0
T221	46100	0	0	0
T222	428	0	0	0
T223	14792	0	0	0
T224	36177	0	0	0
T225	528	0	0	0
T226	861	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	68162	0	0
T10	16230	173	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	212	0	0
T28	0	19	0	0
T29	0	193	0	0
T31	0	181	0	0
T33	0	105	0	0
T35	0	1717	0	0
T36	0	15	0	0
T37	0	20	0	0
T38	0	42	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	60	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7102669	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92361	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7104972	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92374	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	65	0	0
T8	49691	1	0	0
T9	777	0	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	21978	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T75	427	0	0	0
T88	404	0	0	0
T89	412	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	60	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	60	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T31	0	2	0	0
T33	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	68078	0	0
T10	16230	172	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	211	0	0
T28	0	18	0	0
T29	0	191	0	0
T31	0	179	0	0
T33	0	103	0	0
T35	0	1716	0	0
T36	0	14	0	0
T37	0	19	0	0
T38	0	40	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	35	0	0
T10	16230	1	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	1	0	0
T30	0	1	0	0
T31	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T78	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T150	0	1	0	0
T172	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T28,T35,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T28,T35,T27

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T28,T35,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T8,T10
1	0	Covered	T6,T1,T2
1	1	Covered	T28,T35,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T35,T27
0	1	Covered	T100
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T35,T27
0	1	Covered	T172,T149,T217
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T35,T27
1	-	Covered	T172,T149,T217

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T35,T27
DetectSt	168	Covered	T28,T35,T27
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T28,T35,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T35,T27
DebounceSt->IdleSt	163	Covered	T65
DetectSt->IdleSt	186	Covered	T100
DetectSt->StableSt	191	Covered	T28,T35,T27
IdleSt->DebounceSt	148	Covered	T28,T35,T27
StableSt->IdleSt	206	Covered	T28,T27,T172

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T35,T27
0	1	Covered	T28,T35,T27
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T35,T27
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T35,T27
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T35,T27
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T35,T27
DetectSt	-	-	-	-	1	-	-	Covered	T100
DetectSt	-	-	-	-	0	1	-	Covered	T28,T35,T27
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T172,T149
StableSt	-	-	-	-	-	-	0	Covered	T28,T35,T27
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	67	0	0
CntIncr_A	7939905	65357	0	0
CntNoWrap_A	7939905	7282680	0	0
DetectStDropOut_A	7939905	1	0	0
DetectedOut_A	7939905	9182	0	0
DetectedPulseOut_A	7939905	32	0	0
DisabledIdleSt_A	7939905	7126275	0	0
DisabledNoDetection_A	7939905	7128583	0	0
EnterDebounceSt_A	7939905	34	0	0
EnterDetectSt_A	7939905	33	0	0
EnterStableSt_A	7939905	32	0	0
PulseIsPulse_A	7939905	32	0	0
StayInStableSt	7939905	9131	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	6594	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	67	0	0
T27	0	2	0	0
T28	8338	2	0	0
T35	15959	2	0	0
T36	0	2	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	4	0	0
T172	0	2	0	0
T192	0	2	0	0
T202	0	2	0	0
T217	0	4	0	0
T227	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	65357	0	0
T27	0	32	0	0
T28	8338	28	0	0
T35	15959	3374	0	0
T36	0	98	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	148	0	0
T172	0	16	0	0
T192	0	23	0	0
T202	0	60	0	0
T217	0	164	0	0
T227	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282680	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1	0	0
T100	28055	1	0	0
T151	266890	0	0	0
T228	494	0	0	0
T229	407	0	0	0
T230	5416	0	0	0
T231	679	0	0	0
T232	523	0	0	0
T233	636	0	0	0
T234	4441	0	0	0
T235	1660	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	9182	0	0
T27	0	53	0	0
T28	8338	17	0	0
T35	15959	7084	0	0
T36	0	334	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	150	0	0
T172	0	10	0	0
T192	0	39	0	0
T202	0	42	0	0
T217	0	81	0	0
T227	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	32	0	0
T27	0	1	0	0
T28	8338	1	0	0
T35	15959	1	0	0
T36	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	2	0	0
T172	0	1	0	0
T192	0	1	0	0
T202	0	1	0	0
T217	0	2	0	0
T227	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7126275	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92361	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7128583	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92374	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	34	0	0
T27	0	1	0	0
T28	8338	1	0	0
T35	15959	1	0	0
T36	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	2	0	0
T172	0	1	0	0
T192	0	1	0	0
T202	0	1	0	0
T217	0	2	0	0
T227	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	33	0	0
T27	0	1	0	0
T28	8338	1	0	0
T35	15959	1	0	0
T36	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	2	0	0
T172	0	1	0	0
T192	0	1	0	0
T202	0	1	0	0
T217	0	2	0	0
T227	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	32	0	0
T27	0	1	0	0
T28	8338	1	0	0
T35	15959	1	0	0
T36	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	2	0	0
T172	0	1	0	0
T192	0	1	0	0
T202	0	1	0	0
T217	0	2	0	0
T227	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	32	0	0
T27	0	1	0	0
T28	8338	1	0	0
T35	15959	1	0	0
T36	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	2	0	0
T172	0	1	0	0
T192	0	1	0	0
T202	0	1	0	0
T217	0	2	0	0
T227	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	9131	0	0
T27	0	51	0	0
T28	8338	16	0	0
T35	15959	7082	0	0
T36	0	332	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	147	0	0
T172	0	9	0	0
T192	0	37	0	0
T202	0	40	0	0
T217	0	79	0	0
T227	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6594	0	0
T1	8369	29	0	0
T2	14606	46	0	0
T3	12699	28	0	0
T4	13206	25	0	0
T5	97815	16	0	0
T6	495	7	0	0
T12	501	5	0	0
T13	691	0	0	0
T14	539	2	0	0
T15	727	0	0	0
T19	0	13	0	0
T49	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	12	0	0
T96	1633	0	0	0
T121	0	2	0	0
T149	0	1	0	0
T172	590	1	0	0
T217	0	2	0	0
T236	0	2	0	0
T237	0	1	0	0
T238	0	2	0	0
T239	0	1	0	0
T240	18240	0	0	0
T241	527	0	0	0
T242	20648	0	0	0
T243	522	0	0	0
T244	18606	0	0	0
T245	495	0	0	0
T246	12832	0	0	0
T247	905	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T28,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T28,T38
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T28,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T28,T38
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T28,T38
0	1	Covered	T10,T190,T166
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T28,T38
1	-	Covered	T10,T190,T166

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T28,T38
DetectSt	168	Covered	T10,T28,T38
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T28,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T28,T38
DebounceSt->IdleSt	163	Covered	T34,T65,T238
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T10,T28,T38
IdleSt->DebounceSt	148	Covered	T10,T28,T38
StableSt->IdleSt	206	Covered	T10,T28,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T28,T38
0	1	Covered	T10,T28,T38
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T28,T38
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T28,T38
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T28,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T28,T38
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T10,T28,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T28,T190
StableSt	-	-	-	-	-	-	0	Covered	T10,T28,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	101	0	0
CntIncr_A	7939905	112068	0	0
CntNoWrap_A	7939905	7282646	0	0
DetectStDropOut_A	7939905	1	0	0
DetectedOut_A	7939905	112046	0	0
DetectedPulseOut_A	7939905	48	0	0
DisabledIdleSt_A	7939905	7036649	0	0
DisabledNoDetection_A	7939905	7038964	0	0
EnterDebounceSt_A	7939905	52	0	0
EnterDetectSt_A	7939905	49	0	0
EnterStableSt_A	7939905	48	0	0
PulseIsPulse_A	7939905	48	0	0
StayInStableSt	7939905	111974	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	101	0	0
T10	16230	6	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T84	0	2	0	0
T88	404	0	0	0
T89	412	0	0	0
T127	0	4	0	0
T166	0	2	0	0
T190	0	2	0	0
T191	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	112068	0	0
T10	16230	252	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	28	0	0
T34	0	19	0	0
T38	0	72	0	0
T39	0	135	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T84	0	76	0	0
T88	404	0	0	0
T89	412	0	0	0
T127	0	134	0	0
T166	0	93	0	0
T190	0	15	0	0
T191	0	16853	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282646	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1	0	0
T84	36853	1	0	0
T248	506	0	0	0
T249	4821	0	0	0
T250	409	0	0	0
T251	496	0	0	0
T252	422	0	0	0
T253	15379	0	0	0
T254	21773	0	0	0
T255	509	0	0	0
T256	495	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	112046	0	0
T10	16230	303	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	18	0	0
T38	0	42	0	0
T39	0	257	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T100	0	475	0	0
T127	0	373	0	0
T153	0	147	0	0
T166	0	1	0	0
T190	0	86	0	0
T191	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	48	0	0
T10	16230	3	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T100	0	1	0	0
T127	0	2	0	0
T153	0	3	0	0
T166	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7036649	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7038964	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	52	0	0
T10	16230	3	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T84	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T127	0	2	0	0
T166	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	49	0	0
T10	16230	3	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T84	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T127	0	2	0	0
T153	0	3	0	0
T166	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	48	0	0
T10	16230	3	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T100	0	1	0	0
T127	0	2	0	0
T153	0	3	0	0
T166	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	48	0	0
T10	16230	3	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	1	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T100	0	1	0	0
T127	0	2	0	0
T153	0	3	0	0
T166	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	111974	0	0
T10	16230	299	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T28	0	17	0	0
T38	0	40	0	0
T39	0	253	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T100	0	474	0	0
T127	0	370	0	0
T151	0	650	0	0
T153	0	143	0	0
T190	0	85	0	0
T191	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	23	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T100	0	1	0	0
T127	0	1	0	0
T151	0	2	0	0
T153	0	2	0	0
T154	0	1	0	0
T166	0	1	0	0
T190	0	1	0	0
T257	0	1	0	0
T258	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T31,T28,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T31,T28,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T31,T28,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T31,T28,T35
1	0	Covered	T6,T1,T2
1	1	Covered	T31,T28,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T31,T28,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T31,T28,T33
0	1	Covered	T31,T84,T238
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T31,T28,T33
1	-	Covered	T31,T84,T238

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T31,T28,T33
DetectSt	168	Covered	T31,T28,T33
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T31,T28,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T31,T28,T33
DebounceSt->IdleSt	163	Covered	T150,T141,T65
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T31,T28,T33
IdleSt->DebounceSt	148	Covered	T31,T28,T33
StableSt->IdleSt	206	Covered	T31,T28,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T31,T28,T33
0	1	Covered	T31,T28,T33
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T31,T28,T33
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T31,T28,T33
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T31,T28,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T150,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T31,T28,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T31,T28,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T31,T28,T84
StableSt	-	-	-	-	-	-	0	Covered	T31,T28,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	47	0	0
CntIncr_A	7939905	1174	0	0
CntNoWrap_A	7939905	7282700	0	0
DetectStDropOut_A	7939905	0	0	0
DetectedOut_A	7939905	1153	0	0
DetectedPulseOut_A	7939905	22	0	0
DisabledIdleSt_A	7939905	6948646	0	0
DisabledNoDetection_A	7939905	6950963	0	0
EnterDebounceSt_A	7939905	25	0	0
EnterDetectSt_A	7939905	22	0	0
EnterStableSt_A	7939905	22	0	0
PulseIsPulse_A	7939905	22	0	0
StayInStableSt	7939905	1114	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	6550	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	4	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	47	0	0
T28	8338	2	0	0
T31	1135	4	0	0
T32	0	2	0	0
T33	0	2	0	0
T34	0	2	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	2	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	2	0	0
T150	0	1	0	0
T190	0	2	0	0
T227	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1174	0	0
T28	8338	28	0	0
T31	1135	160	0	0
T32	0	22	0	0
T33	0	14	0	0
T34	0	19	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	75	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	74	0	0
T150	0	11	0	0
T190	0	15	0	0
T227	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282700	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1153	0	0
T28	8338	19	0	0
T31	1135	181	0	0
T32	0	42	0	0
T33	0	105	0	0
T34	0	39	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T84	0	76	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	41	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	38	0	0
T190	0	40	0	0
T227	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	22	0	0
T28	8338	1	0	0
T31	1135	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T84	0	2	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	1	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T190	0	1	0	0
T227	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6948646	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6950963	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	25	0	0
T28	8338	1	0	0
T31	1135	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	1	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T190	0	1	0	0
T227	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	22	0	0
T28	8338	1	0	0
T31	1135	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T84	0	2	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	1	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T190	0	1	0	0
T227	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	22	0	0
T28	8338	1	0	0
T31	1135	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T84	0	2	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	1	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T190	0	1	0	0
T227	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	22	0	0
T28	8338	1	0	0
T31	1135	2	0	0
T32	0	1	0	0
T33	0	1	0	0
T34	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T84	0	2	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	1	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T190	0	1	0	0
T227	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1114	0	0
T28	8338	18	0	0
T31	1135	178	0	0
T32	0	40	0	0
T33	0	103	0	0
T34	0	37	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T84	0	73	0	0
T92	738	0	0	0
T93	10267	0	0	0
T123	0	39	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	36	0	0
T190	0	38	0	0
T227	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6550	0	0
T1	8369	35	0	0
T2	14606	47	0	0
T3	12699	38	0	0
T4	13206	28	0	0
T5	97815	15	0	0
T6	495	10	0	0
T12	501	4	0	0
T13	691	0	0	0
T14	539	3	0	0
T15	727	0	0	0
T19	0	14	0	0
T49	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	4	0	0
T28	8338	0	0	0
T31	1135	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T74	16376	0	0	0
T84	0	1	0	0
T92	738	0	0	0
T93	10267	0	0	0
T112	0	1	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T238	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T10,T31,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T31,T28
1	0	Covered	T6,T1,T2
1	1	Covered	T10,T31,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T28
0	1	Covered	T72
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T31,T28
0	1	Covered	T10,T35,T27
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T31,T28
1	-	Covered	T10,T35,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T31,T28
DetectSt	168	Covered	T10,T31,T28
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T10,T31,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T31,T28
DebounceSt->IdleSt	163	Covered	T79,T65
DetectSt->IdleSt	186	Covered	T72
DetectSt->StableSt	191	Covered	T10,T31,T28
IdleSt->DebounceSt	148	Covered	T10,T31,T28
StableSt->IdleSt	206	Covered	T10,T28,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T31,T28
0	1	Covered	T10,T31,T28
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T31,T28
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T31,T28
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T31,T28
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T31,T28
DetectSt	-	-	-	-	1	-	-	Covered	T72
DetectSt	-	-	-	-	0	1	-	Covered	T10,T31,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T28,T35
StableSt	-	-	-	-	-	-	0	Covered	T10,T31,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	127	0	0
CntIncr_A	7939905	184575	0	0
CntNoWrap_A	7939905	7282620	0	0
DetectStDropOut_A	7939905	1	0	0
DetectedOut_A	7939905	143521	0	0
DetectedPulseOut_A	7939905	62	0	0
DisabledIdleSt_A	7939905	6869809	0	0
DisabledNoDetection_A	7939905	6872112	0	0
EnterDebounceSt_A	7939905	65	0	0
EnterDetectSt_A	7939905	63	0	0
EnterStableSt_A	7939905	62	0	0
PulseIsPulse_A	7939905	62	0	0
StayInStableSt	7939905	143429	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	127	0	0
T10	16230	4	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	4	0	0
T28	0	2	0	0
T29	0	4	0	0
T31	0	2	0	0
T35	0	2	0	0
T39	0	2	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	2	0	0
T149	0	4	0	0
T172	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	184575	0	0
T10	16230	168	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	64	0	0
T28	0	28	0	0
T29	0	94	0	0
T31	0	80	0	0
T35	0	3374	0	0
T39	0	100	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	13	0	0
T149	0	148	0	0
T172	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282620	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1	0	0
T72	574	1	0	0
T119	568	0	0	0
T191	34155	0	0	0
T194	18179	0	0	0
T195	27902	0	0	0
T196	35206	0	0	0
T197	524	0	0	0
T198	506	0	0	0
T199	9226	0	0	0
T200	451	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	143521	0	0
T10	16230	107	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	99	0	0
T28	0	17	0	0
T29	0	85	0	0
T31	0	645	0	0
T35	0	40	0	0
T39	0	78	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	129	0	0
T149	0	78	0	0
T172	0	121	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	1	0	0
T149	0	2	0	0
T172	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6869809	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6872112	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	65	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	1	0	0
T149	0	2	0	0
T172	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	63	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	1	0	0
T149	0	2	0	0
T172	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	1	0	0
T149	0	2	0	0
T172	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	62	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T28	0	1	0	0
T29	0	2	0	0
T31	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	1	0	0
T149	0	2	0	0
T172	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	143429	0	0
T10	16230	105	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	97	0	0
T28	0	16	0	0
T29	0	82	0	0
T31	0	643	0	0
T35	0	39	0	0
T39	0	77	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	127	0	0
T149	0	75	0	0
T172	0	118	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	31	0	0
T10	16230	2	0	0
T11	11085	0	0	0
T24	14162	0	0	0
T27	0	2	0	0
T29	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T40	21978	0	0	0
T41	702	0	0	0
T52	18320	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T84	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T119	0	1	0	0
T123	0	1	0	0
T149	0	1	0	0
T172	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T28,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T28,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T28,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T28,T38
1	0	Covered	T6,T1,T2
1	1	Covered	T28,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Covered	T29,T30,T172
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T29,T30
1	-	Covered	T29,T30,T172

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T29,T30
DetectSt	168	Covered	T28,T29,T30
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T28,T29,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T29,T30
DebounceSt->IdleSt	163	Covered	T65,T112
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T28,T29,T30
IdleSt->DebounceSt	148	Covered	T28,T29,T30
StableSt->IdleSt	206	Covered	T28,T29,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T29,T30
0	1	Covered	T28,T29,T30
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T30
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T65
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T29,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T112
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T29,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T28,T29,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T29,T30
StableSt	-	-	-	-	-	-	0	Covered	T28,T29,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	66	0	0
CntIncr_A	7939905	48680	0	0
CntNoWrap_A	7939905	7282681	0	0
DetectStDropOut_A	7939905	0	0	0
DetectedOut_A	7939905	1711	0	0
DetectedPulseOut_A	7939905	32	0	0
DisabledIdleSt_A	7939905	7015240	0	0
DisabledNoDetection_A	7939905	7017540	0	0
EnterDebounceSt_A	7939905	34	0	0
EnterDetectSt_A	7939905	32	0	0
EnterStableSt_A	7939905	32	0	0
PulseIsPulse_A	7939905	32	0	0
StayInStableSt	7939905	1661	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7939905	7284	0	0
gen_low_level_sva.LowLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	66	0	0
T28	8338	2	0	0
T29	0	2	0	0
T30	0	4	0	0
T32	0	2	0	0
T35	15959	0	0	0
T39	0	2	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	2	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	2	0	0
T166	0	2	0	0
T172	0	2	0	0
T174	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	48680	0	0
T28	8338	28	0	0
T29	0	47	0	0
T30	0	194	0	0
T32	0	22	0	0
T35	15959	0	0	0
T39	0	100	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	20	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	74	0	0
T166	0	93	0	0
T172	0	16	0	0
T174	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7282681	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1711	0	0
T28	8338	17	0	0
T29	0	12	0	0
T30	0	95	0	0
T32	0	42	0	0
T35	15959	0	0	0
T39	0	40	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	41	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	229	0	0
T166	0	40	0	0
T172	0	9	0	0
T174	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	32	0	0
T28	8338	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	15959	0	0	0
T39	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	1	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7015240	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92203	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7017540	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92215	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	34	0	0
T28	8338	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	15959	0	0	0
T39	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	1	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	32	0	0
T28	8338	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	15959	0	0	0
T39	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	1	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	32	0	0
T28	8338	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	15959	0	0	0
T39	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	1	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	32	0	0
T28	8338	1	0	0
T29	0	1	0	0
T30	0	2	0	0
T32	0	1	0	0
T35	15959	0	0	0
T39	0	1	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	1	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	1	0	0
T166	0	1	0	0
T172	0	1	0	0
T174	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1661	0	0
T28	8338	16	0	0
T29	0	11	0	0
T30	0	92	0	0
T32	0	40	0	0
T35	15959	0	0	0
T39	0	38	0	0
T42	673	0	0	0
T57	491	0	0	0
T72	0	40	0	0
T74	16376	0	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T149	0	228	0	0
T166	0	38	0	0
T172	0	8	0	0
T174	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7284	0	0
T1	8369	29	0	0
T2	14606	58	0	0
T3	12699	32	0	0
T4	13206	32	0	0
T5	97815	28	0	0
T6	495	6	0	0
T12	501	5	0	0
T13	691	3	0	0
T14	539	5	0	0
T15	727	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	13	0	0
T29	713	1	0	0
T30	0	1	0	0
T63	17486	0	0	0
T72	0	1	0	0
T84	0	1	0	0
T100	0	1	0	0
T121	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T172	0	1	0	0
T217	0	1	0	0
T259	410	0	0	0
T260	483	0	0	0
T261	501	0	0	0
T262	419	0	0	0
T263	1729	0	0	0
T264	740	0	0	0
T265	503	0	0	0
T266	406	0	0	0