Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T28,T43
1	0	Covered	T1,T3,T28

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T11,T24
0	1	Covered	T4,T11,T24
1	0	Covered	T267

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T11,T24
1	-	Covered	T4,T11,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T4,T11,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T28,T46,T268
DetectSt->IdleSt	186	Covered	T1,T3,T28
DetectSt->StableSt	191	Covered	T4,T11,T24
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T4,T11,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T46,T268
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T1,T3,T28
DetectSt	-	-	-	-	0	1	-	Covered	T4,T11,T24
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T4,T11,T24
StableSt	-	-	-	-	-	-	0	Covered	T4,T11,T24
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	2929	0	0
CntIncr_A	7939905	97245	0	0
CntNoWrap_A	7939905	7279818	0	0
DetectStDropOut_A	7939905	395	0	0
DetectedOut_A	7939905	65797	0	0
DetectedPulseOut_A	7939905	878	0	0
DisabledIdleSt_A	7939905	6833955	0	0
DisabledNoDetection_A	7939905	6836112	0	0
EnterDebounceSt_A	7939905	1499	0	0
EnterDetectSt_A	7939905	1430	0	0
EnterStableSt_A	7939905	878	0	0
PulseIsPulse_A	7939905	878	0	0
StayInStableSt	7939905	64819	0	0
gen_high_event_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	777	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	2929	0	0
T1	8369	22	0	0
T2	14606	0	0	0
T3	12699	62	0	0
T4	13206	18	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	50	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	50	0	0
T28	0	16	0	0
T43	0	28	0	0
T45	0	16	0	0
T46	0	30	0	0
T63	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	97245	0	0
T1	8369	571	0	0
T2	14606	0	0	0
T3	12699	1459	0	0
T4	13206	324	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	775	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	1950	0	0
T28	0	703	0	0
T43	0	750	0	0
T45	0	427	0	0
T46	0	1400	0	0
T63	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7279818	0	0
T1	8369	7936	0	0
T2	14606	4985	0	0
T3	12699	12217	0	0
T4	13206	12763	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	395	0	0
T3	12699	26	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	21149	0	0	0
T28	0	1	0	0
T43	0	14	0	0
T45	0	8	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T82	0	27	0	0
T83	0	13	0	0
T269	0	6	0	0
T270	0	19	0	0
T271	0	19	0	0
T272	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	65797	0	0
T4	13206	586	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	4344	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T24	0	1365	0	0
T28	0	407	0	0
T46	0	58	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T63	0	24	0	0
T242	0	2470	0	0
T244	0	1004	0	0
T273	0	569	0	0
T274	0	1225	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	878	0	0
T4	13206	9	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	25	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T24	0	25	0	0
T28	0	5	0	0
T46	0	10	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T63	0	1	0	0
T242	0	27	0	0
T244	0	15	0	0
T273	0	22	0	0
T274	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6833955	0	0
T1	8369	5202	0	0
T2	14606	4985	0	0
T3	12699	9714	0	0
T4	13206	9513	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6836112	0	0
T1	8369	5203	0	0
T2	14606	5009	0	0
T3	12699	9717	0	0
T4	13206	9515	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1499	0	0
T1	8369	11	0	0
T2	14606	0	0	0
T3	12699	31	0	0
T4	13206	9	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	25	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	25	0	0
T28	0	9	0	0
T43	0	14	0	0
T45	0	8	0	0
T46	0	20	0	0
T63	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1430	0	0
T1	8369	11	0	0
T2	14606	0	0	0
T3	12699	31	0	0
T4	13206	9	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	25	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	25	0	0
T28	0	7	0	0
T43	0	14	0	0
T45	0	8	0	0
T46	0	10	0	0
T63	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	878	0	0
T4	13206	9	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	25	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T24	0	25	0	0
T28	0	5	0	0
T46	0	10	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T63	0	1	0	0
T242	0	27	0	0
T244	0	15	0	0
T273	0	22	0	0
T274	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	878	0	0
T4	13206	9	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	25	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T24	0	25	0	0
T28	0	5	0	0
T46	0	10	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T63	0	1	0	0
T242	0	27	0	0
T244	0	15	0	0
T273	0	22	0	0
T274	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	64819	0	0
T4	13206	576	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	4318	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T24	0	1339	0	0
T28	0	402	0	0
T46	0	48	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T63	0	23	0	0
T242	0	2439	0	0
T244	0	986	0	0
T273	0	547	0	0
T274	0	1208	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	777	0	0
T4	13206	8	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	24	0	0
T19	21149	0	0	0
T20	8559	0	0	0
T24	0	24	0	0
T28	0	5	0	0
T46	0	10	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T63	0	1	0	0
T242	0	23	0	0
T244	0	12	0	0
T273	0	22	0	0
T274	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T19,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T2,T19,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T2,T19,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T19,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T8
0	1	Covered	T52,T74,T26
1	0	Covered	T28,T65

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T19,T8
0	1	Covered	T2,T19,T8
1	0	Covered	T65

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T19,T8
1	-	Covered	T2,T19,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T19,T8
DetectSt	168	Covered	T2,T19,T8
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T2,T19,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T19,T8
DebounceSt->IdleSt	163	Covered	T2,T19,T8
DetectSt->IdleSt	186	Covered	T52,T28,T74
DetectSt->StableSt	191	Covered	T2,T19,T8
IdleSt->DebounceSt	148	Covered	T2,T19,T8
StableSt->IdleSt	206	Covered	T2,T19,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T19,T8
0	1	Covered	T2,T19,T8
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T19,T8
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T19,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T19,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T19,T8
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T19,T8
DetectSt	-	-	-	-	1	-	-	Covered	T52,T28,T74
DetectSt	-	-	-	-	0	1	-	Covered	T2,T19,T8
DetectSt	-	-	-	-	0	0	-	Covered	T2,T19,T8
StableSt	-	-	-	-	-	-	1	Covered	T2,T19,T8
StableSt	-	-	-	-	-	-	0	Covered	T2,T19,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	990	0	0
CntIncr_A	7939905	55706	0	0
CntNoWrap_A	7939905	7281757	0	0
DetectStDropOut_A	7939905	83	0	0
DetectedOut_A	7939905	13661	0	0
DetectedPulseOut_A	7939905	364	0	0
DisabledIdleSt_A	7939905	6913056	0	0
DisabledNoDetection_A	7939905	6914743	0	0
EnterDebounceSt_A	7939905	543	0	0
EnterDetectSt_A	7939905	454	0	0
EnterStableSt_A	7939905	364	0	0
PulseIsPulse_A	7939905	364	0	0
StayInStableSt	7939905	13277	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	341	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	990	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	5	0	0
T10	0	2	0	0
T11	0	5	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	15	0	0
T24	0	2	0	0
T28	0	8	0	0
T40	0	13	0	0
T47	934	0	0	0
T52	0	2	0	0
T74	0	17	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	55706	0	0
T2	14606	48	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	288	0	0
T10	0	96	0	0
T11	0	109	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	1262	0	0
T24	0	65	0	0
T28	0	245	0	0
T40	0	1198	0	0
T47	934	0	0	0
T52	0	128	0	0
T74	0	1022	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7281757	0	0
T1	8369	7958	0	0
T2	14606	4982	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	83	0	0
T26	0	10	0	0
T28	8338	0	0	0
T31	1135	0	0	0
T41	702	0	0	0
T52	18320	1	0	0
T53	1228	0	0	0
T57	491	0	0	0
T62	1344	0	0	0
T74	0	7	0	0
T76	0	10	0	0
T77	0	3	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	5	0	0
T81	0	2	0	0
T84	0	10	0	0
T90	427	0	0	0
T91	707	0	0	0
T92	738	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	13661	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	64	0	0
T11	0	272	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	38	0	0
T24	0	79	0	0
T28	0	94	0	0
T33	0	6	0	0
T40	0	58	0	0
T47	934	0	0	0
T93	0	12	0	0
T94	0	22	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	364	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	7	0	0
T24	0	1	0	0
T28	0	1	0	0
T33	0	2	0	0
T40	0	6	0	0
T47	934	0	0	0
T93	0	2	0	0
T94	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6913056	0	0
T1	8369	7958	0	0
T2	14606	4880	0	0
T3	12699	12279	0	0
T4	13206	12196	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6914743	0	0
T1	8369	7960	0	0
T2	14606	4901	0	0
T3	12699	12283	0	0
T4	13206	12199	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	543	0	0
T2	14606	3	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	3	0	0
T10	0	2	0	0
T11	0	4	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	8	0	0
T24	0	1	0	0
T28	0	5	0	0
T40	0	7	0	0
T47	934	0	0	0
T52	0	1	0	0
T74	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	454	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	7	0	0
T24	0	1	0	0
T28	0	3	0	0
T40	0	6	0	0
T47	934	0	0	0
T52	0	1	0	0
T74	0	7	0	0
T93	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	364	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	7	0	0
T24	0	1	0	0
T28	0	1	0	0
T33	0	2	0	0
T40	0	6	0	0
T47	934	0	0	0
T93	0	2	0	0
T94	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	364	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	7	0	0
T24	0	1	0	0
T28	0	1	0	0
T33	0	2	0	0
T40	0	6	0	0
T47	934	0	0	0
T93	0	2	0	0
T94	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	13277	0	0
T2	14606	2	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	62	0	0
T11	0	271	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	31	0	0
T24	0	78	0	0
T28	0	93	0	0
T33	0	4	0	0
T40	0	52	0	0
T47	934	0	0	0
T93	0	10	0	0
T94	0	17	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	341	0	0
T2	14606	1	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	2	0	0
T11	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	0	7	0	0
T24	0	1	0	0
T25	0	5	0	0
T33	0	2	0	0
T40	0	6	0	0
T47	934	0	0	0
T93	0	2	0	0
T94	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T4,T28
1	0	Covered	T3,T4,T28

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T24
0	1	Covered	T1,T11,T24
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T24
1	-	Covered	T1,T11,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T11,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T28,T46,T268
DetectSt->IdleSt	186	Covered	T3,T4,T28
DetectSt->StableSt	191	Covered	T1,T11,T24
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T11,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T46,T268
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T3,T4,T28
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T24
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T11,T24
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T24
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	3324	0	0
CntIncr_A	7939905	116399	0	0
CntNoWrap_A	7939905	7279423	0	0
DetectStDropOut_A	7939905	403	0	0
DetectedOut_A	7939905	75177	0	0
DetectedPulseOut_A	7939905	1029	0	0
DisabledIdleSt_A	7939905	6825918	0	0
DisabledNoDetection_A	7939905	6828077	0	0
EnterDebounceSt_A	7939905	1697	0	0
EnterDetectSt_A	7939905	1628	0	0
EnterStableSt_A	7939905	1029	0	0
PulseIsPulse_A	7939905	1029	0	0
StayInStableSt	7939905	74049	0	0
gen_high_event_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	930	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	3324	0	0
T1	8369	10	0	0
T2	14606	0	0	0
T3	12699	32	0	0
T4	13206	54	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	18	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	32	0	0
T28	0	16	0	0
T43	0	58	0	0
T45	0	52	0	0
T46	0	26	0	0
T63	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	116399	0	0
T1	8369	140	0	0
T2	14606	0	0	0
T3	12699	746	0	0
T4	13206	1423	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	378	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	1344	0	0
T28	0	688	0	0
T43	0	1562	0	0
T45	0	1411	0	0
T46	0	1220	0	0
T63	0	477	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7279423	0	0
T1	8369	7948	0	0
T2	14606	4985	0	0
T3	12699	12247	0	0
T4	13206	12727	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	403	0	0
T3	12699	13	0	0
T4	13206	14	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	21149	0	0	0
T28	0	1	0	0
T43	0	29	0	0
T45	0	26	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T69	0	13	0	0
T82	0	24	0	0
T83	0	25	0	0
T268	0	4	0	0
T275	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	75177	0	0
T1	8369	127	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	791	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	776	0	0
T28	0	398	0	0
T46	0	57	0	0
T63	0	304	0	0
T160	0	674	0	0
T242	0	371	0	0
T244	0	668	0	0
T273	0	1361	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1029	0	0
T1	8369	5	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	9	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	16	0	0
T28	0	5	0	0
T46	0	5	0	0
T63	0	9	0	0
T160	0	13	0	0
T242	0	9	0	0
T244	0	15	0	0
T273	0	15	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6825918	0	0
T1	8369	5185	0	0
T2	14606	4985	0	0
T3	12699	9714	0	0
T4	13206	9958	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6828077	0	0
T1	8369	5186	0	0
T2	14606	5009	0	0
T3	12699	9717	0	0
T4	13206	9961	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1697	0	0
T1	8369	5	0	0
T2	14606	0	0	0
T3	12699	16	0	0
T4	13206	27	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	9	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	16	0	0
T28	0	9	0	0
T43	0	29	0	0
T45	0	26	0	0
T46	0	21	0	0
T63	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1628	0	0
T1	8369	5	0	0
T2	14606	0	0	0
T3	12699	16	0	0
T4	13206	27	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	9	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	16	0	0
T28	0	7	0	0
T43	0	29	0	0
T45	0	26	0	0
T46	0	5	0	0
T63	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1029	0	0
T1	8369	5	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	9	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	16	0	0
T28	0	5	0	0
T46	0	5	0	0
T63	0	9	0	0
T160	0	13	0	0
T242	0	9	0	0
T244	0	15	0	0
T273	0	15	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1029	0	0
T1	8369	5	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	9	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	16	0	0
T28	0	5	0	0
T46	0	5	0	0
T63	0	9	0	0
T160	0	13	0	0
T242	0	9	0	0
T244	0	15	0	0
T273	0	15	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	74049	0	0
T1	8369	122	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	782	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	759	0	0
T28	0	393	0	0
T46	0	52	0	0
T63	0	294	0	0
T160	0	661	0	0
T242	0	362	0	0
T244	0	651	0	0
T273	0	1346	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	930	0	0
T1	8369	5	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	9	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	15	0	0
T28	0	5	0	0
T46	0	5	0	0
T63	0	8	0	0
T160	0	13	0	0
T242	0	9	0	0
T244	0	13	0	0
T273	0	15	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T19,T20,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T19,T20,T8

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T19,T20,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T19,T20,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T8
0	1	Covered	T8,T27,T122
1	0	Covered	T28,T65

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T19,T20,T10
0	1	Covered	T19,T20,T10
1	0	Covered	T66,T65

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T19,T20,T10
1	-	Covered	T19,T20,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T19,T20,T8
DetectSt	168	Covered	T19,T20,T8
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T19,T20,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T19,T20,T8
DebounceSt->IdleSt	163	Covered	T20,T28,T74
DetectSt->IdleSt	186	Covered	T8,T28,T27
DetectSt->StableSt	191	Covered	T19,T20,T10
IdleSt->DebounceSt	148	Covered	T19,T20,T8
StableSt->IdleSt	206	Covered	T19,T20,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T19,T20,T8
0	1	Covered	T19,T20,T8
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T19,T20,T8
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T19,T20,T8
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T19,T20,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T74,T25
DebounceSt	-	0	0	-	-	-	-	Covered	T19,T20,T8
DetectSt	-	-	-	-	1	-	-	Covered	T8,T28,T27
DetectSt	-	-	-	-	0	1	-	Covered	T19,T20,T10
DetectSt	-	-	-	-	0	0	-	Covered	T19,T20,T8
StableSt	-	-	-	-	-	-	1	Covered	T19,T20,T10
StableSt	-	-	-	-	-	-	0	Covered	T19,T20,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	798	0	0
CntIncr_A	7939905	43519	0	0
CntNoWrap_A	7939905	7281949	0	0
DetectStDropOut_A	7939905	47	0	0
DetectedOut_A	7939905	14244	0	0
DetectedPulseOut_A	7939905	328	0	0
DisabledIdleSt_A	7939905	6913819	0	0
DisabledNoDetection_A	7939905	6915588	0	0
EnterDebounceSt_A	7939905	421	0	0
EnterDetectSt_A	7939905	379	0	0
EnterStableSt_A	7939905	328	0	0
PulseIsPulse_A	7939905	328	0	0
StayInStableSt	7939905	13892	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	798	0	0
T8	49691	2	0	0
T9	777	0	0	0
T10	16230	2	0	0
T19	21149	4	0	0
T20	8559	3	0	0
T24	0	2	0	0
T28	0	7	0	0
T40	0	6	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	12	0	0
T75	427	0	0	0
T93	0	4	0	0
T94	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	43519	0	0
T8	49691	168	0	0
T9	777	0	0	0
T10	16230	133	0	0
T19	21149	318	0	0
T20	8559	154	0	0
T24	0	73	0	0
T28	0	237	0	0
T40	0	336	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	578	0	0
T75	427	0	0	0
T93	0	202	0	0
T94	0	196	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7281949	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	47	0	0
T8	49691	1	0	0
T9	777	0	0	0
T10	16230	0	0	0
T11	11085	0	0	0
T27	0	2	0	0
T40	21978	0	0	0
T60	504	0	0	0
T61	519	0	0	0
T75	427	0	0	0
T79	0	1	0	0
T88	404	0	0	0
T89	412	0	0	0
T122	0	7	0	0
T151	0	6	0	0
T204	0	2	0	0
T221	0	8	0	0
T240	0	9	0	0
T276	0	2	0	0
T277	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	14244	0	0
T8	49691	0	0	0
T9	777	0	0	0
T10	16230	5	0	0
T19	21149	28	0	0
T20	8559	46	0	0
T24	0	72	0	0
T28	0	93	0	0
T33	0	57	0	0
T40	0	242	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	143	0	0
T75	427	0	0	0
T93	0	62	0	0
T94	0	134	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	328	0	0
T8	49691	0	0	0
T9	777	0	0	0
T10	16230	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	1	0	0
T28	0	1	0	0
T33	0	1	0	0
T40	0	3	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	5	0	0
T75	427	0	0	0
T93	0	2	0	0
T94	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6913819	0	0
T1	8369	7831	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12781	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6915588	0	0
T1	8369	7833	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	421	0	0
T8	49691	1	0	0
T9	777	0	0	0
T10	16230	1	0	0
T19	21149	2	0	0
T20	8559	2	0	0
T24	0	1	0	0
T28	0	5	0	0
T40	0	3	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	7	0	0
T75	427	0	0	0
T93	0	2	0	0
T94	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	379	0	0
T8	49691	1	0	0
T9	777	0	0	0
T10	16230	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	1	0	0
T28	0	2	0	0
T40	0	3	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	5	0	0
T75	427	0	0	0
T93	0	2	0	0
T94	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	328	0	0
T8	49691	0	0	0
T9	777	0	0	0
T10	16230	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	1	0	0
T28	0	1	0	0
T33	0	1	0	0
T40	0	3	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	5	0	0
T75	427	0	0	0
T93	0	2	0	0
T94	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	328	0	0
T8	49691	0	0	0
T9	777	0	0	0
T10	16230	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	1	0	0
T28	0	1	0	0
T33	0	1	0	0
T40	0	3	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	5	0	0
T75	427	0	0	0
T93	0	2	0	0
T94	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	13892	0	0
T8	49691	0	0	0
T9	777	0	0	0
T10	16230	4	0	0
T19	21149	26	0	0
T20	8559	45	0	0
T24	0	71	0	0
T28	0	92	0	0
T33	0	56	0	0
T40	0	239	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	138	0	0
T75	427	0	0	0
T93	0	60	0	0
T94	0	131	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	299	0	0
T8	49691	0	0	0
T9	777	0	0	0
T10	16230	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	1	0	0
T25	0	16	0	0
T33	0	1	0	0
T40	0	3	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T74	0	5	0	0
T75	427	0	0	0
T93	0	2	0	0
T94	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T3,T28,T43
1	0	Covered	T3,T28,T63

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T11
0	1	Covered	T1,T4,T11
1	0	Covered	T1,T68,T65

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T4,T11
1	-	Covered	T1,T4,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T4,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T28,T46,T268
DetectSt->IdleSt	186	Covered	T3,T28,T43
DetectSt->StableSt	191	Covered	T1,T4,T11
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T4,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T46,T268
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T3,T28,T43
DetectSt	-	-	-	-	0	1	-	Covered	T1,T4,T11
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T4,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T4,T11
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	3226	0	0
CntIncr_A	7939905	108208	0	0
CntNoWrap_A	7939905	7279521	0	0
DetectStDropOut_A	7939905	337	0	0
DetectedOut_A	7939905	82675	0	0
DetectedPulseOut_A	7939905	1039	0	0
DisabledIdleSt_A	7939905	6823425	0	0
DisabledNoDetection_A	7939905	6825581	0	0
EnterDebounceSt_A	7939905	1647	0	0
EnterDetectSt_A	7939905	1581	0	0
EnterStableSt_A	7939905	1039	0	0
PulseIsPulse_A	7939905	1039	0	0
StayInStableSt	7939905	81534	0	0
gen_high_event_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	922	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	3226	0	0
T1	8369	28	0	0
T2	14606	0	0	0
T3	12699	36	0	0
T4	13206	26	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	26	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	66	0	0
T28	0	16	0	0
T43	0	20	0	0
T45	0	24	0	0
T46	0	14	0	0
T63	0	46	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	108208	0	0
T1	8369	462	0	0
T2	14606	0	0	0
T3	12699	838	0	0
T4	13206	520	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	442	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	2574	0	0
T28	0	597	0	0
T43	0	533	0	0
T45	0	643	0	0
T46	0	589	0	0
T63	0	1303	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7279521	0	0
T1	8369	7930	0	0
T2	14606	4985	0	0
T3	12699	12243	0	0
T4	13206	12755	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	337	0	0
T3	12699	16	0	0
T4	13206	0	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T19	21149	0	0	0
T28	0	1	0	0
T43	0	10	0	0
T45	0	12	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T63	0	15	0	0
T68	0	15	0	0
T82	0	11	0	0
T83	0	9	0	0
T268	0	14	0	0
T278	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	82675	0	0
T1	8369	254	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	912	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	1972	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	2388	0	0
T28	0	515	0	0
T46	0	96	0	0
T242	0	1975	0	0
T244	0	24	0	0
T273	0	640	0	0
T279	0	4300	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1039	0	0
T1	8369	14	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	13	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	13	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	33	0	0
T28	0	5	0	0
T46	0	3	0	0
T242	0	33	0	0
T244	0	3	0	0
T273	0	15	0	0
T279	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6823425	0	0
T1	8369	5204	0	0
T2	14606	4985	0	0
T3	12699	9714	0	0
T4	13206	9205	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6825581	0	0
T1	8369	5205	0	0
T2	14606	5009	0	0
T3	12699	9717	0	0
T4	13206	9205	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1647	0	0
T1	8369	14	0	0
T2	14606	0	0	0
T3	12699	18	0	0
T4	13206	13	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	13	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	33	0	0
T28	0	9	0	0
T43	0	10	0	0
T45	0	12	0	0
T46	0	11	0	0
T63	0	23	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1581	0	0
T1	8369	14	0	0
T2	14606	0	0	0
T3	12699	18	0	0
T4	13206	13	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	13	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	33	0	0
T28	0	7	0	0
T43	0	10	0	0
T45	0	12	0	0
T46	0	3	0	0
T63	0	23	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1039	0	0
T1	8369	14	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	13	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	13	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	33	0	0
T28	0	5	0	0
T46	0	3	0	0
T242	0	33	0	0
T244	0	3	0	0
T273	0	15	0	0
T279	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1039	0	0
T1	8369	14	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	13	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	13	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	33	0	0
T28	0	5	0	0
T46	0	3	0	0
T242	0	33	0	0
T244	0	3	0	0
T273	0	15	0	0
T279	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	81534	0	0
T1	8369	240	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	896	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	1958	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	2353	0	0
T28	0	510	0	0
T46	0	93	0	0
T242	0	1938	0	0
T244	0	21	0	0
T273	0	625	0	0
T279	0	4269	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	922	0	0
T1	8369	4	0	0
T2	14606	0	0	0
T3	12699	0	0	0
T4	13206	10	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	12	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	31	0	0
T28	0	5	0	0
T46	0	3	0	0
T242	0	29	0	0
T244	0	3	0	0
T273	0	15	0	0
T279	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T4,T19,T20

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T4,T19,T20

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T4,T19,T20

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T19
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T19,T20

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T4,T19,T20
0	1	Covered	T40,T93,T94
1	0	Covered	T28,T65

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T4,T19,T20
0	1	Covered	T4,T19,T20
1	0	Covered	T28,T65

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T4,T19,T20
1	-	Covered	T4,T19,T20

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T19,T20
DetectSt	168	Covered	T4,T19,T20
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T4,T19,T20

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T4,T19,T20
DebounceSt->IdleSt	163	Covered	T20,T8,T28
DetectSt->IdleSt	186	Covered	T40,T28,T93
DetectSt->StableSt	191	Covered	T4,T19,T20
IdleSt->DebounceSt	148	Covered	T4,T19,T20
StableSt->IdleSt	206	Covered	T4,T19,T20

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T19,T20
0	1	Covered	T4,T19,T20
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T4,T19,T20
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T19,T20
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T4,T19,T20
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T8,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T19,T20
DetectSt	-	-	-	-	1	-	-	Covered	T40,T28,T93
DetectSt	-	-	-	-	0	1	-	Covered	T4,T19,T20
DetectSt	-	-	-	-	0	0	-	Covered	T4,T19,T20
StableSt	-	-	-	-	-	-	1	Covered	T4,T19,T20
StableSt	-	-	-	-	-	-	0	Covered	T4,T19,T20
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	822	0	0
CntIncr_A	7939905	45257	0	0
CntNoWrap_A	7939905	7281925	0	0
DetectStDropOut_A	7939905	75	0	0
DetectedOut_A	7939905	14905	0	0
DetectedPulseOut_A	7939905	305	0	0
DisabledIdleSt_A	7939905	6896394	0	0
DisabledNoDetection_A	7939905	6898126	0	0
EnterDebounceSt_A	7939905	439	0	0
EnterDetectSt_A	7939905	388	0	0
EnterStableSt_A	7939905	305	0	0
PulseIsPulse_A	7939905	305	0	0
StayInStableSt	7939905	14569	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	271	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	822	0	0
T4	13206	6	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	9	0	0
T11	0	2	0	0
T19	21149	4	0	0
T20	8559	3	0	0
T24	0	4	0	0
T28	0	8	0	0
T40	0	8	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	12	0	0
T74	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	45257	0	0
T4	13206	267	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	597	0	0
T11	0	59	0	0
T19	21149	222	0	0
T20	8559	169	0	0
T24	0	112	0	0
T28	0	353	0	0
T40	0	768	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	678	0	0
T74	0	693	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7281925	0	0
T1	8369	7958	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	12775	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	75	0	0
T24	14162	0	0	0
T31	1135	0	0	0
T40	21978	4	0	0
T41	702	0	0	0
T52	18320	0	0	0
T53	1228	0	0	0
T62	1344	0	0	0
T77	0	1	0	0
T80	0	3	0	0
T81	0	4	0	0
T89	412	0	0	0
T90	427	0	0	0
T91	707	0	0	0
T93	0	4	0	0
T94	0	1	0	0
T221	0	8	0	0
T240	0	1	0	0
T246	0	1	0	0
T280	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	14905	0	0
T4	13206	136	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	154	0	0
T11	0	278	0	0
T19	21149	124	0	0
T20	8559	31	0	0
T24	0	177	0	0
T25	0	32	0	0
T28	0	94	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	92	0	0
T74	0	28	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	305	0	0
T4	13206	3	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T28	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	6	0	0
T74	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6896394	0	0
T1	8369	7704	0	0
T2	14606	4985	0	0
T3	12699	12279	0	0
T4	13206	11872	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6898126	0	0
T1	8369	7706	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	11873	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	439	0	0
T4	13206	3	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	6	0	0
T11	0	1	0	0
T19	21149	2	0	0
T20	8559	2	0	0
T24	0	2	0	0
T28	0	5	0	0
T40	0	4	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	6	0	0
T74	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	388	0	0
T4	13206	3	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	2	0	0
T28	0	3	0	0
T40	0	4	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	6	0	0
T74	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	305	0	0
T4	13206	3	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T28	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	6	0	0
T74	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	305	0	0
T4	13206	3	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T28	0	1	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	6	0	0
T74	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	14569	0	0
T4	13206	133	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	151	0	0
T11	0	277	0	0
T19	21149	122	0	0
T20	8559	30	0	0
T24	0	175	0	0
T25	0	31	0	0
T28	0	93	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	86	0	0
T74	0	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	271	0	0
T4	13206	3	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	3	0	0
T11	0	1	0	0
T19	21149	2	0	0
T20	8559	1	0	0
T24	0	2	0	0
T25	0	1	0	0
T26	0	4	0	0
T47	934	0	0	0
T48	402	0	0	0
T49	422	0	0	0
T50	431	0	0	0
T51	529	0	0	0
T52	0	6	0	0
T74	0	5	0	0