Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T28,T43,T45
1	0	Covered	T11,T28,T279

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T69,T281

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T28,T46,T268
DetectSt->IdleSt	186	Covered	T11,T28,T43
DetectSt->StableSt	191	Covered	T1,T3,T4
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T4
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T46,T268
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T11,T28,T43
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	3072	0	0
CntIncr_A	7939905	99099	0	0
CntNoWrap_A	7939905	7279675	0	0
DetectStDropOut_A	7939905	289	0	0
DetectedOut_A	7939905	86467	0	0
DetectedPulseOut_A	7939905	1037	0	0
DisabledIdleSt_A	7939905	6820221	0	0
DisabledNoDetection_A	7939905	6822354	0	0
EnterDebounceSt_A	7939905	1573	0	0
EnterDetectSt_A	7939905	1500	0	0
EnterStableSt_A	7939905	1037	0	0
PulseIsPulse_A	7939905	1037	0	0
StayInStableSt	7939905	85306	0	0
gen_high_event_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	897	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	3072	0	0
T1	8369	50	0	0
T2	14606	0	0	0
T3	12699	30	0	0
T4	13206	30	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	6	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	36	0	0
T28	0	16	0	0
T43	0	58	0	0
T45	0	46	0	0
T46	0	17	0	0
T63	0	28	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	99099	0	0
T1	8369	950	0	0
T2	14606	0	0	0
T3	12699	675	0	0
T4	13206	720	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	157	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	1530	0	0
T28	0	486	0	0
T43	0	1562	0	0
T45	0	1244	0	0
T46	0	733	0	0
T63	0	588	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7279675	0	0
T1	8369	7908	0	0
T2	14606	4985	0	0
T3	12699	12249	0	0
T4	13206	12751	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	289	0	0
T28	8338	1	0	0
T35	15959	0	0	0
T42	673	0	0	0
T43	0	29	0	0
T45	0	23	0	0
T57	491	0	0	0
T69	0	6	0	0
T74	16376	0	0	0
T82	0	6	0	0
T83	0	13	0	0
T92	738	0	0	0
T93	10267	0	0	0
T124	537	0	0	0
T125	401	0	0	0
T126	410	0	0	0
T224	0	13	0	0
T268	0	4	0	0
T269	0	7	0	0
T270	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	86467	0	0
T1	8369	1478	0	0
T2	14606	0	0	0
T3	12699	1678	0	0
T4	13206	1519	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	1417	0	0
T28	0	417	0	0
T46	0	102	0	0
T63	0	1813	0	0
T242	0	1055	0	0
T244	0	1621	0	0
T273	0	99	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1037	0	0
T1	8369	25	0	0
T2	14606	0	0	0
T3	12699	15	0	0
T4	13206	15	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	18	0	0
T28	0	5	0	0
T46	0	3	0	0
T63	0	14	0	0
T242	0	15	0	0
T244	0	16	0	0
T273	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6820221	0	0
T1	8369	4045	0	0
T2	14606	4985	0	0
T3	12699	8058	0	0
T4	13206	8496	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6822354	0	0
T1	8369	4045	0	0
T2	14606	5009	0	0
T3	12699	8058	0	0
T4	13206	8497	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1573	0	0
T1	8369	25	0	0
T2	14606	0	0	0
T3	12699	15	0	0
T4	13206	15	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	3	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	18	0	0
T28	0	9	0	0
T43	0	29	0	0
T45	0	23	0	0
T46	0	14	0	0
T63	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1500	0	0
T1	8369	25	0	0
T2	14606	0	0	0
T3	12699	15	0	0
T4	13206	15	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T11	0	3	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	18	0	0
T28	0	7	0	0
T43	0	29	0	0
T45	0	23	0	0
T46	0	3	0	0
T63	0	14	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1037	0	0
T1	8369	25	0	0
T2	14606	0	0	0
T3	12699	15	0	0
T4	13206	15	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	18	0	0
T28	0	5	0	0
T46	0	3	0	0
T63	0	14	0	0
T242	0	15	0	0
T244	0	16	0	0
T273	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	1037	0	0
T1	8369	25	0	0
T2	14606	0	0	0
T3	12699	15	0	0
T4	13206	15	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	18	0	0
T28	0	5	0	0
T46	0	3	0	0
T63	0	14	0	0
T242	0	15	0	0
T244	0	16	0	0
T273	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	85306	0	0
T1	8369	1452	0	0
T2	14606	0	0	0
T3	12699	1660	0	0
T4	13206	1502	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	1397	0	0
T28	0	412	0	0
T46	0	99	0	0
T63	0	1795	0	0
T242	0	1037	0	0
T244	0	1603	0	0
T273	0	97	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	897	0	0
T1	8369	24	0	0
T2	14606	0	0	0
T3	12699	12	0	0
T4	13206	13	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T24	0	16	0	0
T28	0	5	0	0
T46	0	3	0	0
T63	0	10	0	0
T242	0	12	0	0
T244	0	14	0	0
T273	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T6,T1,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T6,T1,T2
1	1	Covered	T6,T1,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T6,T1,T2	VC_COV_UNR
1	Covered	T1,T3,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T1,T3,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T37,T132,T282
1	0	Covered	T28,T65

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
1	0	Covered	T28

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T4
1	-	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T4
DetectSt	168	Covered	T1,T3,T4
IdleSt	163	Covered	T6,T1,T2
StableSt	191	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T4
DebounceSt->IdleSt	163	Covered	T20,T8,T28
DetectSt->IdleSt	186	Covered	T28,T33,T37
DetectSt->StableSt	191	Covered	T1,T3,T4
IdleSt->DebounceSt	148	Covered	T1,T3,T4
StableSt->IdleSt	206	Covered	T1,T3,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T4
0	1	Covered	T1,T3,T4
0	0	Excluded	T6,T1,T2	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	-	-	-	-	-	-	Covered	T6,T1,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T28,T65
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T20,T8,T93
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	1	-	-	Covered	T28,T37,T132
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T4
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T4
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T6,T1,T2
0	Covered	T6,T1,T2

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7939905	844	0	0
CntIncr_A	7939905	42795	0	0
CntNoWrap_A	7939905	7281903	0	0
DetectStDropOut_A	7939905	33	0	0
DetectedOut_A	7939905	16248	0	0
DetectedPulseOut_A	7939905	364	0	0
DisabledIdleSt_A	7939905	6887839	0	0
DisabledNoDetection_A	7939905	6889542	0	0
EnterDebounceSt_A	7939905	444	0	0
EnterDetectSt_A	7939905	403	0	0
EnterStableSt_A	7939905	364	0	0
PulseIsPulse_A	7939905	364	0	0
StayInStableSt	7939905	15864	0	0
gen_high_level_sva.HighLevelEvent_A	7939905	7285103	0	0
gen_not_sticky_sva.StableStDropOut_A	7939905	341	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	844	0	0
T1	8369	2	0	0
T2	14606	0	0	0
T3	12699	6	0	0
T4	13206	8	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	3	0	0
T24	0	4	0	0
T28	0	8	0	0
T40	0	6	0	0
T52	0	8	0	0
T93	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	42795	0	0
T1	8369	32	0	0
T2	14606	0	0	0
T3	12699	234	0	0
T4	13206	240	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	84	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	146	0	0
T24	0	130	0	0
T28	0	253	0	0
T40	0	336	0	0
T52	0	340	0	0
T93	0	292	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7281903	0	0
T1	8369	7956	0	0
T2	14606	4985	0	0
T3	12699	12273	0	0
T4	13206	12773	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	33	0	0
T27	35167	0	0	0
T37	15214	1	0	0
T45	5318	0	0	0
T100	0	1	0	0
T132	21229	8	0	0
T175	39681	0	0	0
T176	919	0	0	0
T177	426	0	0	0
T178	414	0	0	0
T179	422	0	0	0
T180	404	0	0	0
T188	0	1	0	0
T246	0	2	0	0
T282	0	1	0	0
T283	0	2	0	0
T284	0	9	0	0
T285	0	3	0	0
T286	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	16248	0	0
T1	8369	63	0	0
T2	14606	0	0	0
T3	12699	125	0	0
T4	13206	298	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	54	0	0
T24	0	159	0	0
T25	0	280	0	0
T28	0	94	0	0
T40	0	240	0	0
T52	0	172	0	0
T93	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	364	0	0
T1	8369	1	0	0
T2	14606	0	0	0
T3	12699	3	0	0
T4	13206	4	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	1	0	0
T24	0	2	0	0
T25	0	8	0	0
T28	0	1	0	0
T40	0	3	0	0
T52	0	4	0	0
T93	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6887839	0	0
T1	8369	6481	0	0
T2	14606	4985	0	0
T3	12699	10604	0	0
T4	13206	11264	0	0
T5	97815	92550	0	0
T6	495	94	0	0
T12	501	100	0	0
T13	691	290	0	0
T14	539	138	0	0
T15	727	326	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	6889542	0	0
T1	8369	6482	0	0
T2	14606	5009	0	0
T3	12699	10605	0	0
T4	13206	11266	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	444	0	0
T1	8369	1	0	0
T2	14606	0	0	0
T3	12699	3	0	0
T4	13206	4	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T8	0	1	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	2	0	0
T24	0	2	0	0
T28	0	5	0	0
T40	0	3	0	0
T52	0	4	0	0
T93	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	403	0	0
T1	8369	1	0	0
T2	14606	0	0	0
T3	12699	3	0	0
T4	13206	4	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	1	0	0
T24	0	2	0	0
T28	0	3	0	0
T33	0	1	0	0
T40	0	3	0	0
T52	0	4	0	0
T93	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	364	0	0
T1	8369	1	0	0
T2	14606	0	0	0
T3	12699	3	0	0
T4	13206	4	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	1	0	0
T24	0	2	0	0
T25	0	8	0	0
T28	0	1	0	0
T40	0	3	0	0
T52	0	4	0	0
T93	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	364	0	0
T1	8369	1	0	0
T2	14606	0	0	0
T3	12699	3	0	0
T4	13206	4	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	1	0	0
T24	0	2	0	0
T25	0	8	0	0
T28	0	1	0	0
T40	0	3	0	0
T52	0	4	0	0
T93	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	15864	0	0
T1	8369	62	0	0
T2	14606	0	0	0
T3	12699	122	0	0
T4	13206	294	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	53	0	0
T24	0	157	0	0
T25	0	272	0	0
T28	0	93	0	0
T40	0	237	0	0
T52	0	168	0	0
T93	0	7	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	7285103	0	0
T1	8369	7960	0	0
T2	14606	5009	0	0
T3	12699	12283	0	0
T4	13206	12785	0	0
T5	97815	92564	0	0
T6	495	95	0	0
T12	501	101	0	0
T13	691	291	0	0
T14	539	139	0	0
T15	727	327	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7939905	341	0	0
T1	8369	1	0	0
T2	14606	0	0	0
T3	12699	3	0	0
T4	13206	4	0	0
T5	97815	0	0	0
T7	516679	0	0	0
T12	501	0	0	0
T13	691	0	0	0
T14	539	0	0	0
T15	727	0	0	0
T20	0	1	0	0
T24	0	2	0	0
T25	0	8	0	0
T26	0	4	0	0
T40	0	3	0	0
T52	0	4	0	0
T93	0	2	0	0