Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1131775087	10873	0	0
auto_block_debounce_ctl_rd_A	1131775087	2099	0	0
auto_block_out_ctl_rd_A	1131775087	2505	0	0
com_det_ctl_0_rd_A	1131775087	3876	0	0
com_det_ctl_1_rd_A	1131775087	4062	0	0
com_det_ctl_2_rd_A	1131775087	4042	0	0
com_det_ctl_3_rd_A	1131775087	4219	0	0
com_out_ctl_0_rd_A	1131775087	4312	0	0
com_out_ctl_1_rd_A	1131775087	4386	0	0
com_out_ctl_2_rd_A	1131775087	4310	0	0
com_out_ctl_3_rd_A	1131775087	4350	0	0
com_pre_det_ctl_0_rd_A	1131775087	1417	0	0
com_pre_det_ctl_1_rd_A	1131775087	1522	0	0
com_pre_det_ctl_2_rd_A	1131775087	1430	0	0
com_pre_det_ctl_3_rd_A	1131775087	1485	0	0
com_pre_sel_ctl_0_rd_A	1131775087	4377	0	0
com_pre_sel_ctl_1_rd_A	1131775087	4730	0	0
com_pre_sel_ctl_2_rd_A	1131775087	4329	0	0
com_pre_sel_ctl_3_rd_A	1131775087	4523	0	0
com_sel_ctl_0_rd_A	1131775087	4303	0	0
com_sel_ctl_1_rd_A	1131775087	4503	0	0
com_sel_ctl_2_rd_A	1131775087	4710	0	0
com_sel_ctl_3_rd_A	1131775087	4650	0	0
ec_rst_ctl_rd_A	1131775087	2603	0	0
intr_enable_rd_A	1131775087	2162	0	0
key_intr_ctl_rd_A	1131775087	3293	0	0
key_intr_debounce_ctl_rd_A	1131775087	1464	0	0
key_invert_ctl_rd_A	1131775087	4888	0	0
pin_allowed_ctl_rd_A	1131775087	5558	0	0
pin_out_ctl_rd_A	1131775087	4421	0	0
pin_out_value_rd_A	1131775087	4676	0	0
regwen_rd_A	1131775087	1595	0	0
ulp_ac_debounce_ctl_rd_A	1131775087	1752	0	0
ulp_ctl_rd_A	1131775087	1615	0	0
ulp_lid_debounce_ctl_rd_A	1131775087	1717	0	0
ulp_pwrb_debounce_ctl_rd_A	1131775087	1577	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	10873	0	0
T2	364111	16	0	0
T3	152394	0	0	0
T4	165075	0	0	0
T5	345646	11	0	0
T7	56848	0	0	0
T8	0	10	0	0
T10	0	10	0	0
T12	250839	0	0	0
T13	86445	0	0	0
T14	21564	0	0	0
T15	90894	0	0	0
T27	0	4	0	0
T33	0	22	0	0
T37	0	10	0	0
T47	219597	0	0	0
T64	0	7	0	0
T77	0	9	0	0
T175	0	9	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	2099	0	0
T4	165075	0	0	0
T5	345646	0	0	0
T7	56848	0	0	0
T15	90894	16	0	0
T19	391266	0	0	0
T20	406597	0	0	0
T47	219597	0	0	0
T48	193263	0	0	0
T49	156397	0	0	0
T50	23727	0	0	0
T64	0	22	0	0
T79	0	23	0	0
T175	0	32	0	0
T227	0	43	0	0
T308	0	3	0	0
T312	0	6	0	0
T313	0	17	0	0
T314	0	7	0	0
T315	0	14	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	2505	0	0
T4	165075	0	0	0
T5	345646	0	0	0
T7	56848	0	0	0
T15	90894	14	0	0
T19	391266	0	0	0
T20	406597	0	0	0
T47	219597	0	0	0
T48	193263	0	0	0
T49	156397	0	0	0
T50	23727	0	0	0
T64	0	21	0	0
T79	0	19	0	0
T175	0	33	0	0
T227	0	58	0	0
T308	0	1	0	0
T312	0	5	0	0
T313	0	5	0	0
T314	0	11	0	0
T315	0	10	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	3876	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	33	0	0
T40	0	65	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	26	0	0
T74	0	69	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	40	0	0
T122	0	148	0	0
T175	0	13	0	0
T275	0	65	0	0
T280	0	81	0	0
T316	0	45	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4062	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	38	0	0
T40	0	63	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	26	0	0
T74	0	81	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	73	0	0
T122	0	134	0	0
T175	0	19	0	0
T275	0	60	0	0
T280	0	96	0	0
T316	0	58	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4042	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	66	0	0
T40	0	66	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	22	0	0
T74	0	60	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	46	0	0
T122	0	121	0	0
T175	0	7	0	0
T275	0	76	0	0
T280	0	78	0	0
T316	0	37	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4219	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	27	0	0
T40	0	70	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	22	0	0
T74	0	62	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	64	0	0
T122	0	199	0	0
T175	0	20	0	0
T275	0	77	0	0
T280	0	63	0	0
T316	0	38	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4312	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	26	0	0
T40	0	75	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	26	0	0
T74	0	68	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	26	0	0
T122	0	153	0	0
T175	0	31	0	0
T275	0	60	0	0
T280	0	75	0	0
T316	0	41	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4386	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	40	0	0
T40	0	49	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	21	0	0
T74	0	75	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	30	0	0
T122	0	140	0	0
T175	0	21	0	0
T275	0	64	0	0
T280	0	54	0	0
T316	0	33	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4310	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	26	0	0
T40	0	58	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	12	0	0
T74	0	77	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	40	0	0
T122	0	144	0	0
T175	0	10	0	0
T275	0	73	0	0
T280	0	73	0	0
T316	0	36	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4350	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	37	0	0
T40	0	60	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	37	0	0
T74	0	76	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	45	0	0
T122	0	128	0	0
T175	0	16	0	0
T275	0	65	0	0
T280	0	76	0	0
T316	0	34	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1417	0	0
T27	152810	0	0	0
T45	127625	0	0	0
T64	0	15	0	0
T79	0	30	0	0
T86	0	16	0	0
T101	0	33	0	0
T132	180449	0	0	0
T133	48796	0	0	0
T153	0	22	0	0
T175	117043	15	0	0
T176	459793	0	0	0
T177	51130	0	0	0
T178	200630	0	0	0
T179	209053	0	0	0
T180	50616	0	0	0
T217	0	21	0	0
T227	0	8	0	0
T317	0	20	0	0
T318	0	5	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1522	0	0
T46	615154	0	0	0
T64	489202	21	0	0
T70	251262	0	0	0
T77	181595	0	0	0
T79	0	21	0	0
T86	0	27	0	0
T101	0	25	0	0
T112	0	4	0	0
T113	206849	0	0	0
T114	59981	0	0	0
T115	51232	0	0	0
T116	329871	0	0	0
T117	45833	0	0	0
T118	105928	0	0	0
T153	0	39	0	0
T217	0	32	0	0
T227	0	1	0	0
T317	0	15	0	0
T318	0	4	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1430	0	0
T27	152810	0	0	0
T45	127625	0	0	0
T64	0	15	0	0
T79	0	23	0	0
T86	0	9	0	0
T101	0	32	0	0
T132	180449	0	0	0
T133	48796	0	0	0
T153	0	21	0	0
T175	117043	9	0	0
T176	459793	0	0	0
T177	51130	0	0	0
T178	200630	0	0	0
T179	209053	0	0	0
T180	50616	0	0	0
T217	0	23	0	0
T227	0	10	0	0
T317	0	43	0	0
T318	0	4	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1485	0	0
T27	152810	0	0	0
T45	127625	0	0	0
T64	0	14	0	0
T79	0	36	0	0
T86	0	8	0	0
T101	0	18	0	0
T112	0	6	0	0
T132	180449	0	0	0
T133	48796	0	0	0
T153	0	32	0	0
T175	117043	8	0	0
T176	459793	0	0	0
T177	51130	0	0	0
T178	200630	0	0	0
T179	209053	0	0	0
T180	50616	0	0	0
T217	0	27	0	0
T317	0	17	0	0
T318	0	13	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4377	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	41	0	0
T40	0	81	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	19	0	0
T74	0	51	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	47	0	0
T122	0	123	0	0
T175	0	6	0	0
T275	0	88	0	0
T280	0	73	0	0
T316	0	24	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4730	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	28	0	0
T40	0	77	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	30	0	0
T74	0	71	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	39	0	0
T122	0	131	0	0
T175	0	20	0	0
T275	0	78	0	0
T280	0	76	0	0
T316	0	26	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4329	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	74	0	0
T40	0	54	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	9	0	0
T74	0	75	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	36	0	0
T122	0	143	0	0
T175	0	25	0	0
T275	0	68	0	0
T280	0	72	0	0
T316	0	51	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4523	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	24	0	0
T40	0	65	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	15	0	0
T74	0	77	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	67	0	0
T122	0	166	0	0
T175	0	15	0	0
T275	0	80	0	0
T280	0	72	0	0
T316	0	54	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4303	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	27	0	0
T40	0	72	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	31	0	0
T74	0	57	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	42	0	0
T122	0	160	0	0
T175	0	21	0	0
T275	0	65	0	0
T280	0	96	0	0
T316	0	41	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4503	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	37	0	0
T40	0	81	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	26	0	0
T74	0	82	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	53	0	0
T122	0	131	0	0
T175	0	30	0	0
T275	0	84	0	0
T280	0	61	0	0
T316	0	48	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4710	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	52	0	0
T40	0	81	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	35	0	0
T74	0	63	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	46	0	0
T122	0	138	0	0
T175	0	23	0	0
T275	0	70	0	0
T280	0	83	0	0
T316	0	45	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4650	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	30	0	0
T40	0	76	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	18	0	0
T74	0	77	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	36	0	0
T122	0	123	0	0
T175	0	11	0	0
T275	0	73	0	0
T280	0	63	0	0
T316	0	30	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	2603	0	0
T8	244989	0	0	0
T9	218549	0	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T20	406597	10	0	0
T40	0	24	0	0
T51	26503	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	45	0	0
T74	0	21	0	0
T75	19227	0	0	0
T88	99190	0	0	0
T94	0	7	0	0
T122	0	41	0	0
T175	0	24	0	0
T264	0	7	0	0
T280	0	6	0	0
T319	0	2	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	2162	0	0
T27	152810	0	0	0
T45	127625	0	0	0
T64	0	51	0	0
T71	0	3	0	0
T79	0	33	0	0
T132	180449	0	0	0
T133	48796	0	0	0
T153	0	13	0	0
T175	117043	13	0	0
T176	459793	0	0	0
T177	51130	0	0	0
T178	200630	0	0	0
T179	209053	0	0	0
T180	50616	0	0	0
T217	0	35	0	0
T227	0	60	0	0
T263	0	8	0	0
T320	0	12	0	0
T321	0	24	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	3293	0	0
T27	152810	0	0	0
T30	0	5	0	0
T45	127625	0	0	0
T64	0	30	0	0
T79	0	32	0	0
T127	0	1	0	0
T132	180449	0	0	0
T133	48796	0	0	0
T153	0	20	0	0
T172	0	7	0	0
T175	117043	4	0	0
T176	459793	0	0	0
T177	51130	0	0	0
T178	200630	0	0	0
T179	209053	0	0	0
T180	50616	0	0	0
T190	0	2	0	0
T217	0	32	0	0
T227	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1464	0	0
T27	152810	0	0	0
T45	127625	0	0	0
T64	0	21	0	0
T79	0	27	0	0
T86	0	15	0	0
T101	0	20	0	0
T132	180449	0	0	0
T133	48796	0	0	0
T153	0	21	0	0
T175	117043	12	0	0
T176	459793	0	0	0
T177	51130	0	0	0
T178	200630	0	0	0
T179	209053	0	0	0
T180	50616	0	0	0
T217	0	36	0	0
T227	0	1	0	0
T317	0	21	0	0
T318	0	4	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4888	0	0
T1	200857	0	0	0
T2	364111	0	0	0
T3	152394	0	0	0
T4	165075	0	0	0
T5	345646	0	0	0
T6	118911	82	0	0
T12	250839	0	0	0
T13	86445	0	0	0
T14	21564	0	0	0
T15	90894	0	0	0
T57	0	82	0	0
T58	0	76	0	0
T64	0	82	0	0
T175	0	64	0	0
T261	0	49	0	0
T263	0	38	0	0
T322	0	93	0	0
T323	0	32	0	0
T324	0	59	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	5558	0	0
T26	217557	0	0	0
T37	158945	0	0	0
T38	78217	0	0	0
T56	251331	0	0	0
T64	0	25	0	0
T79	0	13	0	0
T95	157337	0	0	0
T117	0	82	0	0
T168	103258	86	0	0
T169	101280	0	0	0
T170	245138	0	0	0
T171	53501	0	0	0
T175	117043	103	0	0
T217	0	111	0	0
T227	0	66	0	0
T265	0	72	0	0
T325	0	79	0	0
T326	0	64	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4421	0	0
T26	217557	0	0	0
T37	158945	0	0	0
T38	78217	0	0	0
T56	251331	0	0	0
T64	0	6	0	0
T79	0	24	0	0
T95	157337	0	0	0
T117	0	76	0	0
T168	103258	63	0	0
T169	101280	0	0	0
T170	245138	0	0	0
T171	53501	0	0	0
T175	117043	68	0	0
T217	0	101	0	0
T227	0	79	0	0
T265	0	47	0	0
T325	0	92	0	0
T326	0	70	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	4676	0	0
T26	217557	0	0	0
T37	158945	0	0	0
T38	78217	0	0	0
T56	251331	0	0	0
T64	0	29	0	0
T79	0	24	0	0
T95	157337	0	0	0
T117	0	75	0	0
T168	103258	66	0	0
T169	101280	0	0	0
T170	245138	0	0	0
T171	53501	0	0	0
T175	117043	103	0	0
T217	0	87	0	0
T227	0	84	0	0
T265	0	82	0	0
T325	0	65	0	0
T326	0	64	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1595	0	0
T27	152810	0	0	0
T45	127625	0	0	0
T64	0	23	0	0
T79	0	33	0	0
T86	0	17	0	0
T101	0	39	0	0
T132	180449	0	0	0
T133	48796	0	0	0
T153	0	37	0	0
T175	117043	6	0	0
T176	459793	0	0	0
T177	51130	0	0	0
T178	200630	0	0	0
T179	209053	0	0	0
T180	50616	0	0	0
T217	0	24	0	0
T227	0	2	0	0
T317	0	25	0	0
T318	0	9	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1752	0	0
T7	56848	6	0	0
T8	244989	0	0	0
T9	218549	4	0	0
T19	391266	0	0	0
T20	406597	0	0	0
T30	0	2	0	0
T47	219597	0	0	0
T48	193263	0	0	0
T49	156397	0	0	0
T50	23727	0	0	0
T51	26503	0	0	0
T64	0	22	0	0
T79	0	41	0	0
T97	0	8	0	0
T162	0	1	0	0
T175	0	13	0	0
T307	0	12	0	0
T327	0	7	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1615	0	0
T7	56848	3	0	0
T8	244989	0	0	0
T9	218549	8	0	0
T19	391266	0	0	0
T20	406597	0	0	0
T30	0	7	0	0
T47	219597	0	0	0
T48	193263	0	0	0
T49	156397	0	0	0
T50	23727	0	0	0
T51	26503	0	0	0
T64	0	33	0	0
T79	0	34	0	0
T97	0	3	0	0
T162	0	4	0	0
T175	0	13	0	0
T227	0	5	0	0
T328	0	1	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1717	0	0
T7	56848	2	0	0
T8	244989	0	0	0
T9	218549	1	0	0
T19	391266	0	0	0
T20	406597	0	0	0
T30	0	1	0	0
T47	219597	0	0	0
T48	193263	0	0	0
T49	156397	0	0	0
T50	23727	0	0	0
T51	26503	0	0	0
T64	0	30	0	0
T79	0	39	0	0
T97	0	13	0	0
T175	0	7	0	0
T227	0	9	0	0
T327	0	9	0	0
T328	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131775087	1577	0	0
T9	218549	2	0	0
T10	133890	0	0	0
T11	127483	0	0	0
T24	701046	0	0	0
T40	549471	0	0	0
T60	63072	0	0	0
T61	12980	0	0	0
T64	0	28	0	0
T75	19227	0	0	0
T79	0	38	0	0
T88	99190	0	0	0
T89	45436	0	0	0
T97	0	12	0	0
T153	0	35	0	0
T175	0	14	0	0
T217	0	44	0	0
T307	0	7	0	0
T321	0	4	0	0
T327	0	6	0	0