Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

Module Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_key2_in_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_ac_present_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_ec_rst_l_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_flash_wp_l_h2l

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_pwrb_l2h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_key0_in_l2h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_key1_in_l2h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_key2_in_l2h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_ac_present_l2h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_ec_rst_l_l2h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_key_intr_status_flash_wp_l_l2h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T5,T10,T28
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T5,T10,T35
1	1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T10,T31,T28
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T10,T31,T37
1	1	Covered	T10,T31,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T5,T10,T28
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T5,T10,T38
1	1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_h2l.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T5,T10,T28
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T5,T10,T35
1	1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_pwrb_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T10,T31,T28
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T10,T31,T35
1	1	Covered	T10,T31,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key0_in_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T10,T28,T38
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T10,T38,T39
1	1	Covered	T10,T28,T38

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T38

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key1_in_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T10,T31,T28
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T10,T31,T35
1	1	Covered	T10,T31,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T31,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_key2_in_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T10,T28,T37
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T10,T37,T27
1	1	Covered	T10,T28,T37

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T37

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ac_present_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T5,T10,T28
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T5,T10,T35
1	1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T28

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_ec_rst_l_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T10,T28,T37
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T10,T37,T27
1	1	Covered	T10,T28,T37

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T10,T28,T37

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	88	1	1	100.00
CONT_ASSIGN	110	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg_arb.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
88	1	1
110	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_status_flash_wp_l_l2h.wr_en_data_arb

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       88
 EXPRESSION (we | de)
             -1   -2

-1-	-2-	Status	Tests
0	0	Covered	T6,T1,T2
0	1	Covered	T28,T33,T38
1	0	Covered	T5,T10,T31

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T1,T2
1	0	Covered	T33,T38,T27
1	1	Covered	T28,T33,T38

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T28,T33,T38

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1

-1-	Status	Tests
0	Covered	T6,T1,T2
1	Covered	T5,T10,T31