Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
147 |
1 |
|
|
T28 |
2 |
|
T40 |
1 |
|
T33 |
1 |
auto[1] |
112 |
1 |
|
|
T28 |
1 |
|
T23 |
3 |
|
T40 |
2 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
124 |
1 |
|
|
T40 |
2 |
|
T33 |
3 |
|
T41 |
1 |
auto[1] |
135 |
1 |
|
|
T28 |
3 |
|
T23 |
3 |
|
T40 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
139 |
1 |
|
|
T28 |
1 |
|
T23 |
2 |
|
T40 |
1 |
auto[1] |
120 |
1 |
|
|
T28 |
2 |
|
T23 |
1 |
|
T40 |
2 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
137 |
1 |
|
|
T23 |
1 |
|
T40 |
1 |
|
T33 |
2 |
auto[1] |
122 |
1 |
|
|
T28 |
3 |
|
T23 |
2 |
|
T40 |
2 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
146 |
1 |
|
|
T23 |
1 |
|
T40 |
3 |
|
T33 |
3 |
auto[1] |
113 |
1 |
|
|
T28 |
3 |
|
T23 |
2 |
|
T42 |
3 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
132 |
1 |
|
|
T28 |
1 |
|
T23 |
1 |
|
T41 |
2 |
auto[1] |
127 |
1 |
|
|
T28 |
2 |
|
T23 |
2 |
|
T40 |
3 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
80 |
1 |
|
|
T40 |
1 |
|
T33 |
1 |
|
T42 |
1 |
auto[0] |
auto[1] |
44 |
1 |
|
|
T40 |
1 |
|
T33 |
2 |
|
T41 |
1 |
auto[1] |
auto[0] |
67 |
1 |
|
|
T28 |
2 |
|
T41 |
1 |
|
T38 |
1 |
auto[1] |
auto[1] |
68 |
1 |
|
|
T28 |
1 |
|
T23 |
3 |
|
T40 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
70 |
1 |
|
|
T23 |
1 |
|
T33 |
2 |
|
T42 |
1 |
auto[0] |
auto[1] |
67 |
1 |
|
|
T40 |
1 |
|
T41 |
1 |
|
T73 |
1 |
auto[1] |
auto[0] |
69 |
1 |
|
|
T28 |
1 |
|
T23 |
1 |
|
T40 |
1 |
auto[1] |
auto[1] |
53 |
1 |
|
|
T28 |
2 |
|
T23 |
1 |
|
T40 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
69 |
1 |
|
|
T41 |
2 |
|
T38 |
2 |
|
T73 |
1 |
auto[0] |
auto[1] |
63 |
1 |
|
|
T28 |
1 |
|
T23 |
1 |
|
T44 |
2 |
auto[1] |
auto[0] |
77 |
1 |
|
|
T23 |
1 |
|
T40 |
3 |
|
T33 |
3 |
auto[1] |
auto[1] |
50 |
1 |
|
|
T28 |
2 |
|
T23 |
1 |
|
T42 |
3 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12 |
1 |
|
|
T38 |
1 |
|
T142 |
1 |
|
T175 |
3 |
auto[1] |
26 |
1 |
|
|
T38 |
2 |
|
T43 |
3 |
|
T62 |
3 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
15 |
1 |
|
|
T38 |
3 |
|
T43 |
1 |
|
T94 |
1 |
auto[1] |
23 |
1 |
|
|
T43 |
2 |
|
T62 |
3 |
|
T94 |
2 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20 |
1 |
|
|
T38 |
2 |
|
T43 |
2 |
|
T62 |
2 |
auto[1] |
18 |
1 |
|
|
T38 |
1 |
|
T43 |
1 |
|
T62 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
18 |
1 |
|
|
T38 |
2 |
|
T43 |
2 |
|
T62 |
1 |
auto[1] |
20 |
1 |
|
|
T38 |
1 |
|
T43 |
1 |
|
T62 |
2 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
20 |
1 |
|
|
T38 |
2 |
|
T43 |
2 |
|
T62 |
1 |
auto[1] |
18 |
1 |
|
|
T38 |
1 |
|
T43 |
1 |
|
T62 |
2 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
17 |
1 |
|
|
T38 |
1 |
|
T43 |
3 |
|
T94 |
1 |
auto[1] |
21 |
1 |
|
|
T38 |
2 |
|
T62 |
3 |
|
T94 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
4 |
1 |
|
|
T38 |
1 |
|
T175 |
1 |
|
T155 |
1 |
auto[0] |
auto[1] |
11 |
1 |
|
|
T38 |
2 |
|
T43 |
1 |
|
T94 |
1 |
auto[1] |
auto[0] |
8 |
1 |
|
|
T142 |
1 |
|
T175 |
2 |
|
T351 |
1 |
auto[1] |
auto[1] |
15 |
1 |
|
|
T43 |
2 |
|
T62 |
3 |
|
T94 |
2 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
9 |
1 |
|
|
T38 |
1 |
|
T43 |
1 |
|
T62 |
1 |
auto[0] |
auto[1] |
9 |
1 |
|
|
T38 |
1 |
|
T43 |
1 |
|
T142 |
1 |
auto[1] |
auto[0] |
11 |
1 |
|
|
T38 |
1 |
|
T43 |
1 |
|
T62 |
1 |
auto[1] |
auto[1] |
9 |
1 |
|
|
T62 |
1 |
|
T142 |
1 |
|
T170 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
10 |
1 |
|
|
T43 |
2 |
|
T94 |
1 |
|
T142 |
2 |
auto[0] |
auto[1] |
7 |
1 |
|
|
T38 |
1 |
|
T43 |
1 |
|
T142 |
1 |
auto[1] |
auto[0] |
10 |
1 |
|
|
T38 |
2 |
|
T62 |
1 |
|
T175 |
1 |
auto[1] |
auto[1] |
11 |
1 |
|
|
T62 |
2 |
|
T94 |
2 |
|
T175 |
2 |
Summary for Variable cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
8 |
1 |
|
|
T43 |
2 |
|
T94 |
1 |
|
T68 |
1 |
auto[1] |
11 |
1 |
|
|
T43 |
1 |
|
T94 |
2 |
|
T175 |
1 |
Summary for Variable cp_key0_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
7 |
1 |
|
|
T43 |
2 |
|
T175 |
2 |
|
T102 |
1 |
auto[1] |
12 |
1 |
|
|
T43 |
1 |
|
T94 |
3 |
|
T68 |
1 |
Summary for Variable cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12 |
1 |
|
|
T43 |
1 |
|
T94 |
2 |
|
T175 |
3 |
auto[1] |
7 |
1 |
|
|
T43 |
2 |
|
T94 |
1 |
|
T68 |
1 |
Summary for Variable cp_key1_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11 |
1 |
|
|
T43 |
3 |
|
T94 |
1 |
|
T68 |
1 |
auto[1] |
8 |
1 |
|
|
T94 |
2 |
|
T175 |
1 |
|
T146 |
3 |
Summary for Variable cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_sel
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
12 |
1 |
|
|
T43 |
3 |
|
T175 |
2 |
|
T146 |
3 |
auto[1] |
7 |
1 |
|
|
T94 |
3 |
|
T68 |
1 |
|
T175 |
1 |
Summary for Variable cp_key2_out_value
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out_value
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11 |
1 |
|
|
T43 |
3 |
|
T94 |
1 |
|
T175 |
1 |
auto[1] |
8 |
1 |
|
|
T94 |
2 |
|
T68 |
1 |
|
T175 |
2 |
Summary for Cross cross_key0_out_sel_value
Samples crossed: cp_key0_out_value cp_key0_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key0_out_sel_value
Bins
cp_key0_out_value | cp_key0_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
5 |
1 |
|
|
T43 |
2 |
|
T175 |
2 |
|
T102 |
1 |
auto[0] |
auto[1] |
2 |
1 |
|
|
T155 |
2 |
|
- |
- |
|
- |
- |
auto[1] |
auto[0] |
3 |
1 |
|
|
T94 |
1 |
|
T68 |
1 |
|
T146 |
1 |
auto[1] |
auto[1] |
9 |
1 |
|
|
T43 |
1 |
|
T94 |
2 |
|
T175 |
1 |
Summary for Cross cross_key1_out_sel_value
Samples crossed: cp_key1_out_value cp_key1_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key1_out_sel_value
Bins
cp_key1_out_value | cp_key1_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
7 |
1 |
|
|
T43 |
1 |
|
T175 |
2 |
|
T102 |
2 |
auto[0] |
auto[1] |
4 |
1 |
|
|
T43 |
2 |
|
T94 |
1 |
|
T68 |
1 |
auto[1] |
auto[0] |
5 |
1 |
|
|
T94 |
2 |
|
T175 |
1 |
|
T146 |
2 |
auto[1] |
auto[1] |
3 |
1 |
|
|
T146 |
1 |
|
T102 |
1 |
|
T155 |
1 |
Summary for Cross cross_key2_out_sel_value
Samples crossed: cp_key2_out_value cp_key2_out_sel
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for cross_key2_out_sel_value
Bins
cp_key2_out_value | cp_key2_out_sel | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
auto[0] |
9 |
1 |
|
|
T43 |
3 |
|
T175 |
1 |
|
T146 |
2 |
auto[0] |
auto[1] |
2 |
1 |
|
|
T94 |
1 |
|
T102 |
1 |
|
- |
- |
auto[1] |
auto[0] |
3 |
1 |
|
|
T175 |
1 |
|
T146 |
1 |
|
T155 |
1 |
auto[1] |
auto[1] |
5 |
1 |
|
|
T94 |
2 |
|
T68 |
1 |
|
T175 |
1 |