Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1896

1

T1

58

T5

15

T15

12

auto[1]

543

1

T1

2

T5

5

T17

1

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1834

1

T1

58

T5

20

T15

9

auto[1]

605

1

T1

2

T15

3

T6

9

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1780

1

T1

50

T5

20

T15

9

auto[1]

659

1

T1

10

T15

3

T3

5

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1936

1

T1

39

T5

20

T15

12

auto[1]

503

1

T1

21

T17

1

T3

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2245

1

T1

56

T5

20

T15

12

auto[1]

194

1

T1

4

T3

10

T6

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2225

1

T1

53

T5

15

T15

12

auto[1]

214

1

T1

7

T5

5

T17

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2169

1

T1

54

T5

20

T15

12

auto[1]

270

1

T1

6

T3

3

T6

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2297

1

T1

58

T5

20

T15

12

auto[1]

142

1

T1

2

T3

3

T6

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2285

1

T1

50

T5

20

T15

9

auto[1]

154

1

T1

10

T15

3

T3

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1813

1

T1

60

T5

20

T15

12

auto[1]

626

1

T17

1

T6

4

T7

2

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	897	1			T7	15		T8	22		T10	10
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	48	1			T6	4		T211	2		T66	12
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	42	1			T1	10		T15	3		T263	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	24	1			T196	2		T297	6		T315	8
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	42	1			T211	3		T149	4		T263	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	7	1			T301	2		T316	3		T317	2
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	14	1			T6	5		T318	6		T319	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T320	2		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	56	1			T210	6		T302	10		T263	1
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	36	1			T1	4		T195	1		T321	15
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	30	1			T31	8		T210	3		T314	7
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	8	1			T297	2		T77	6		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	28	1			T1	2		T31	10		T114	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T302	4		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	53	1			T1	7		T17	1		T92	4
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	28	1			T297	18		T322	5		T323	3
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	12	1			T301	2		T314	4		T134	2
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	12	1			T3	10		T324	2		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	8	1			T197	3		T325	3		T326	2
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	2	1			T319	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	45	1			T6	3		T59	14		T263	1
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	8	1			T301	3		T210	2		T327	2
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	2	1			T77	2		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	9	1			T3	3		T64	6		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

132

1

T3

3

T8

10

T31

8

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

95

1

T59

7

T301

3

T44

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

40

1

T306

2

T218

3

T321

12

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T1

11

T3

5

T59

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T6

3

T92

4

T302

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

41

1

T202

4

T200

7

T315

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T17

1

T10

1

T44

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

113

1

T3

5

T301

2

T297

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

51

1

T33

1

T212

7

T263

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

76

1

T10

3

T40

2

T33

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T149

2

T328

4

T303

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

56

1

T1

10

T212

8

T66

6

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

33

1

T7

5

T301

3

T329

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

41

1

T89

1

T212

5

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

16

1

T23

2

T330

2

T331

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

133

1

T8

12

T210

3

T302

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

33

1

T1

2

T332

6

T333

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

77

1

T10

4

T31

5

T195

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T31

5

T93

4

T149

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

27

1

T40

2

T33

1

T297

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T300

1

T334

1

T146

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

36

1

T6

4

T93

3

T321

16

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

17

1

T302

5

T263

1

T329

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

89

1

T15

3

T7

5

T89

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

42

1

T6

5

T7

3

T10

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

20

1

T93

5

T82

8

T335

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

5

1

T219

1

T330

2

T80

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

25

1

T93

4

T196

2

T300

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T202

2

T186

3

T336

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T7

2

T78

2

T217

3

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

7

1

T79

2

T216

2

T337

2

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded