Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	156333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119479

1

T4

1

T1

576

T5

260

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	143452	1			T4	2		T1	495		T5	193
values[0x0]	65930	1			T4	2		T1	449		T5	293
values[0x1]	66430	1			T4	7		T1	465		T5	288

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	126150	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

149662

1

T4

2

T1

699

T5

323

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	804	1			T4	11		T1	7		T5	6
valid_sources[0x01]	948	1			T1	6		T5	2		T15	6
valid_sources[0x02]	1124	1			T1	18		T5	4		T15	6
valid_sources[0x03]	828	1			T1	4		T5	6		T15	3
valid_sources[0x04]	907	1			T1	3		T5	3		T15	3
valid_sources[0x05]	949	1			T1	1		T5	4		T15	4
valid_sources[0x06]	1036	1			T5	6		T15	4		T17	16
valid_sources[0x07]	774	1			T5	2		T15	3		T16	3
valid_sources[0x08]	1014	1			T1	4		T5	6		T15	3
valid_sources[0x09]	915	1			T1	13		T5	1		T15	2
valid_sources[0x0a]	851	1			T1	8		T5	3		T15	1
valid_sources[0x0b]	833	1			T1	2		T5	4		T15	2
valid_sources[0x0c]	812	1			T1	4		T5	3		T15	5
valid_sources[0x0d]	855	1			T5	4		T15	5		T3	4
valid_sources[0x0e]	1378	1			T1	9		T5	1		T15	4
valid_sources[0x0f]	971	1			T1	4		T15	5		T17	5
valid_sources[0x10]	1863	1			T5	2		T15	4		T3	5
valid_sources[0x11]	1646	1			T1	8		T5	1		T15	4
valid_sources[0x12]	1128	1			T1	1		T15	2		T16	2
valid_sources[0x13]	901	1			T1	6		T15	6		T3	3
valid_sources[0x14]	951	1			T1	2		T5	3		T13	1
valid_sources[0x15]	1280	1			T1	11		T5	7		T15	6
valid_sources[0x16]	1043	1			T5	5		T15	5		T3	1
valid_sources[0x17]	2161	1			T1	6		T14	2		T15	9
valid_sources[0x18]	1552	1			T5	5		T15	5		T3	6
valid_sources[0x19]	1059	1			T1	2		T5	2		T15	2
valid_sources[0x1a]	1342	1			T5	4		T15	1		T17	8
valid_sources[0x1b]	829	1			T1	2		T15	3		T3	10
valid_sources[0x1c]	983	1			T5	1		T15	5		T3	3
valid_sources[0x1d]	921	1			T1	1		T5	3		T15	4
valid_sources[0x1e]	1016	1			T1	2		T5	4		T15	6
valid_sources[0x1f]	1036	1			T1	2		T5	2		T15	5
valid_sources[0x20]	1120	1			T1	10		T5	6		T15	5
valid_sources[0x21]	953	1			T1	1		T5	4		T15	4
valid_sources[0x22]	933	1			T1	2		T15	4		T6	4
valid_sources[0x23]	922	1			T5	6		T15	3		T17	17
valid_sources[0x24]	986	1			T1	2		T5	3		T15	6
valid_sources[0x25]	1125	1			T1	6		T15	2		T3	3
valid_sources[0x26]	1213	1			T1	3		T5	5		T15	4
valid_sources[0x27]	1254	1			T5	1		T15	1		T3	3
valid_sources[0x28]	1108	1			T5	4		T15	4		T17	6
valid_sources[0x29]	916	1			T1	22		T5	3		T13	1
valid_sources[0x2a]	984	1			T5	3		T15	1		T3	4
valid_sources[0x2b]	1287	1			T5	6		T15	2		T6	3
valid_sources[0x2c]	970	1			T1	1		T5	1		T15	2
valid_sources[0x2d]	1780	1			T5	1		T15	3		T3	1
valid_sources[0x2e]	791	1			T1	3		T5	6		T15	1
valid_sources[0x2f]	950	1			T1	4		T5	6		T15	2
valid_sources[0x30]	916	1			T1	3		T5	3		T15	3
valid_sources[0x31]	947	1			T1	2		T5	6		T15	4
valid_sources[0x32]	935	1			T1	18		T5	1		T15	2
valid_sources[0x33]	874	1			T1	6		T5	6		T15	2
valid_sources[0x34]	682	1			T1	12		T5	3		T15	3
valid_sources[0x35]	1038	1			T5	5		T17	13		T3	4
valid_sources[0x36]	1849	1			T1	4		T5	3		T15	3
valid_sources[0x37]	909	1			T5	3		T15	3		T6	3
valid_sources[0x38]	919	1			T1	7		T15	4		T21	1
valid_sources[0x39]	1011	1			T1	5		T5	7		T15	3
valid_sources[0x3a]	797	1			T1	2		T5	1		T15	4
valid_sources[0x3b]	1051	1			T1	5		T5	1		T15	2
valid_sources[0x3c]	989	1			T5	1		T15	5		T3	6
valid_sources[0x3d]	1107	1			T1	2		T5	5		T15	3
valid_sources[0x3e]	1112	1			T1	2		T5	9		T15	4
valid_sources[0x3f]	825	1			T1	10		T15	5		T16	2
valid_sources[0x40]	861	1			T1	8		T5	4		T15	3
valid_sources[0x41]	850	1			T1	10		T5	1		T15	1
valid_sources[0x42]	1156	1			T1	1		T5	1		T15	3
valid_sources[0x43]	1006	1			T1	1		T5	8		T15	1
valid_sources[0x44]	2067	1			T5	3		T15	5		T3	1
valid_sources[0x45]	870	1			T1	2		T5	2		T15	2
valid_sources[0x46]	1097	1			T5	4		T15	6		T3	2
valid_sources[0x47]	1040	1			T5	8		T15	4		T6	6
valid_sources[0x48]	998	1			T1	10		T5	1		T15	4
valid_sources[0x49]	1351	1			T1	11		T5	3		T15	4
valid_sources[0x4a]	1020	1			T1	7		T5	1		T15	3
valid_sources[0x4b]	912	1			T1	7		T5	1		T15	4
valid_sources[0x4c]	1963	1			T1	6		T5	2		T15	4
valid_sources[0x4d]	931	1			T1	4		T5	1		T15	1
valid_sources[0x4e]	1141	1			T1	8		T5	6		T15	4
valid_sources[0x4f]	1443	1			T1	5		T5	4		T15	4
valid_sources[0x50]	875	1			T1	2		T5	2		T15	4
valid_sources[0x51]	1760	1			T1	5		T5	1		T15	3
valid_sources[0x52]	1078	1			T1	2		T5	3		T15	4
valid_sources[0x53]	1022	1			T1	11		T5	2		T15	4
valid_sources[0x54]	1636	1			T1	11		T5	4		T15	5
valid_sources[0x55]	811	1			T1	2		T5	3		T15	3
valid_sources[0x56]	1233	1			T1	7		T5	2		T15	3
valid_sources[0x57]	946	1			T1	7		T5	3		T15	4
valid_sources[0x58]	1191	1			T5	3		T15	4		T17	4
valid_sources[0x59]	1000	1			T1	9		T15	1		T3	4
valid_sources[0x5a]	1129	1			T1	9		T15	2		T3	3
valid_sources[0x5b]	968	1			T1	11		T5	4		T15	4
valid_sources[0x5c]	821	1			T5	2		T15	4		T6	3
valid_sources[0x5d]	1022	1			T1	4		T5	2		T15	6
valid_sources[0x5e]	957	1			T1	13		T5	2		T15	4
valid_sources[0x5f]	897	1			T1	11		T5	2		T15	4
valid_sources[0x60]	966	1			T5	9		T15	1		T3	8
valid_sources[0x61]	910	1			T1	2		T5	1		T15	3
valid_sources[0x62]	1944	1			T1	14		T5	10		T15	8
valid_sources[0x63]	986	1			T1	2		T5	6		T15	1
valid_sources[0x64]	1002	1			T1	12		T5	3		T15	2
valid_sources[0x65]	1015	1			T1	5		T5	5		T15	2
valid_sources[0x66]	2204	1			T1	12		T5	2		T15	2
valid_sources[0x67]	1015	1			T5	4		T15	3		T17	9
valid_sources[0x68]	1029	1			T5	1		T15	3		T3	2
valid_sources[0x69]	1778	1			T1	7		T5	4		T15	6
valid_sources[0x6a]	1120	1			T1	6		T5	4		T15	2
valid_sources[0x6b]	839	1			T1	6		T5	1		T15	1
valid_sources[0x6c]	1165	1			T1	27		T5	5		T3	8
valid_sources[0x6d]	963	1			T5	6		T15	4		T3	6
valid_sources[0x6e]	925	1			T1	5		T5	2		T15	4
valid_sources[0x6f]	751	1			T5	4		T15	7		T3	5
valid_sources[0x70]	969	1			T5	2		T15	3		T17	1
valid_sources[0x71]	963	1			T14	2		T15	4		T3	2
valid_sources[0x72]	859	1			T5	4		T15	2		T3	7
valid_sources[0x73]	890	1			T1	6		T5	5		T15	4
valid_sources[0x74]	936	1			T1	4		T15	3		T17	15
valid_sources[0x75]	1161	1			T1	6		T5	3		T15	4
valid_sources[0x76]	1045	1			T1	5		T5	1		T15	5
valid_sources[0x77]	935	1			T1	9		T5	1		T15	4
valid_sources[0x78]	790	1			T1	4		T15	5		T3	2
valid_sources[0x79]	830	1			T1	2		T5	2		T15	3
valid_sources[0x7a]	1714	1			T5	2		T15	4		T3	1
valid_sources[0x7b]	882	1			T1	6		T5	2		T15	1
valid_sources[0x7c]	959	1			T1	3		T5	6		T15	6
valid_sources[0x7d]	937	1			T5	2		T15	2		T3	3
valid_sources[0x7e]	855	1			T1	2		T5	3		T15	1
valid_sources[0x7f]	1923	1			T1	6		T5	2		T15	1
valid_sources[0x80]	805	1			T1	1		T5	4		T15	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63974

1

T1

232

T5

102

T14

2

values[0x0]

all_enables

biggest_size

32432

1

T1

207

T5

94

T15

121

values[0x1]

all_enables

biggest_size

23073

1

T4

1

T1

137

T5

64