Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1229409558	9557	0	0
auto_block_debounce_ctl_rd_A	1229409558	2226	0	0
auto_block_out_ctl_rd_A	1229409558	3144	0	0
com_det_ctl_0_rd_A	1229409558	3923	0	0
com_det_ctl_1_rd_A	1229409558	4498	0	0
com_det_ctl_2_rd_A	1229409558	4073	0	0
com_det_ctl_3_rd_A	1229409558	4147	0	0
com_out_ctl_0_rd_A	1229409558	4847	0	0
com_out_ctl_1_rd_A	1229409558	4684	0	0
com_out_ctl_2_rd_A	1229409558	4953	0	0
com_out_ctl_3_rd_A	1229409558	5081	0	0
com_pre_det_ctl_0_rd_A	1229409558	1771	0	0
com_pre_det_ctl_1_rd_A	1229409558	1700	0	0
com_pre_det_ctl_2_rd_A	1229409558	1738	0	0
com_pre_det_ctl_3_rd_A	1229409558	1824	0	0
com_pre_sel_ctl_0_rd_A	1229409558	5190	0	0
com_pre_sel_ctl_1_rd_A	1229409558	5343	0	0
com_pre_sel_ctl_2_rd_A	1229409558	5189	0	0
com_pre_sel_ctl_3_rd_A	1229409558	5119	0	0
com_sel_ctl_0_rd_A	1229409558	5042	0	0
com_sel_ctl_1_rd_A	1229409558	5348	0	0
com_sel_ctl_2_rd_A	1229409558	5186	0	0
com_sel_ctl_3_rd_A	1229409558	5085	0	0
ec_rst_ctl_rd_A	1229409558	2766	0	0
intr_enable_rd_A	1229409558	2124	0	0
key_intr_ctl_rd_A	1229409558	4624	0	0
key_intr_debounce_ctl_rd_A	1229409558	1765	0	0
key_invert_ctl_rd_A	1229409558	6165	0	0
pin_allowed_ctl_rd_A	1229409558	6251	0	0
pin_out_ctl_rd_A	1229409558	5080	0	0
pin_out_value_rd_A	1229409558	4794	0	0
regwen_rd_A	1229409558	1971	0	0
ulp_ac_debounce_ctl_rd_A	1229409558	1833	0	0
ulp_ctl_rd_A	1229409558	1776	0	0
ulp_lid_debounce_ctl_rd_A	1229409558	1921	0	0
ulp_pwrb_debounce_ctl_rd_A	1229409558	1892	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	9557	0	0
T22	200657	4	0	0
T23	161475	11	0	0
T30	107978	0	0	0
T33	0	21	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T38	0	26	0	0
T40	0	11	0	0
T43	0	18	0	0
T44	0	15	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T61	0	16	0	0
T62	0	21	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T140	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	2226	0	0
T23	161475	21	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	43	0	0
T91	0	14	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	5	0	0
T142	0	9	0	0
T160	0	13	0	0
T189	0	27	0	0
T260	0	3	0	0
T261	0	13	0	0
T262	0	16	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	3144	0	0
T23	161475	19	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	56	0	0
T91	0	8	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	6	0	0
T142	0	22	0	0
T160	0	4	0	0
T189	0	12	0	0
T260	0	10	0	0
T261	0	11	0	0
T262	0	16	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	3923	0	0
T2	71546	0	0	0
T3	780288	43	0	0
T5	783201	26	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	29	0	0
T59	0	60	0	0
T89	0	78	0	0
T93	0	55	0	0
T195	0	30	0	0
T212	0	40	0	0
T219	0	93	0	0
T263	0	12	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4498	0	0
T2	71546	0	0	0
T3	780288	69	0	0
T5	783201	20	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	26	0	0
T59	0	59	0	0
T89	0	64	0	0
T93	0	67	0	0
T195	0	24	0	0
T212	0	43	0	0
T219	0	83	0	0
T263	0	42	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4073	0	0
T2	71546	0	0	0
T3	780288	68	0	0
T5	783201	15	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	27	0	0
T59	0	40	0	0
T89	0	68	0	0
T93	0	73	0	0
T195	0	39	0	0
T212	0	52	0	0
T219	0	87	0	0
T263	0	40	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4147	0	0
T2	71546	0	0	0
T3	780288	73	0	0
T5	783201	21	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	38	0	0
T59	0	60	0	0
T89	0	80	0	0
T93	0	83	0	0
T195	0	45	0	0
T212	0	29	0	0
T219	0	61	0	0
T263	0	9	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4847	0	0
T2	71546	0	0	0
T3	780288	60	0	0
T5	783201	20	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	34	0	0
T59	0	61	0	0
T89	0	74	0	0
T93	0	66	0	0
T195	0	41	0	0
T212	0	64	0	0
T219	0	84	0	0
T263	0	28	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4684	0	0
T2	71546	0	0	0
T3	780288	44	0	0
T5	783201	18	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	12	0	0
T59	0	79	0	0
T89	0	85	0	0
T93	0	60	0	0
T195	0	33	0	0
T212	0	53	0	0
T219	0	71	0	0
T263	0	26	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4953	0	0
T2	71546	0	0	0
T3	780288	78	0	0
T5	783201	21	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	37	0	0
T59	0	86	0	0
T89	0	78	0	0
T93	0	65	0	0
T195	0	52	0	0
T212	0	64	0	0
T219	0	66	0	0
T263	0	23	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5081	0	0
T2	71546	0	0	0
T3	780288	55	0	0
T5	783201	20	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	34	0	0
T59	0	54	0	0
T89	0	62	0	0
T93	0	75	0	0
T195	0	48	0	0
T212	0	25	0	0
T219	0	81	0	0
T263	0	24	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1771	0	0
T23	161475	5	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	18	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T104	0	9	0	0
T123	0	17	0	0
T142	0	20	0	0
T146	0	24	0	0
T189	0	10	0	0
T262	0	9	0	0
T264	0	7	0	0
T265	0	49	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1700	0	0
T23	161475	13	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	32	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T104	0	12	0	0
T123	0	3	0	0
T142	0	7	0	0
T145	0	9	0	0
T146	0	39	0	0
T189	0	21	0	0
T264	0	7	0	0
T265	0	38	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1738	0	0
T23	161475	9	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	24	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T104	0	14	0	0
T123	0	15	0	0
T142	0	24	0	0
T146	0	32	0	0
T189	0	13	0	0
T262	0	3	0	0
T264	0	18	0	0
T265	0	35	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1824	0	0
T23	161475	9	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	34	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	4	0	0
T142	0	16	0	0
T145	0	3	0	0
T146	0	24	0	0
T189	0	3	0	0
T262	0	14	0	0
T264	0	13	0	0
T265	0	32	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5190	0	0
T2	71546	0	0	0
T3	780288	58	0	0
T5	783201	13	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	40	0	0
T59	0	79	0	0
T89	0	81	0	0
T93	0	62	0	0
T195	0	63	0	0
T212	0	50	0	0
T219	0	63	0	0
T263	0	22	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5343	0	0
T2	71546	0	0	0
T3	780288	79	0	0
T5	783201	31	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	25	0	0
T59	0	78	0	0
T89	0	73	0	0
T93	0	77	0	0
T195	0	56	0	0
T212	0	52	0	0
T219	0	77	0	0
T263	0	16	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5189	0	0
T2	71546	0	0	0
T3	780288	70	0	0
T5	783201	12	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	40	0	0
T59	0	75	0	0
T89	0	64	0	0
T93	0	64	0	0
T195	0	50	0	0
T212	0	41	0	0
T219	0	80	0	0
T263	0	17	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5119	0	0
T2	71546	0	0	0
T3	780288	67	0	0
T5	783201	46	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	41	0	0
T59	0	42	0	0
T89	0	81	0	0
T93	0	67	0	0
T195	0	37	0	0
T212	0	54	0	0
T219	0	62	0	0
T263	0	20	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5042	0	0
T2	71546	0	0	0
T3	780288	71	0	0
T5	783201	38	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	23	0	0
T59	0	80	0	0
T89	0	82	0	0
T93	0	64	0	0
T195	0	32	0	0
T212	0	31	0	0
T219	0	66	0	0
T263	0	31	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5348	0	0
T2	71546	0	0	0
T3	780288	68	0	0
T5	783201	5	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	23	0	0
T59	0	56	0	0
T89	0	82	0	0
T93	0	63	0	0
T195	0	45	0	0
T212	0	26	0	0
T219	0	93	0	0
T263	0	16	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5186	0	0
T2	71546	0	0	0
T3	780288	52	0	0
T5	783201	4	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	29	0	0
T59	0	39	0	0
T89	0	64	0	0
T93	0	95	0	0
T195	0	39	0	0
T212	0	39	0	0
T219	0	75	0	0
T263	0	22	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5085	0	0
T2	71546	0	0	0
T3	780288	68	0	0
T5	783201	30	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	29	0	0
T59	0	75	0	0
T89	0	41	0	0
T93	0	48	0	0
T195	0	44	0	0
T212	0	41	0	0
T219	0	62	0	0
T263	0	26	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	2766	0	0
T2	71546	0	0	0
T3	780288	16	0	0
T5	783201	5	0	0
T6	783556	0	0	0
T13	22061	0	0	0
T14	401759	0	0	0
T15	713927	0	0	0
T16	55256	0	0	0
T17	639844	0	0	0
T21	354513	0	0	0
T23	0	25	0	0
T56	0	4	0	0
T59	0	43	0	0
T89	0	13	0	0
T93	0	27	0	0
T195	0	6	0	0
T266	0	2	0	0
T267	0	7	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	2124	0	0
T23	161475	9	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	36	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T142	0	11	0	0
T145	0	6	0	0
T146	0	104	0	0
T189	0	7	0	0
T262	0	20	0	0
T264	0	5	0	0
T265	0	44	0	0
T268	0	16	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4624	0	0
T23	161475	23	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	31	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T122	0	7	0	0
T123	0	7	0	0
T141	0	1	0	0
T142	0	8	0	0
T162	0	4	0	0
T189	0	7	0	0
T262	0	6	0	0
T264	0	8	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1765	0	0
T23	161475	8	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	27	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	2	0	0
T142	0	17	0	0
T145	0	2	0	0
T146	0	42	0	0
T189	0	8	0	0
T262	0	14	0	0
T264	0	16	0	0
T265	0	41	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	6165	0	0
T23	161475	13	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	207	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	54	0	0
T142	0	124	0	0
T189	0	37	0	0
T262	0	11	0	0
T264	0	12	0	0
T269	0	59	0	0
T270	0	80	0	0
T271	0	84	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	6251	0	0
T23	161475	19	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	55	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	174	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	7	0	0
T142	0	187	0	0
T189	0	6	0	0
T262	0	56	0	0
T264	0	7	0	0
T272	0	19	0	0
T273	0	80	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	5080	0	0
T23	161475	18	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	83	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	149	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	7	0	0
T142	0	148	0	0
T189	0	12	0	0
T262	0	74	0	0
T264	0	11	0	0
T272	0	40	0	0
T273	0	74	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	4794	0	0
T23	161475	16	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	51	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	198	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	17	0	0
T142	0	168	0	0
T189	0	8	0	0
T262	0	48	0	0
T264	0	10	0	0
T272	0	39	0	0
T273	0	61	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1971	0	0
T23	161475	31	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T68	0	21	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	8	0	0
T142	0	10	0	0
T145	0	2	0	0
T146	0	28	0	0
T189	0	6	0	0
T262	0	10	0	0
T264	0	13	0	0
T265	0	37	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1833	0	0
T23	161475	35	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T60	0	8	0	0
T68	0	59	0	0
T95	0	12	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	11	0	0
T142	0	8	0	0
T152	0	5	0	0
T189	0	7	0	0
T262	0	5	0	0
T274	0	2	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1776	0	0
T23	161475	15	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T60	0	2	0	0
T68	0	47	0	0
T95	0	11	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	8	0	0
T142	0	5	0	0
T152	0	7	0	0
T160	0	3	0	0
T262	0	13	0	0
T274	0	4	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1921	0	0
T23	161475	14	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T60	0	8	0	0
T68	0	41	0	0
T95	0	6	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	11	0	0
T142	0	8	0	0
T262	0	7	0	0
T264	0	7	0	0
T274	0	6	0	0
T275	0	17	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1229409558	1892	0	0
T23	161475	29	0	0
T30	107978	0	0	0
T36	64167	0	0	0
T37	217991	0	0	0
T52	63048	0	0	0
T53	73207	0	0	0
T54	63081	0	0	0
T60	0	2	0	0
T68	0	37	0	0
T95	0	2	0	0
T98	48751	0	0	0
T99	49343	0	0	0
T103	54114	0	0	0
T123	0	11	0	0
T142	0	14	0	0
T160	0	4	0	0
T189	0	12	0	0
T262	0	2	0	0
T274	0	3	0	0