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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.56 99.27 96.33 100.00 95.51 98.74 99.33 93.71


Total test records in report: 906
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

T443 /workspace/coverage/default/49.sysrst_ctrl_stress_all.3311775565 Jun 28 06:05:35 PM PDT 24 Jun 28 06:05:44 PM PDT 24 7062015828 ps
T444 /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.4085842059 Jun 28 06:05:33 PM PDT 24 Jun 28 06:05:40 PM PDT 24 2518045924 ps
T445 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3416209577 Jun 28 06:05:34 PM PDT 24 Jun 28 06:05:41 PM PDT 24 2465874061 ps
T262 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3204791353 Jun 28 06:04:17 PM PDT 24 Jun 28 06:04:49 PM PDT 24 8803261207 ps
T162 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.2420671478 Jun 28 06:04:20 PM PDT 24 Jun 28 06:04:37 PM PDT 24 4905273972 ps
T446 /workspace/coverage/default/4.sysrst_ctrl_smoke.84775725 Jun 28 06:04:05 PM PDT 24 Jun 28 06:04:12 PM PDT 24 2127178578 ps
T198 /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2379038558 Jun 28 06:04:05 PM PDT 24 Jun 28 06:04:29 PM PDT 24 25856702736 ps
T447 /workspace/coverage/default/25.sysrst_ctrl_smoke.460451126 Jun 28 06:04:47 PM PDT 24 Jun 28 06:04:55 PM PDT 24 2134259941 ps
T215 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.1597994980 Jun 28 06:04:25 PM PDT 24 Jun 28 06:07:32 PM PDT 24 72740886994 ps
T448 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.2978789260 Jun 28 06:05:37 PM PDT 24 Jun 28 06:08:32 PM PDT 24 68424655153 ps
T274 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2414315744 Jun 28 06:04:34 PM PDT 24 Jun 28 06:04:49 PM PDT 24 5724659869 ps
T449 /workspace/coverage/default/11.sysrst_ctrl_smoke.22094284 Jun 28 06:04:19 PM PDT 24 Jun 28 06:04:33 PM PDT 24 2109076498 ps
T450 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1816363656 Jun 28 06:05:44 PM PDT 24 Jun 28 06:05:50 PM PDT 24 2514596828 ps
T142 /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.773990826 Jun 28 06:04:28 PM PDT 24 Jun 28 06:06:51 PM PDT 24 108286754546 ps
T186 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.380258567 Jun 28 06:04:35 PM PDT 24 Jun 28 06:12:46 PM PDT 24 187393398535 ps
T187 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2957854025 Jun 28 06:04:47 PM PDT 24 Jun 28 06:04:59 PM PDT 24 2462249032 ps
T188 /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.671241383 Jun 28 06:05:44 PM PDT 24 Jun 28 06:05:55 PM PDT 24 2117182616 ps
T189 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.241180063 Jun 28 06:04:28 PM PDT 24 Jun 28 06:05:39 PM PDT 24 23896954998 ps
T190 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.3509290793 Jun 28 06:04:58 PM PDT 24 Jun 28 06:05:09 PM PDT 24 2633441446 ps
T71 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1443122054 Jun 28 06:05:09 PM PDT 24 Jun 28 06:07:48 PM PDT 24 239479165558 ps
T122 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.1666969035 Jun 28 06:05:35 PM PDT 24 Jun 28 06:05:49 PM PDT 24 4116981933 ps
T191 /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.1736612546 Jun 28 06:05:09 PM PDT 24 Jun 28 06:05:22 PM PDT 24 2023543677 ps
T175 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.464539452 Jun 28 06:05:40 PM PDT 24 Jun 28 06:06:33 PM PDT 24 36701776445 ps
T451 /workspace/coverage/default/7.sysrst_ctrl_edge_detect.162696318 Jun 28 06:04:15 PM PDT 24 Jun 28 06:04:25 PM PDT 24 4315131542 ps
T452 /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1899902526 Jun 28 06:04:18 PM PDT 24 Jun 28 06:04:31 PM PDT 24 2591027591 ps
T453 /workspace/coverage/default/17.sysrst_ctrl_stress_all.1632620995 Jun 28 06:04:33 PM PDT 24 Jun 28 06:04:51 PM PDT 24 7247625388 ps
T123 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1748691246 Jun 28 06:04:15 PM PDT 24 Jun 28 06:05:13 PM PDT 24 22397381144 ps
T307 /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2162597245 Jun 28 06:05:37 PM PDT 24 Jun 28 06:08:23 PM PDT 24 131732186417 ps
T454 /workspace/coverage/default/26.sysrst_ctrl_smoke.178343417 Jun 28 06:05:00 PM PDT 24 Jun 28 06:05:09 PM PDT 24 2124520070 ps
T455 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.1788670740 Jun 28 06:04:46 PM PDT 24 Jun 28 06:05:03 PM PDT 24 4098059342 ps
T216 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.3691625450 Jun 28 06:05:11 PM PDT 24 Jun 28 06:06:36 PM PDT 24 133923179810 ps
T456 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.3782146804 Jun 28 06:03:42 PM PDT 24 Jun 28 06:03:50 PM PDT 24 2209534381 ps
T457 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3598753396 Jun 28 06:04:53 PM PDT 24 Jun 28 06:05:09 PM PDT 24 7225624987 ps
T264 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1203737308 Jun 28 06:04:18 PM PDT 24 Jun 28 06:05:09 PM PDT 24 16856793604 ps
T458 /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.4222698771 Jun 28 06:04:04 PM PDT 24 Jun 28 06:04:18 PM PDT 24 7805414201 ps
T459 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.2689936270 Jun 28 06:04:19 PM PDT 24 Jun 28 06:04:29 PM PDT 24 2481530403 ps
T303 /workspace/coverage/default/49.sysrst_ctrl_combo_detect.3109149509 Jun 28 06:05:41 PM PDT 24 Jun 28 06:06:04 PM PDT 24 95407631187 ps
T270 /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.228896035 Jun 28 06:05:09 PM PDT 24 Jun 28 06:05:18 PM PDT 24 2481474785 ps
T81 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.1578430233 Jun 28 06:03:48 PM PDT 24 Jun 28 06:09:02 PM PDT 24 126411483530 ps
T460 /workspace/coverage/default/23.sysrst_ctrl_ultra_low_pwr.991260574 Jun 28 06:04:31 PM PDT 24 Jun 28 06:04:42 PM PDT 24 6234435228 ps
T275 /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3756960317 Jun 28 06:05:24 PM PDT 24 Jun 28 06:05:34 PM PDT 24 11233089884 ps
T461 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4024137041 Jun 28 06:05:49 PM PDT 24 Jun 28 06:06:14 PM PDT 24 60853877262 ps
T462 /workspace/coverage/default/24.sysrst_ctrl_smoke.3931924210 Jun 28 06:04:33 PM PDT 24 Jun 28 06:04:43 PM PDT 24 2130842939 ps
T271 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.1497776116 Jun 28 06:04:52 PM PDT 24 Jun 28 06:05:08 PM PDT 24 2487346103 ps
T199 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.531495921 Jun 28 06:05:47 PM PDT 24 Jun 28 06:07:05 PM PDT 24 27331035624 ps
T273 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2191478328 Jun 28 06:04:22 PM PDT 24 Jun 28 06:04:34 PM PDT 24 2524235261 ps
T463 /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.132620236 Jun 28 06:05:35 PM PDT 24 Jun 28 06:05:43 PM PDT 24 2536169144 ps
T464 /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.353306825 Jun 28 06:04:51 PM PDT 24 Jun 28 06:05:02 PM PDT 24 2222664986 ps
T465 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.4132731979 Jun 28 06:05:40 PM PDT 24 Jun 28 06:05:58 PM PDT 24 4168648027 ps
T466 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.589896090 Jun 28 06:04:52 PM PDT 24 Jun 28 06:05:21 PM PDT 24 24101727040 ps
T467 /workspace/coverage/default/42.sysrst_ctrl_smoke.3162328876 Jun 28 06:05:35 PM PDT 24 Jun 28 06:05:47 PM PDT 24 2112462547 ps
T468 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1714566872 Jun 28 06:04:49 PM PDT 24 Jun 28 06:04:58 PM PDT 24 2528108795 ps
T469 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2737855947 Jun 28 06:04:02 PM PDT 24 Jun 28 06:04:07 PM PDT 24 2182326367 ps
T314 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.202666339 Jun 28 06:05:00 PM PDT 24 Jun 28 06:06:07 PM PDT 24 83951149508 ps
T470 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1714391611 Jun 28 06:04:17 PM PDT 24 Jun 28 06:04:24 PM PDT 24 2476164954 ps
T471 /workspace/coverage/default/0.sysrst_ctrl_stress_all.421053431 Jun 28 06:03:48 PM PDT 24 Jun 28 06:04:07 PM PDT 24 7319875804 ps
T472 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1137894402 Jun 28 06:04:36 PM PDT 24 Jun 28 06:04:47 PM PDT 24 4865907314 ps
T473 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.2003425203 Jun 28 06:05:33 PM PDT 24 Jun 28 06:05:38 PM PDT 24 3024408196 ps
T474 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2212592852 Jun 28 06:05:39 PM PDT 24 Jun 28 06:05:51 PM PDT 24 25182401121 ps
T475 /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.411699030 Jun 28 06:05:56 PM PDT 24 Jun 28 06:06:17 PM PDT 24 26343904648 ps
T476 /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.1406682365 Jun 28 06:04:37 PM PDT 24 Jun 28 06:04:53 PM PDT 24 2472862107 ps
T64 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3947621403 Jun 28 06:05:47 PM PDT 24 Jun 28 06:05:58 PM PDT 24 36076740591 ps
T477 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.1555445347 Jun 28 06:04:17 PM PDT 24 Jun 28 06:04:31 PM PDT 24 2610605975 ps
T478 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.4275693417 Jun 28 06:05:37 PM PDT 24 Jun 28 06:05:47 PM PDT 24 3224392565 ps
T479 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.4209269680 Jun 28 06:05:10 PM PDT 24 Jun 28 06:05:22 PM PDT 24 2515714377 ps
T480 /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.206586151 Jun 28 06:04:57 PM PDT 24 Jun 28 06:05:07 PM PDT 24 2040950149 ps
T481 /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.193164191 Jun 28 06:05:36 PM PDT 24 Jun 28 06:05:45 PM PDT 24 3794326835 ps
T334 /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.955427117 Jun 28 06:05:48 PM PDT 24 Jun 28 06:06:22 PM PDT 24 49396076009 ps
T82 /workspace/coverage/default/31.sysrst_ctrl_combo_detect.439329437 Jun 28 06:04:58 PM PDT 24 Jun 28 06:06:06 PM PDT 24 99275172044 ps
T482 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.772524571 Jun 28 06:04:04 PM PDT 24 Jun 28 06:04:17 PM PDT 24 2533159805 ps
T483 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.25033568 Jun 28 06:04:55 PM PDT 24 Jun 28 06:05:07 PM PDT 24 4834852567 ps
T233 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.4228826370 Jun 28 06:05:02 PM PDT 24 Jun 28 06:05:45 PM PDT 24 33251531649 ps
T484 /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3564540011 Jun 28 06:04:02 PM PDT 24 Jun 28 06:04:06 PM PDT 24 2229918624 ps
T128 /workspace/coverage/default/32.sysrst_ctrl_stress_all.2686433394 Jun 28 06:04:57 PM PDT 24 Jun 28 06:05:20 PM PDT 24 11645275678 ps
T69 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.3425487855 Jun 28 06:05:12 PM PDT 24 Jun 28 06:05:23 PM PDT 24 7931866576 ps
T130 /workspace/coverage/default/7.sysrst_ctrl_alert_test.573254545 Jun 28 06:04:17 PM PDT 24 Jun 28 06:04:24 PM PDT 24 2040936199 ps
T131 /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2538293565 Jun 28 06:04:04 PM PDT 24 Jun 28 06:04:12 PM PDT 24 3130961211 ps
T132 /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.751579541 Jun 28 06:05:39 PM PDT 24 Jun 28 06:05:58 PM PDT 24 4938253098 ps
T133 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2900777829 Jun 28 06:05:34 PM PDT 24 Jun 28 06:05:41 PM PDT 24 2479540333 ps
T134 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.1982828968 Jun 28 06:05:47 PM PDT 24 Jun 28 06:08:07 PM PDT 24 57314286609 ps
T135 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3623986612 Jun 28 06:03:59 PM PDT 24 Jun 28 06:04:07 PM PDT 24 2409327669 ps
T136 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4057050242 Jun 28 06:04:02 PM PDT 24 Jun 28 06:04:13 PM PDT 24 2608002536 ps
T137 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1563680624 Jun 28 06:05:46 PM PDT 24 Jun 28 06:06:07 PM PDT 24 24350742803 ps
T144 /workspace/coverage/default/23.sysrst_ctrl_edge_detect.2846137376 Jun 28 06:04:34 PM PDT 24 Jun 28 06:04:46 PM PDT 24 2611669342 ps
T485 /workspace/coverage/default/0.sysrst_ctrl_smoke.3135191876 Jun 28 06:03:38 PM PDT 24 Jun 28 06:03:46 PM PDT 24 2129953616 ps
T486 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.892365402 Jun 28 06:03:42 PM PDT 24 Jun 28 06:03:55 PM PDT 24 2459284862 ps
T487 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.1774932593 Jun 28 06:04:51 PM PDT 24 Jun 28 06:07:55 PM PDT 24 66869712322 ps
T488 /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.4084054409 Jun 28 06:03:48 PM PDT 24 Jun 28 06:03:56 PM PDT 24 11621854077 ps
T489 /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3010751173 Jun 28 06:04:47 PM PDT 24 Jun 28 06:05:03 PM PDT 24 3393216620 ps
T490 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3316124089 Jun 28 06:04:03 PM PDT 24 Jun 28 06:04:19 PM PDT 24 3704477905 ps
T491 /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.39717819 Jun 28 06:04:42 PM PDT 24 Jun 28 06:04:57 PM PDT 24 3041924447 ps
T83 /workspace/coverage/default/6.sysrst_ctrl_stress_all.180648356 Jun 28 06:04:06 PM PDT 24 Jun 28 06:05:30 PM PDT 24 62870815780 ps
T145 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1177119509 Jun 28 06:05:37 PM PDT 24 Jun 28 06:05:55 PM PDT 24 47036067861 ps
T492 /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.3279104726 Jun 28 06:04:53 PM PDT 24 Jun 28 06:05:06 PM PDT 24 2518908509 ps
T493 /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.560994039 Jun 28 06:04:30 PM PDT 24 Jun 28 06:04:40 PM PDT 24 2641474438 ps
T494 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.1642819169 Jun 28 06:04:20 PM PDT 24 Jun 28 06:04:29 PM PDT 24 3355757276 ps
T229 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.2549795069 Jun 28 06:03:47 PM PDT 24 Jun 28 06:04:54 PM PDT 24 22009228804 ps
T251 /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.1388507614 Jun 28 06:05:02 PM PDT 24 Jun 28 06:05:16 PM PDT 24 2217640265 ps
T252 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3568796857 Jun 28 06:05:26 PM PDT 24 Jun 28 06:05:37 PM PDT 24 2610064923 ps
T253 /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.1545143855 Jun 28 06:03:49 PM PDT 24 Jun 28 06:03:57 PM PDT 24 2283522046 ps
T254 /workspace/coverage/default/3.sysrst_ctrl_smoke.760891565 Jun 28 06:04:03 PM PDT 24 Jun 28 06:04:11 PM PDT 24 2136144187 ps
T255 /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.410241324 Jun 28 06:05:37 PM PDT 24 Jun 28 06:05:51 PM PDT 24 2613497183 ps
T256 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3018005898 Jun 28 06:05:46 PM PDT 24 Jun 28 06:06:23 PM PDT 24 25585048632 ps
T257 /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.690449394 Jun 28 06:04:46 PM PDT 24 Jun 28 06:04:56 PM PDT 24 2516687155 ps
T258 /workspace/coverage/default/44.sysrst_ctrl_smoke.828520133 Jun 28 06:05:35 PM PDT 24 Jun 28 06:05:41 PM PDT 24 2127675042 ps
T259 /workspace/coverage/default/5.sysrst_ctrl_alert_test.2289284195 Jun 28 06:04:02 PM PDT 24 Jun 28 06:04:08 PM PDT 24 2035469308 ps
T495 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2626166326 Jun 28 06:04:59 PM PDT 24 Jun 28 06:05:13 PM PDT 24 2669375709 ps
T496 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1923785422 Jun 28 06:05:06 PM PDT 24 Jun 28 06:05:31 PM PDT 24 209715629553 ps
T497 /workspace/coverage/default/35.sysrst_ctrl_smoke.2233234761 Jun 28 06:05:04 PM PDT 24 Jun 28 06:05:13 PM PDT 24 2188242506 ps
T498 /workspace/coverage/default/24.sysrst_ctrl_alert_test.3053574027 Jun 28 06:04:51 PM PDT 24 Jun 28 06:05:00 PM PDT 24 2026392786 ps
T351 /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.1486214509 Jun 28 06:04:16 PM PDT 24 Jun 28 06:05:21 PM PDT 24 24123051481 ps
T217 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.2780112385 Jun 28 06:04:34 PM PDT 24 Jun 28 06:06:57 PM PDT 24 54362301833 ps
T499 /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.690740511 Jun 28 06:04:51 PM PDT 24 Jun 28 06:05:06 PM PDT 24 2465784200 ps
T171 /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.867069127 Jun 28 06:05:35 PM PDT 24 Jun 28 06:06:09 PM PDT 24 43442185815 ps
T500 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1208463972 Jun 28 06:04:16 PM PDT 24 Jun 28 06:04:25 PM PDT 24 3529407489 ps
T501 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3834764644 Jun 28 06:04:21 PM PDT 24 Jun 28 06:05:33 PM PDT 24 24829620612 ps
T502 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.1170257935 Jun 28 06:03:59 PM PDT 24 Jun 28 06:04:02 PM PDT 24 2244244380 ps
T503 /workspace/coverage/default/13.sysrst_ctrl_alert_test.923216231 Jun 28 06:04:21 PM PDT 24 Jun 28 06:04:29 PM PDT 24 2088703122 ps
T504 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.907237440 Jun 28 06:04:04 PM PDT 24 Jun 28 06:04:21 PM PDT 24 4564533371 ps
T505 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1477280781 Jun 28 06:05:00 PM PDT 24 Jun 28 06:05:12 PM PDT 24 2616593540 ps
T506 /workspace/coverage/default/30.sysrst_ctrl_smoke.4116563499 Jun 28 06:05:02 PM PDT 24 Jun 28 06:05:16 PM PDT 24 2111694388 ps
T507 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4118862645 Jun 28 06:05:26 PM PDT 24 Jun 28 06:05:34 PM PDT 24 2074475324 ps
T508 /workspace/coverage/default/36.sysrst_ctrl_smoke.437306053 Jun 28 06:05:12 PM PDT 24 Jun 28 06:05:24 PM PDT 24 2113376350 ps
T509 /workspace/coverage/default/35.sysrst_ctrl_alert_test.2147384150 Jun 28 06:05:07 PM PDT 24 Jun 28 06:05:16 PM PDT 24 2044288401 ps
T510 /workspace/coverage/default/38.sysrst_ctrl_smoke.3311608184 Jun 28 06:05:13 PM PDT 24 Jun 28 06:05:21 PM PDT 24 2130367828 ps
T511 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.2432166978 Jun 28 06:04:22 PM PDT 24 Jun 28 06:04:34 PM PDT 24 3373878508 ps
T512 /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3190297865 Jun 28 06:04:28 PM PDT 24 Jun 28 06:04:43 PM PDT 24 2511789724 ps
T346 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1756628877 Jun 28 06:05:50 PM PDT 24 Jun 28 06:09:23 PM PDT 24 81216236702 ps
T513 /workspace/coverage/default/40.sysrst_ctrl_smoke.3172404375 Jun 28 06:05:21 PM PDT 24 Jun 28 06:05:33 PM PDT 24 2111359227 ps
T514 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1788249093 Jun 28 06:04:21 PM PDT 24 Jun 28 06:04:33 PM PDT 24 2136558727 ps
T515 /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.3109870133 Jun 28 06:04:18 PM PDT 24 Jun 28 06:04:27 PM PDT 24 2480539757 ps
T516 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3848818602 Jun 28 06:05:01 PM PDT 24 Jun 28 06:05:15 PM PDT 24 3284196815 ps
T517 /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.681925703 Jun 28 06:05:12 PM PDT 24 Jun 28 06:05:21 PM PDT 24 2621896839 ps
T518 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.1723037310 Jun 28 06:04:16 PM PDT 24 Jun 28 06:04:25 PM PDT 24 3160409881 ps
T519 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1389153689 Jun 28 06:04:51 PM PDT 24 Jun 28 06:05:05 PM PDT 24 2043645350 ps
T520 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.4080010121 Jun 28 06:05:38 PM PDT 24 Jun 28 06:05:46 PM PDT 24 2659308531 ps
T521 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.1314530408 Jun 28 06:03:49 PM PDT 24 Jun 28 06:03:58 PM PDT 24 2522076808 ps
T170 /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.4213250121 Jun 28 06:04:51 PM PDT 24 Jun 28 06:05:22 PM PDT 24 48447906414 ps
T318 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3892321608 Jun 28 06:05:35 PM PDT 24 Jun 28 06:07:31 PM PDT 24 159846145365 ps
T331 /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.800149606 Jun 28 06:05:54 PM PDT 24 Jun 28 06:08:10 PM PDT 24 55691819538 ps
T522 /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.909549417 Jun 28 06:05:33 PM PDT 24 Jun 28 06:05:41 PM PDT 24 3195273815 ps
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T524 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3070520567 Jun 28 06:05:38 PM PDT 24 Jun 28 06:05:51 PM PDT 24 2789582832 ps
T525 /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.3518885490 Jun 28 06:04:20 PM PDT 24 Jun 28 06:04:30 PM PDT 24 2630761058 ps
T304 /workspace/coverage/default/28.sysrst_ctrl_stress_all.1914751015 Jun 28 06:04:49 PM PDT 24 Jun 28 06:06:08 PM PDT 24 137463813627 ps
T526 /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.4288294267 Jun 28 06:05:09 PM PDT 24 Jun 28 06:05:19 PM PDT 24 3175202214 ps
T315 /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3505756588 Jun 28 06:04:25 PM PDT 24 Jun 28 06:06:10 PM PDT 24 72088774956 ps
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T531 /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2922236152 Jun 28 06:04:55 PM PDT 24 Jun 28 06:05:07 PM PDT 24 2077888731 ps
T84 /workspace/coverage/default/23.sysrst_ctrl_stress_all.3780137611 Jun 28 06:04:37 PM PDT 24 Jun 28 06:13:01 PM PDT 24 181753640812 ps
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T533 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1996440532 Jun 28 06:05:11 PM PDT 24 Jun 28 06:05:20 PM PDT 24 6093702663 ps
T534 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3922634325 Jun 28 06:05:37 PM PDT 24 Jun 28 06:05:46 PM PDT 24 2086215305 ps
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T146 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1582465755 Jun 28 06:05:03 PM PDT 24 Jun 28 06:07:08 PM PDT 24 190113896551 ps
T538 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1667199292 Jun 28 06:05:21 PM PDT 24 Jun 28 06:05:34 PM PDT 24 2508322925 ps
T72 /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.3439090907 Jun 28 06:04:20 PM PDT 24 Jun 28 06:04:35 PM PDT 24 2982178447 ps
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T327 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3053469814 Jun 28 06:05:52 PM PDT 24 Jun 28 06:09:38 PM PDT 24 78911234749 ps
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T541 /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.3815270991 Jun 28 06:05:35 PM PDT 24 Jun 28 06:05:43 PM PDT 24 2460361654 ps
T542 /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1238114909 Jun 28 06:05:21 PM PDT 24 Jun 28 06:13:32 PM PDT 24 1248284106716 ps
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T354 /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2025414459 Jun 28 06:04:43 PM PDT 24 Jun 28 06:05:53 PM PDT 24 510482074474 ps
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T544 /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1449508940 Jun 28 06:04:35 PM PDT 24 Jun 28 06:04:52 PM PDT 24 3181835624 ps
T70 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3971727464 Jun 28 06:04:25 PM PDT 24 Jun 28 06:04:36 PM PDT 24 4490522788 ps
T545 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.635101308 Jun 28 06:04:53 PM PDT 24 Jun 28 06:05:03 PM PDT 24 3741062741 ps
T546 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1799246435 Jun 28 06:04:51 PM PDT 24 Jun 28 06:05:07 PM PDT 24 2511708550 ps
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T550 /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3958881246 Jun 28 06:05:47 PM PDT 24 Jun 28 06:06:47 PM PDT 24 86386677708 ps
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T333 /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1588969550 Jun 28 06:04:43 PM PDT 24 Jun 28 06:05:35 PM PDT 24 71272364247 ps
T551 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.984160418 Jun 28 06:04:04 PM PDT 24 Jun 28 06:04:12 PM PDT 24 5938095354 ps
T335 /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1113527027 Jun 28 06:05:47 PM PDT 24 Jun 28 06:06:28 PM PDT 24 50031274355 ps
T203 /workspace/coverage/default/41.sysrst_ctrl_combo_detect.4212256976 Jun 28 06:05:26 PM PDT 24 Jun 28 06:07:57 PM PDT 24 105125730341 ps
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T553 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.1430140933 Jun 28 06:04:31 PM PDT 24 Jun 28 06:04:42 PM PDT 24 7374127147 ps
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T555 /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.3298905760 Jun 28 06:04:24 PM PDT 24 Jun 28 06:04:43 PM PDT 24 3795425006 ps
T556 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2010762485 Jun 28 06:04:50 PM PDT 24 Jun 28 06:05:05 PM PDT 24 2812454155 ps
T557 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4049596001 Jun 28 06:04:18 PM PDT 24 Jun 28 06:04:27 PM PDT 24 4537330285 ps
T308 /workspace/coverage/default/15.sysrst_ctrl_stress_all.1232663816 Jun 28 06:04:21 PM PDT 24 Jun 28 06:10:46 PM PDT 24 148990711465 ps
T348 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.3014144475 Jun 28 06:05:49 PM PDT 24 Jun 28 06:15:21 PM PDT 24 213511826375 ps
T558 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.1403653869 Jun 28 06:05:13 PM PDT 24 Jun 28 06:05:24 PM PDT 24 2023097068 ps
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T559 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1332111831 Jun 28 06:04:18 PM PDT 24 Jun 28 06:04:28 PM PDT 24 2483467970 ps
T230 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.2285058177 Jun 28 06:04:02 PM PDT 24 Jun 28 06:04:22 PM PDT 24 22071580901 ps
T560 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3658802405 Jun 28 06:04:18 PM PDT 24 Jun 28 06:04:29 PM PDT 24 3069667992 ps
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T562 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.56999585 Jun 28 06:05:55 PM PDT 24 Jun 28 06:06:28 PM PDT 24 38906333518 ps
T563 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.294635425 Jun 28 06:05:24 PM PDT 24 Jun 28 06:05:33 PM PDT 24 2440601015 ps
T564 /workspace/coverage/default/49.sysrst_ctrl_alert_test.1115653964 Jun 28 06:05:49 PM PDT 24 Jun 28 06:06:00 PM PDT 24 2012767139 ps
T312 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1230388158 Jun 28 06:05:37 PM PDT 24 Jun 28 06:11:48 PM PDT 24 134394423081 ps
T565 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3721881951 Jun 28 06:03:42 PM PDT 24 Jun 28 06:03:50 PM PDT 24 2434696205 ps
T566 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1309764238 Jun 28 06:05:35 PM PDT 24 Jun 28 06:06:47 PM PDT 24 25680746913 ps
T567 /workspace/coverage/default/18.sysrst_ctrl_smoke.1647178039 Jun 28 06:04:31 PM PDT 24 Jun 28 06:04:46 PM PDT 24 2113579800 ps
T220 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.2590623716 Jun 28 06:04:57 PM PDT 24 Jun 28 06:05:29 PM PDT 24 64283075748 ps
T568 /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3170902123 Jun 28 06:04:53 PM PDT 24 Jun 28 06:06:28 PM PDT 24 222203882584 ps
T569 /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1529482909 Jun 28 06:05:13 PM PDT 24 Jun 28 06:05:21 PM PDT 24 2622983850 ps
T570 /workspace/coverage/default/18.sysrst_ctrl_alert_test.945271707 Jun 28 06:04:29 PM PDT 24 Jun 28 06:04:41 PM PDT 24 2020613785 ps
T571 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.14025371 Jun 28 06:05:39 PM PDT 24 Jun 28 06:05:54 PM PDT 24 3658641269 ps
T572 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2704926742 Jun 28 06:04:16 PM PDT 24 Jun 28 06:04:29 PM PDT 24 2511333940 ps
T573 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.1035220750 Jun 28 06:04:29 PM PDT 24 Jun 28 06:04:46 PM PDT 24 2462971263 ps
T574 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1404628632 Jun 28 06:04:02 PM PDT 24 Jun 28 06:04:07 PM PDT 24 2538389348 ps
T221 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3648959941 Jun 28 06:04:18 PM PDT 24 Jun 28 06:04:43 PM PDT 24 85228546434 ps
T575 /workspace/coverage/default/39.sysrst_ctrl_smoke.1504863946 Jun 28 06:05:09 PM PDT 24 Jun 28 06:05:18 PM PDT 24 2122071974 ps
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T577 /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.1073306928 Jun 28 06:05:03 PM PDT 24 Jun 28 06:05:12 PM PDT 24 3309402742 ps
T578 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.2484867588 Jun 28 06:04:24 PM PDT 24 Jun 28 06:04:40 PM PDT 24 2211420683 ps
T204 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.1725977630 Jun 28 06:04:19 PM PDT 24 Jun 28 06:06:01 PM PDT 24 69520875247 ps
T579 /workspace/coverage/default/15.sysrst_ctrl_smoke.4184050341 Jun 28 06:04:22 PM PDT 24 Jun 28 06:04:32 PM PDT 24 2131075948 ps
T580 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.765888606 Jun 28 06:05:15 PM PDT 24 Jun 28 06:05:22 PM PDT 24 4906947518 ps
T581 /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1043850750 Jun 28 06:04:25 PM PDT 24 Jun 28 06:04:36 PM PDT 24 2533649710 ps
T582 /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1332339204 Jun 28 06:04:44 PM PDT 24 Jun 28 06:04:57 PM PDT 24 2582099962 ps
T583 /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.4056820488 Jun 28 06:04:15 PM PDT 24 Jun 28 06:04:23 PM PDT 24 2450710083 ps
T584 /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1604331186 Jun 28 06:04:58 PM PDT 24 Jun 28 06:05:11 PM PDT 24 2903347395 ps
T585 /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1801022111 Jun 28 06:04:29 PM PDT 24 Jun 28 06:04:45 PM PDT 24 2613819729 ps
T586 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3791532502 Jun 28 06:04:55 PM PDT 24 Jun 28 06:05:09 PM PDT 24 3240048413 ps
T587 /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.4058402339 Jun 28 06:04:03 PM PDT 24 Jun 28 06:04:09 PM PDT 24 2207980994 ps
T125 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.1172095033 Jun 28 06:04:29 PM PDT 24 Jun 28 06:31:55 PM PDT 24 631095532166 ps
T588 /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.2839069029 Jun 28 06:04:51 PM PDT 24 Jun 28 06:05:05 PM PDT 24 3723873028 ps
T589 /workspace/coverage/default/34.sysrst_ctrl_smoke.625418867 Jun 28 06:05:06 PM PDT 24 Jun 28 06:05:16 PM PDT 24 2119218864 ps
T590 /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.2452219274 Jun 28 06:04:46 PM PDT 24 Jun 28 06:04:54 PM PDT 24 2528976789 ps
T591 /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.537260910 Jun 28 06:03:43 PM PDT 24 Jun 28 06:03:52 PM PDT 24 2619605333 ps
T592 /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.606771042 Jun 28 06:04:43 PM PDT 24 Jun 28 06:04:52 PM PDT 24 3287746179 ps
T593 /workspace/coverage/default/45.sysrst_ctrl_stress_all.3647121469 Jun 28 06:05:37 PM PDT 24 Jun 28 06:06:24 PM PDT 24 15930623487 ps
T205 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.3036537636 Jun 28 06:04:16 PM PDT 24 Jun 28 06:08:44 PM PDT 24 101198570166 ps
T594 /workspace/coverage/default/9.sysrst_ctrl_alert_test.1655201950 Jun 28 06:04:13 PM PDT 24 Jun 28 06:04:20 PM PDT 24 2015794649 ps
T595 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.1650261078 Jun 28 06:05:08 PM PDT 24 Jun 28 06:05:17 PM PDT 24 3090742104 ps
T596 /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1130784754 Jun 28 06:04:14 PM PDT 24 Jun 28 06:04:19 PM PDT 24 3604804782 ps
T597 /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.242068524 Jun 28 06:04:17 PM PDT 24 Jun 28 06:04:25 PM PDT 24 2584847550 ps
T598 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.3175421100 Jun 28 06:04:31 PM PDT 24 Jun 28 06:04:42 PM PDT 24 3720644518 ps
T206 /workspace/coverage/default/27.sysrst_ctrl_stress_all.176338480 Jun 28 06:04:49 PM PDT 24 Jun 28 06:07:22 PM PDT 24 61416619194 ps
T599 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.493665149 Jun 28 06:05:35 PM PDT 24 Jun 28 06:05:42 PM PDT 24 2746469393 ps
T600 /workspace/coverage/default/10.sysrst_ctrl_smoke.2721752528 Jun 28 06:04:18 PM PDT 24 Jun 28 06:04:27 PM PDT 24 2120507063 ps
T347 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1401246882 Jun 28 06:05:50 PM PDT 24 Jun 28 06:07:16 PM PDT 24 61425562284 ps
T601 /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1197023896 Jun 28 06:04:34 PM PDT 24 Jun 28 06:04:47 PM PDT 24 2845192693 ps
T602 /workspace/coverage/default/46.sysrst_ctrl_stress_all.96192385 Jun 28 06:05:37 PM PDT 24 Jun 28 06:06:03 PM PDT 24 14617947269 ps
T603 /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.2634777970 Jun 28 06:05:42 PM PDT 24 Jun 28 06:05:49 PM PDT 24 2631672881 ps
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