Unified Coverage Report :: Module :: sysrst_ctrl_intr

Module : sysrst_ctrl_intr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_intr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_intr	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_intr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.25	100.00	85.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_match_sync	87.50	100.00	50.00			100.00	100.00
u_sysrst_ctrl_intr_o	100.00	100.00	100.00			100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_intr

	Line No.	Total	Covered	Percent
TOTAL		28	28	100.00
CONT_ASSIGN	41	1	1	100.00
CONT_ASSIGN	47	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
ALWAYS	61	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
ALWAYS	78	6	6	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	127	1	1	100.00
CONT_ASSIGN	135	1	1	100.00
CONT_ASSIGN	163	1	1	100.00
CONT_ASSIGN	170	1	1	100.00
CONT_ASSIGN	174	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_intr.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_intr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
41	1	1
47	1	1
49	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
66	1	1
			MISSING_ELSE
74	1	1
78	1	1
79	1	1
80	1	1
81	1	1
82	1	1
83	1	1
			MISSING_ELSE
105	1	1
106	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE
121	1	1
127	1	1
135	1	1
163	1	1
170	1	1
174	1	1

---

Cond Coverage for Module : sysrst_ctrl_intr

	Total	Covered	Percent
Conditions	5	5	100.00
Logical	5	5	100.00
Non-Logical	0	0
Event	0	0

 LINE       74
 EXPRESSION ((aon_req_hold_q == '0) && ((|aon_staging_reqs_q)))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T4,T8,T13
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T2,T3

 LINE       74
 SUB-EXPRESSION (aon_req_hold_q == '0)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T6,T7

---

Branch Coverage for Module : sysrst_ctrl_intr

	Line No.	Total	Covered	Percent
Branches		11	11	100.00
IF	61	4	4	100.00
IF	78	4	4	100.00
IF	105	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_intr.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_intr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	61	if ((!rst_aon_ni))
-2-:	63	if (aon_ld_req)
-3-:	65	if ((|aon_reqs))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	78	if ((!rst_aon_ni))
-2-:	80	if (aon_ld_req)
-3-:	82	if (aon_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	105	if ((!rst_ni))
-2-:	110	if (dst_ack)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
0	0	Covered	T5,T6,T7