Line Coverage for Module :
sysrst_ctrl
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 17 | 100.00 |
CONT_ASSIGN | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 107 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
CONT_ASSIGN | 110 | 1 | 1 | 100.00 |
CONT_ASSIGN | 111 | 1 | 1 | 100.00 |
CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
CONT_ASSIGN | 114 | 1 | 1 | 100.00 |
CONT_ASSIGN | 303 | 1 | 1 | 100.00 |
CONT_ASSIGN | 304 | 1 | 1 | 100.00 |
CONT_ASSIGN | 305 | 1 | 1 | 100.00 |
CONT_ASSIGN | 306 | 1 | 1 | 100.00 |
CONT_ASSIGN | 307 | 1 | 1 | 100.00 |
CONT_ASSIGN | 308 | 1 | 1 | 100.00 |
CONT_ASSIGN | 310 | 1 | 1 | 100.00 |
CONT_ASSIGN | 311 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
68 |
1 |
1 |
106 |
1 |
1 |
107 |
1 |
1 |
108 |
1 |
1 |
109 |
1 |
1 |
110 |
1 |
1 |
111 |
1 |
1 |
113 |
1 |
1 |
114 |
1 |
1 |
303 |
1 |
1 |
304 |
1 |
1 |
305 |
1 |
1 |
306 |
1 |
1 |
307 |
1 |
1 |
308 |
1 |
1 |
310 |
1 |
1 |
311 |
1 |
1 |
Cond Coverage for Module :
sysrst_ctrl
| Total | Covered | Percent |
Conditions | 51 | 49 | 96.08 |
Logical | 51 | 49 | 96.08 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 68
SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
---------1--------- ----------2---------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T5,T17,T67 |
1 | 0 | Covered | T5,T6,T7 |
1 | 1 | Covered | T5,T17,T72 |
LINE 106
EXPRESSION (reg2hw.key_invert_ctl.pwrb_in.q ^ cio_pwrb_in_i)
---------------1--------------- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 107
EXPRESSION (reg2hw.key_invert_ctl.key0_in.q ^ cio_key0_in_i)
---------------1--------------- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 108
EXPRESSION (reg2hw.key_invert_ctl.key1_in.q ^ cio_key1_in_i)
---------------1--------------- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 109
EXPRESSION (reg2hw.key_invert_ctl.key2_in.q ^ cio_key2_in_i)
---------------1--------------- ------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 110
EXPRESSION (reg2hw.key_invert_ctl.ac_present.q ^ cio_ac_present_i)
-----------------1---------------- --------2-------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 111
EXPRESSION (reg2hw.key_invert_ctl.lid_open.q ^ cio_lid_open_i)
----------------1--------------- -------2------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T14,T15 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 303
EXPRESSION (reg2hw.key_invert_ctl.pwrb_out.q ^ pwrb_out_int)
----------------1--------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 304
EXPRESSION (reg2hw.key_invert_ctl.key0_out.q ^ key0_out_int)
----------------1--------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 305
EXPRESSION (reg2hw.key_invert_ctl.key1_out.q ^ key1_out_int)
----------------1--------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 306
EXPRESSION (reg2hw.key_invert_ctl.key2_out.q ^ key2_out_int)
----------------1--------------- ------2-----
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T14 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Covered | T20,T25,T26 |
LINE 307
EXPRESSION (reg2hw.key_invert_ctl.bat_disable.q ^ aon_bat_disable_out_int)
-----------------1----------------- -----------2-----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T1,T2 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Not Covered | |
LINE 308
EXPRESSION (reg2hw.key_invert_ctl.z3_wakeup.q ^ aon_z3_wakeup_out_int)
----------------1---------------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T5,T6,T7 |
0 | 1 | Covered | T7,T3,T27 |
1 | 0 | Covered | T20,T25,T26 |
1 | 1 | Not Covered | |
Toggle Coverage for Module :
sysrst_ctrl
| Total | Covered | Percent |
Totals |
47 |
47 |
100.00 |
Total Bits |
374 |
374 |
100.00 |
Total Bits 0->1 |
187 |
187 |
100.00 |
Total Bits 1->0 |
187 |
187 |
100.00 |
| | | |
Ports |
47 |
47 |
100.00 |
Port Bits |
374 |
374 |
100.00 |
Port Bits 0->1 |
187 |
187 |
100.00 |
Port Bits 1->0 |
187 |
187 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
clk_aon_i |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
rst_ni |
Yes |
Yes |
T1,T2,T16 |
Yes |
T5,T6,T7 |
INPUT |
rst_aon_ni |
Yes |
Yes |
T1,T2,T16 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T15,T18,T20 |
Yes |
T15,T18,T20 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T6,T7,T1 |
INPUT |
tl_i.a_address[31:0] |
Yes |
Yes |
T5,T7,T1 |
Yes |
T5,T7,T1 |
INPUT |
tl_i.a_source[7:0] |
Yes |
Yes |
T5,T6,T14 |
Yes |
T5,T6,T14 |
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T7,T1 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T4,T10,T28 |
Yes |
T4,T10,T28 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T6,T7,T1 |
Yes |
T6,T7,T1 |
OUTPUT |
tl_o.d_user.rsp_intg[5:0] |
Yes |
Yes |
*T5,*T6,*T7 |
Yes |
T5,T6,T7 |
OUTPUT |
tl_o.d_user.rsp_intg[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
tl_o.d_sink |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_source[7:0] |
Yes |
Yes |
T5,T6,T14 |
Yes |
T5,T6,T14 |
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T7,*T1,*T2 |
Yes |
T5,T6,T7 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T5,T17,T59 |
Yes |
T5,T17,T59 |
INPUT |
alert_rx_i[0].ping_n |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_rx_i[0].ping_p |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T5,T6,T7 |
Yes |
T5,T6,T7 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T5,T17,T59 |
Yes |
T5,T17,T59 |
OUTPUT |
wkup_req_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
rst_req_o |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
intr_event_detected_o |
Yes |
Yes |
T2,T3,T10 |
Yes |
T2,T3,T10 |
OUTPUT |
cio_ac_present_i |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
INPUT |
cio_ec_rst_l_i |
Yes |
Yes |
T6,T7,T14 |
Yes |
T6,T7,T14 |
INPUT |
cio_key0_in_i |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
INPUT |
cio_key1_in_i |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
INPUT |
cio_key2_in_i |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
INPUT |
cio_pwrb_in_i |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
INPUT |
cio_lid_open_i |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
INPUT |
cio_flash_wp_l_i |
Yes |
Yes |
T7,T14,T15 |
Yes |
T7,T14,T15 |
INPUT |
cio_bat_disable_o |
Yes |
Yes |
T7,T1,T2 |
Yes |
T7,T1,T2 |
OUTPUT |
cio_flash_wp_l_o |
Yes |
Yes |
T7,T3,T27 |
Yes |
T7,T3,T27 |
OUTPUT |
cio_ec_rst_l_o |
Yes |
Yes |
T6,T7,T1 |
Yes |
T6,T7,T1 |
OUTPUT |
cio_key0_out_o |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
OUTPUT |
cio_key1_out_o |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
OUTPUT |
cio_key2_out_o |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
OUTPUT |
cio_pwrb_out_o |
Yes |
Yes |
T7,T1,T14 |
Yes |
T7,T1,T14 |
OUTPUT |
cio_z3_wakeup_o |
Yes |
Yes |
T7,T20,T25 |
Yes |
T7,T20,T25 |
OUTPUT |
cio_bat_disable_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_flash_wp_l_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_ec_rst_l_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_key0_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_key1_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_key2_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_pwrb_out_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
cio_z3_wakeup_en_o |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
*Tests covering at least one bit in the range
Assert Coverage for Module :
sysrst_ctrl
Assertion Details
AlertKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
BatOEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
BatOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
ECRSTOEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
ECRSTOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
FlashWpOEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
FlashWpOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
FpvSecCmRegWeOnehotCheck_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
60 |
0 |
0 |
T11 |
180546 |
0 |
0 |
0 |
T12 |
55041 |
0 |
0 |
0 |
T13 |
210963 |
0 |
0 |
0 |
T28 |
463508 |
0 |
0 |
0 |
T59 |
859196 |
10 |
0 |
0 |
T68 |
122845 |
0 |
0 |
0 |
T69 |
70557 |
0 |
0 |
0 |
T72 |
101095 |
0 |
0 |
0 |
T73 |
44619 |
0 |
0 |
0 |
T74 |
211426 |
0 |
0 |
0 |
T245 |
0 |
10 |
0 |
0 |
T320 |
0 |
10 |
0 |
0 |
T336 |
0 |
10 |
0 |
0 |
T337 |
0 |
20 |
0 |
0 |
IntrEventOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Key0OEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Key0OKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Key1OEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Key1OKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Key2OEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Key2OKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
OTRstOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
OTWkOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
PwrbOEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
PwrbOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
TlOAReadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
TlODValidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Z3WakeupOEnIsOne_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |
Z3WwakupOKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1083803699 |
1082174431 |
0 |
0 |
T1 |
151807 |
151581 |
0 |
0 |
T2 |
114862 |
114639 |
0 |
0 |
T5 |
46943 |
46875 |
0 |
0 |
T6 |
249929 |
249849 |
0 |
0 |
T7 |
63150 |
63087 |
0 |
0 |
T14 |
115744 |
115661 |
0 |
0 |
T15 |
51066 |
50998 |
0 |
0 |
T16 |
230782 |
230550 |
0 |
0 |
T17 |
50689 |
50599 |
0 |
0 |
T18 |
67586 |
67496 |
0 |
0 |