Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1147771170	10250	0	0
auto_block_debounce_ctl_rd_A	1147771170	2666	0	0
auto_block_out_ctl_rd_A	1147771170	3098	0	0
com_det_ctl_0_rd_A	1147771170	4587	0	0
com_det_ctl_1_rd_A	1147771170	4593	0	0
com_det_ctl_2_rd_A	1147771170	4665	0	0
com_det_ctl_3_rd_A	1147771170	4729	0	0
com_out_ctl_0_rd_A	1147771170	5021	0	0
com_out_ctl_1_rd_A	1147771170	4979	0	0
com_out_ctl_2_rd_A	1147771170	5043	0	0
com_out_ctl_3_rd_A	1147771170	5152	0	0
com_pre_det_ctl_0_rd_A	1147771170	2077	0	0
com_pre_det_ctl_1_rd_A	1147771170	1991	0	0
com_pre_det_ctl_2_rd_A	1147771170	2127	0	0
com_pre_det_ctl_3_rd_A	1147771170	2099	0	0
com_pre_sel_ctl_0_rd_A	1147771170	5198	0	0
com_pre_sel_ctl_1_rd_A	1147771170	5209	0	0
com_pre_sel_ctl_2_rd_A	1147771170	5011	0	0
com_pre_sel_ctl_3_rd_A	1147771170	5065	0	0
com_sel_ctl_0_rd_A	1147771170	5021	0	0
com_sel_ctl_1_rd_A	1147771170	5142	0	0
com_sel_ctl_2_rd_A	1147771170	5180	0	0
com_sel_ctl_3_rd_A	1147771170	5066	0	0
ec_rst_ctl_rd_A	1147771170	3197	0	0
intr_enable_rd_A	1147771170	2817	0	0
key_intr_ctl_rd_A	1147771170	3681	0	0
key_intr_debounce_ctl_rd_A	1147771170	2128	0	0
key_invert_ctl_rd_A	1147771170	5043	0	0
pin_allowed_ctl_rd_A	1147771170	4925	0	0
pin_out_ctl_rd_A	1147771170	4113	0	0
pin_out_value_rd_A	1147771170	4435	0	0
regwen_rd_A	1147771170	2548	0	0
ulp_ac_debounce_ctl_rd_A	1147771170	2334	0	0
ulp_ctl_rd_A	1147771170	2189	0	0
ulp_lid_debounce_ctl_rd_A	1147771170	2279	0	0
ulp_pwrb_debounce_ctl_rd_A	1147771170	2173	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	10250	0	0
T4	236680	2	0	0
T8	49542	0	0	0
T9	347209	0	0	0
T10	754552	11	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	0	20	0	0
T28	0	10	0	0
T34	0	8	0	0
T35	0	2	0	0
T41	0	3	0	0
T59	859196	0	0	0
T61	0	16	0	0
T62	0	11	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T119	0	12	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2666	0	0
T10	754552	52	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	29	0	0
T28	463508	0	0	0
T35	0	26	0	0
T52	0	10	0	0
T56	0	18	0	0
T59	859196	0	0	0
T62	0	49	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T142	0	9	0	0
T177	0	11	0	0
T338	0	1	0	0
T339	0	5	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	3098	0	0
T10	754552	38	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	24	0	0
T28	463508	0	0	0
T35	0	31	0	0
T52	0	20	0	0
T56	0	15	0	0
T59	859196	0	0	0
T62	0	92	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T142	0	11	0	0
T177	0	13	0	0
T338	0	4	0	0
T339	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4587	0	0
T2	114862	54	0	0
T3	0	72	0	0
T9	0	63	0	0
T10	0	50	0	0
T13	0	30	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	11	0	0
T45	0	5	0	0
T47	0	62	0	0
T62	0	30	0	0
T144	0	63	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4593	0	0
T2	114862	52	0	0
T3	0	57	0	0
T9	0	91	0	0
T10	0	27	0	0
T13	0	29	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	19	0	0
T45	0	16	0	0
T47	0	94	0	0
T62	0	52	0	0
T144	0	50	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4665	0	0
T2	114862	88	0	0
T3	0	65	0	0
T9	0	55	0	0
T10	0	48	0	0
T13	0	16	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	12	0	0
T47	0	53	0	0
T62	0	34	0	0
T90	0	64	0	0
T144	0	77	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4729	0	0
T2	114862	68	0	0
T3	0	73	0	0
T9	0	68	0	0
T10	0	41	0	0
T13	0	17	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	19	0	0
T45	0	13	0	0
T47	0	65	0	0
T62	0	28	0	0
T144	0	57	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5021	0	0
T2	114862	40	0	0
T3	0	76	0	0
T9	0	90	0	0
T10	0	25	0	0
T13	0	38	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	12	0	0
T45	0	9	0	0
T47	0	67	0	0
T62	0	41	0	0
T144	0	63	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4979	0	0
T2	114862	78	0	0
T3	0	87	0	0
T9	0	64	0	0
T10	0	39	0	0
T13	0	12	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	21	0	0
T45	0	9	0	0
T47	0	55	0	0
T62	0	21	0	0
T144	0	82	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5043	0	0
T2	114862	62	0	0
T3	0	88	0	0
T9	0	58	0	0
T10	0	46	0	0
T13	0	21	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	18	0	0
T45	0	16	0	0
T47	0	63	0	0
T62	0	45	0	0
T144	0	78	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5152	0	0
T2	114862	79	0	0
T3	0	61	0	0
T9	0	67	0	0
T10	0	29	0	0
T13	0	43	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	15	0	0
T45	0	12	0	0
T47	0	55	0	0
T62	0	33	0	0
T144	0	70	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2077	0	0
T10	754552	32	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	14	0	0
T28	463508	0	0	0
T35	0	11	0	0
T59	859196	0	0	0
T62	0	24	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T184	0	8	0	0
T254	0	5	0	0
T259	0	40	0	0
T340	0	14	0	0
T341	0	12	0	0
T342	0	14	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	1991	0	0
T10	754552	12	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	16	0	0
T28	463508	0	0	0
T35	0	13	0	0
T41	0	1	0	0
T59	859196	0	0	0
T62	0	42	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T254	0	7	0	0
T259	0	21	0	0
T340	0	8	0	0
T341	0	21	0	0
T342	0	13	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2127	0	0
T10	754552	22	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	16	0	0
T28	463508	0	0	0
T35	0	5	0	0
T41	0	7	0	0
T59	859196	0	0	0
T62	0	29	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T184	0	5	0	0
T254	0	18	0	0
T259	0	26	0	0
T340	0	24	0	0
T341	0	21	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2099	0	0
T10	754552	36	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	28	0	0
T28	463508	0	0	0
T35	0	14	0	0
T41	0	4	0	0
T59	859196	0	0	0
T62	0	34	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T184	0	1	0	0
T254	0	16	0	0
T259	0	17	0	0
T340	0	23	0	0
T341	0	16	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5198	0	0
T2	114862	70	0	0
T3	0	74	0	0
T9	0	101	0	0
T10	0	36	0	0
T13	0	24	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	9	0	0
T45	0	17	0	0
T47	0	62	0	0
T62	0	22	0	0
T144	0	59	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5209	0	0
T2	114862	70	0	0
T3	0	65	0	0
T9	0	71	0	0
T10	0	47	0	0
T13	0	36	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	5	0	0
T45	0	9	0	0
T47	0	59	0	0
T62	0	24	0	0
T144	0	85	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5011	0	0
T2	114862	81	0	0
T3	0	47	0	0
T9	0	53	0	0
T10	0	45	0	0
T13	0	11	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	4	0	0
T45	0	7	0	0
T47	0	61	0	0
T62	0	46	0	0
T144	0	82	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5065	0	0
T2	114862	52	0	0
T3	0	74	0	0
T9	0	60	0	0
T10	0	25	0	0
T13	0	33	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	11	0	0
T45	0	7	0	0
T47	0	64	0	0
T62	0	45	0	0
T144	0	67	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5021	0	0
T2	114862	68	0	0
T3	0	63	0	0
T9	0	65	0	0
T10	0	46	0	0
T13	0	21	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	16	0	0
T45	0	3	0	0
T47	0	49	0	0
T62	0	45	0	0
T144	0	82	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5142	0	0
T2	114862	61	0	0
T3	0	61	0	0
T9	0	76	0	0
T10	0	47	0	0
T13	0	9	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	16	0	0
T45	0	9	0	0
T47	0	58	0	0
T62	0	38	0	0
T144	0	60	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5180	0	0
T2	114862	66	0	0
T3	0	83	0	0
T9	0	72	0	0
T10	0	34	0	0
T13	0	15	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	12	0	0
T45	0	14	0	0
T47	0	48	0	0
T62	0	22	0	0
T144	0	67	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5066	0	0
T2	114862	82	0	0
T3	0	75	0	0
T9	0	61	0	0
T10	0	29	0	0
T13	0	21	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T21	15358	0	0	0
T29	620408	0	0	0
T31	103986	0	0	0
T35	0	17	0	0
T45	0	7	0	0
T47	0	63	0	0
T62	0	52	0	0
T144	0	70	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	3197	0	0
T1	151807	0	0	0
T2	114862	37	0	0
T3	0	59	0	0
T6	249929	7	0	0
T7	63150	0	0	0
T9	0	32	0	0
T10	0	47	0	0
T13	0	17	0	0
T14	115744	0	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T35	0	10	0	0
T45	0	13	0	0
T47	0	31	0	0
T62	0	32	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2817	0	0
T10	754552	40	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	34	0	0
T28	463508	0	0	0
T35	0	16	0	0
T59	859196	0	0	0
T62	0	20	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T121	0	10	0	0
T254	0	25	0	0
T259	0	40	0	0
T343	0	22	0	0
T344	0	10	0	0
T345	0	11	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	3681	0	0
T10	754552	40	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	11	0	0
T28	463508	0	0	0
T35	0	12	0	0
T41	0	17	0	0
T59	859196	0	0	0
T62	0	49	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T153	0	1	0	0
T226	0	2	0	0
T254	0	18	0	0
T259	0	25	0	0
T340	0	21	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2128	0	0
T10	754552	16	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	36	0	0
T28	463508	0	0	0
T35	0	13	0	0
T41	0	3	0	0
T59	859196	0	0	0
T62	0	43	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T184	0	4	0	0
T254	0	3	0	0
T259	0	30	0	0
T340	0	25	0	0
T341	0	6	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	5043	0	0
T10	754552	449	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	87	0	0
T28	463508	0	0	0
T35	0	12	0	0
T41	0	52	0	0
T59	859196	0	0	0
T62	0	74	0	0
T66	0	46	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T247	0	55	0	0
T346	0	43	0	0
T347	0	79	0	0
T348	0	50	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4925	0	0
T1	151807	0	0	0
T2	114862	0	0	0
T7	63150	79	0	0
T10	0	111	0	0
T13	0	14	0	0
T14	115744	0	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T35	0	5	0	0
T41	0	95	0	0
T62	0	33	0	0
T349	0	96	0	0
T350	0	71	0	0
T351	0	36	0	0
T352	0	78	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4113	0	0
T1	151807	0	0	0
T2	114862	0	0	0
T7	63150	61	0	0
T10	0	85	0	0
T13	0	5	0	0
T14	115744	0	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T35	0	16	0	0
T41	0	76	0	0
T62	0	40	0	0
T349	0	70	0	0
T350	0	46	0	0
T351	0	41	0	0
T352	0	65	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	4435	0	0
T1	151807	0	0	0
T2	114862	0	0	0
T7	63150	81	0	0
T10	0	139	0	0
T13	0	19	0	0
T14	115744	0	0	0
T15	51066	0	0	0
T16	230782	0	0	0
T17	50689	0	0	0
T18	67586	0	0	0
T19	205430	0	0	0
T20	59955	0	0	0
T35	0	16	0	0
T41	0	93	0	0
T62	0	23	0	0
T349	0	80	0	0
T350	0	36	0	0
T351	0	44	0	0
T352	0	77	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2548	0	0
T10	754552	28	0	0
T11	180546	0	0	0
T12	55041	0	0	0
T13	210963	15	0	0
T28	463508	0	0	0
T35	0	12	0	0
T41	0	8	0	0
T59	859196	0	0	0
T62	0	20	0	0
T68	122845	0	0	0
T72	101095	0	0	0
T73	44619	0	0	0
T74	211426	0	0	0
T184	0	5	0	0
T254	0	22	0	0
T259	0	23	0	0
T340	0	26	0	0
T341	0	11	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2334	0	0
T3	806495	0	0	0
T4	236680	0	0	0
T8	49542	0	0	0
T10	0	30	0	0
T12	0	13	0	0
T13	0	22	0	0
T25	245727	0	0	0
T26	97882	0	0	0
T27	125849	0	0	0
T31	103986	3	0	0
T35	0	11	0	0
T41	0	1	0	0
T58	149486	0	0	0
T60	0	3	0	0
T62	0	48	0	0
T63	20385	0	0	0
T67	48555	0	0	0
T118	0	6	0	0
T146	0	6	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2189	0	0
T3	806495	0	0	0
T4	236680	0	0	0
T8	49542	0	0	0
T10	0	24	0	0
T12	0	9	0	0
T13	0	17	0	0
T25	245727	0	0	0
T26	97882	0	0	0
T27	125849	0	0	0
T31	103986	16	0	0
T35	0	8	0	0
T41	0	6	0	0
T58	149486	0	0	0
T60	0	4	0	0
T62	0	37	0	0
T63	20385	0	0	0
T67	48555	0	0	0
T118	0	7	0	0
T146	0	2	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2279	0	0
T3	806495	0	0	0
T4	236680	0	0	0
T8	49542	0	0	0
T10	0	35	0	0
T12	0	8	0	0
T13	0	17	0	0
T25	245727	0	0	0
T26	97882	0	0	0
T27	125849	0	0	0
T31	103986	18	0	0
T35	0	10	0	0
T41	0	6	0	0
T58	149486	0	0	0
T60	0	1	0	0
T62	0	27	0	0
T63	20385	0	0	0
T67	48555	0	0	0
T146	0	13	0	0
T353	0	4	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1147771170	2173	0	0
T3	806495	0	0	0
T4	236680	0	0	0
T8	49542	0	0	0
T10	0	36	0	0
T12	0	3	0	0
T13	0	13	0	0
T25	245727	0	0	0
T26	97882	0	0	0
T27	125849	0	0	0
T31	103986	5	0	0
T35	0	15	0	0
T58	149486	0	0	0
T60	0	7	0	0
T62	0	45	0	0
T63	20385	0	0	0
T67	48555	0	0	0
T118	0	5	0	0
T121	0	1	0	0
T146	0	12	0	0