Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
90.24	90.24	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	90.24	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.24	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	8	54	87.10

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	8	23	74.19	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1918

1

T2

6

T7

9

T11

8

auto[1]

677

1

T2

12

T7

2

T31

10

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1956

1

T7

11

T11

7

T31

10

auto[1]

639

1

T2

18

T11

1

T31

12

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1942

1

T2

12

T7

9

T11

8

auto[1]

653

1

T2

6

T7

2

T31

2

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2025

1

T2

12

T7

9

T11

6

auto[1]

570

1

T2

6

T7

2

T11

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2405

1

T2

18

T7

11

T11

7

auto[1]

190

1

T11

1

T44

3

T42

28

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2392

1

T2

18

T7

11

T11

8

auto[1]

203

1

T41

3

T42

2

T246

6

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2419

1

T2

18

T7

11

T11

7

auto[1]

176

1

T11

1

T43

21

T44

3

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2385

1

T2

18

T7

11

T11

8

auto[1]

210

1

T69

3

T42

2

T70

8

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2350

1

T2

18

T7

11

T11

7

auto[1]

245

1

T11

1

T43

8

T69

3

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1978

1

T2

16

T11

7

T31

14

auto[1]

617

1

T2

2

T7

11

T11

1

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	8	23	74.19	8
Automatically Generated Cross Bins	31	8	23	74.19	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	*	[auto[1]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

888

1

T2

18

T7

11

T31

22

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

72

1

T11

1

T244

2

T75

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

79

1

T243

10

T247

6

T352

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

35

1

T42

28

T246

4

T353

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

53

1

T70

1

T241

10

T244

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

17

1

T70

1

T247

1

T75

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

24

1

T236

7

T354

1

T345

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T239

2

T355

4

T356

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T43

13

T257

5

T357

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T44

3

T235

2

T351

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

30

1

T11

1

T43

8

T242

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10

1

T358

4

T350

5

T359

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T360

1

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

17

1

T69

3

T242

4

T355

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

71

1

T41

3

T242

22

T352

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T247

5

T361

4

T352

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

19

1

T247

6

T362

3

T236

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

32

1

T241

8

T362

2

T349

4

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

2

1

T354

1

T363

1

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

25

1

T246

6

T245

2

T364

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T365

3

T217

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

5

1

T366

5

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T42

2

T367

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

133

1

T37

12

T107

8

T69

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

108

1

T7

9

T44

3

T42

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

49

1

T31

8

T254

1

T364

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

106

1

T11

1

T33

8

T259

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

53

1

T246

6

T357

2

T260

5

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

47

1

T43

13

T247

5

T352

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

40

1

T242

11

T362

5

T368

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

109

1

T87

5

T42

28

T242

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

68

1

T37

6

T41

3

T319

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

61

1

T107

4

T241

18

T49

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

22

1

T105

3

T244

3

T342

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

60

1

T258

3

T352

4

T245

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T31

2

T32

6

T248

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T87

1

T259

8

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T7

2

T32

3

T87

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

78

1

T31

12

T43

8

T246

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

40

1

T2

12

T110

5

T242

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

75

1

T320

4

T258

5

T244

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

34

1

T105

1

T257

4

T248

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T33

4

T242

5

T349

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T37

4

T110

2

T247

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

26

1

T11

1

T32

5

T107

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T235

2

T369

6

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

53

1

T32

5

T108

3

T110

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

64

1

T70

1

T49

4

T257

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T105

3

T110

3

T70

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T342

2

T370

1

T343

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

25

1

T2

4

T243

5

T342

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

13

1

T33

1

T182

1

T371

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T2

2

T105

2

T319

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T341

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded