Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T3

14

T21

10

T22

9

auto[1]

1049

1

T3

6

T21

10

T22

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

505

1

T3

6

T21

5

T22

5

from_0to1

510

1

T3

5

T21

4

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T3

9

T21

10

T22

9

auto[1]

992

1

T3

11

T21

10

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T3

10

T21

10

T22

10

auto[1]

1038

1

T3

10

T21

10

T22

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T3

2

T34

3

T386

3

auto[0]

from_1to0

auto[0]

auto[1]

80

1

T386

1

T318

1

T50

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T3

1

T21

1

T22

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T34

1

T50

3

T123

2

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T21

1

T22

2

T34

2

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T3

1

T21

1

T22

1

auto[0]

from_0to1

auto[1]

auto[0]

73

1

T3

1

T21

1

T22

1

auto[0]

from_0to1

auto[1]

auto[1]

53

1

T3

2

T318

1

T50

1

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T66

1

T34

2

T206

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T3

1

T21

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

70

1

T3

2

T21

3

T22

2

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T22

1

T34

3

T206

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T3

1

T21

1

T34

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T22

1

T34

2

T206

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T34

3

T206

1

T386

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T34

1

T386

3

T318

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

989

1

T3

7

T21

8

T22

11

auto[1]

1091

1

T3

13

T21

12

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

494

1

T3

5

T21

5

T22

3

from_0to1

490

1

T3

6

T21

6

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009

1

T3

8

T21

10

T22

7

auto[1]

1071

1

T3

12

T21

10

T22

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1055

1

T3

9

T21

9

T22

11

auto[1]

1025

1

T3

11

T21

11

T22

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T3

1

T22

1

T66

2

auto[0]

from_1to0

auto[0]

auto[1]

49

1

T3

1

T21

2

T386

1

auto[0]

from_1to0

auto[1]

auto[0]

66

1

T206

1

T50

3

T387

2

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T21

2

T22

2

T66

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T66

1

T34

2

T50

3

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T3

1

T21

1

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T22

2

T66

1

T34

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T3

2

T66

1

T34

3

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T3

1

T34

4

T318

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T34

2

T206

1

T50

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T3

1

T34

2

T206

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T3

1

T21

1

T66

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T3

2

T21

2

T22

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T66

1

T34

1

T206

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T21

1

T66

1

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

60

1

T3

1

T21

2

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1057

1

T3

12

T21

9

T22

11

auto[1]

1023

1

T3

8

T21

11

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T3

5

T21

4

T22

5

from_0to1

498

1

T3

4

T21

4

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1037

1

T3

9

T21

8

T22

8

auto[1]

1043

1

T3

11

T21

12

T22

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T3

11

T21

9

T22

6

auto[1]

1044

1

T3

9

T21

11

T22

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

46

1

T21

1

T22

1

T66

1

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T3

3

T66

1

T34

3

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T22

1

T66

1

T206

1

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T66

1

T34

1

T206

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T3

2

T21

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

67

1

T22

1

T34

1

T206

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T21

1

T66

2

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T3

1

T22

1

T34

3

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T34

2

T206

1

T386

1

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T21

1

T22

1

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T3

2

T22

1

T206

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T21

2

T22

1

T34

2

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T34

1

T386

1

T50

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T3

1

T21

1

T22

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T206

1

T318

1

T50

1

auto[1]

from_0to1

auto[1]

auto[1]

53

1

T21

1

T22

1

T50

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1041

1

T3

12

T21

9

T22

9

auto[1]

1039

1

T3

8

T21

11

T22

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T3

6

T21

6

T22

1

from_0to1

509

1

T3

6

T21

7

T22

1

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T3

7

T21

11

T22

9

auto[1]

1027

1

T3

13

T21

9

T22

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T3

11

T21

7

T22

12

auto[1]

1053

1

T3

9

T21

13

T22

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T66

1

T34

1

T318

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T21

1

T34

1

T50

3

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T21

1

T66

1

T34

1

auto[0]

from_1to0

auto[1]

auto[1]

61

1

T3

2

T21

1

T34

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T3

2

T66

3

T34

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T21

1

T22

1

T34

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T3

1

T21

2

T66

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T3

1

T34

2

T206

3

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T66

1

T386

1

T50

1

auto[1]

from_1to0

auto[0]

auto[1]

71

1

T3

1

T21

2

T34

2

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T3

2

T22

1

T66

2

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T3

1

T21

1

T34

4

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T3

1

T21

1

T318

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T21

3

T34

1

T50

3

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T3

1

T66

1

T34

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T34

3

T386

1

T50

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1083

1

T3

11

T21

11

T22

9

auto[1]

997

1

T3

9

T21

9

T22

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T3

5

T21

4

T22

3

from_0to1

496

1

T3

4

T21

4

T22

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T3

10

T21

9

T22

10

auto[1]

1059

1

T3

10

T21

11

T22

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T3

12

T21

11

T22

8

auto[1]

1045

1

T3

8

T21

9

T22

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

51

1

T66

1

T34

1

T386

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T3

1

T21

1

T206

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T3

2

T21

2

T22

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T34

2

T386

2

T50

1

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T3

2

T21

1

T66

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T22

1

T66

1

T50

2

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T3

1

T66

1

T34

1

auto[0]

from_0to1

auto[1]

auto[1]

76

1

T21

2

T22

1

T66

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T3

1

T22

1

T34

1

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T22

1

T66

2

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T3

1

T21

1

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T34

1

T318

1

T50

3

auto[1]

from_0to1

auto[0]

auto[0]

62

1

T34

2

T206

1

T386

1

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T22

1

T34

1

T50

2

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T21

1

T34

2

T386

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T3

1

T34

1

T206

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1009

1

T3

8

T21

11

T22

7

auto[1]

1071

1

T3

12

T21

9

T22

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T3

3

T21

8

T22

5

from_0to1

514

1

T3

4

T21

8

T22

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T3

7

T21

11

T22

8

auto[1]

1040

1

T3

13

T21

9

T22

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1061

1

T3

8

T21

9

T22

11

auto[1]

1019

1

T3

12

T21

11

T22

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T21

2

T66

1

T318

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T21

1

T22

1

T206

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T21

1

T22

1

T66

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T3

1

T21

1

T34

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T3

1

T66

1

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T21

2

T34

3

T206

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T21

1

T34

2

T318

1

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T21

2

T66

1

T386

2

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T22

1

T66

1

T34

1

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T21

1

T34

2

T206

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T3

1

T21

1

T34

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T3

1

T21

1

T22

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T21

1

T22

1

T318

1

auto[1]

from_0to1

auto[0]

auto[1]

63

1

T3

1

T22

2

T34

2

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T3

1

T21

2

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T3

1

T66

1

T34

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T3

9

T21

10

T22

11

auto[1]

1037

1

T3

11

T21

10

T22

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T3

6

T21

5

T22

6

from_0to1

494

1

T3

5

T21

5

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T3

10

T21

7

T22

10

auto[1]

1053

1

T3

10

T21

13

T22

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1058

1

T3

8

T21

8

T22

8

auto[1]

1022

1

T3

12

T21

12

T22

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T22

2

T66

2

T206

1

auto[0]

from_1to0

auto[0]

auto[1]

47

1

T3

2

T21

1

T22

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T21

1

T66

1

T34

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T3

1

T22

1

T34

2

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T34

3

T386

2

T50

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T21

1

T22

1

T66

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T34

2

T50

1

T388

1

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T3

1

T22

1

T66

2

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T3

2

T34

2

T206

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T3

1

T21

2

T34

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T21

1

T66

1

T34

2

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T22

2

T34

1

T388

2

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T3

2

T206

1

T386

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T22

1

T66

1

T34

1

auto[1]

from_0to1

auto[1]

auto[0]

72

1

T3

1

T21

2

T22

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T3

1

T21

2

T22

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1036

1

T3

11

T21

11

T22

10

auto[1]

1044

1

T3

9

T21

9

T22

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

485

1

T3

6

T21

4

T22

5

from_0to1

486

1

T3

5

T21

4

T22

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T3

5

T21

9

T22

10

auto[1]

1015

1

T3

15

T21

11

T22

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T3

7

T21

11

T22

15

auto[1]

1050

1

T3

13

T21

9

T22

5

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T21

1

T22

1

T34

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T21

1

T22

3

T66

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T3

2

T21

1

T66

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T3

3

T34

3

T206

1

auto[0]

from_0to1

auto[0]

auto[0]

71

1

T21

1

T22

2

T34

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T3

1

T206

1

T386

2

auto[0]

from_0to1

auto[1]

auto[0]

56

1

T22

1

T66

1

T50

2

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T34

2

T386

1

T50

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T34

4

T386

2

T318

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T386

1

T318

1

T50

3

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T3

1

T22

1

T66

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T21

1

T318

1

T50

3

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T66

1

T34

2

T206

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T3

2

T21

1

T34

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T3

1

T21

1

T22

2

auto[1]

from_0to1

auto[1]

auto[1]

74

1

T3

1

T21

1

T66

2