Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150881	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

115574

1

T1

18

T4

8

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	136043	1			T1	18		T4	2		T5	3
values[0x0]	64870	1			T1	4		T4	9		T5	1
values[0x1]	65542	1			T1	7		T4	8		T5	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	122199	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

144256

1

T1

18

T4

10

T5

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	875	1			T2	3		T26	5		T7	3
valid_sources[0x01]	889	1			T26	4		T7	7		T27	1
valid_sources[0x02]	1113	1			T2	2		T26	1		T7	1
valid_sources[0x03]	776	1			T2	1		T26	1		T7	1
valid_sources[0x04]	783	1			T2	1		T7	1		T27	1
valid_sources[0x05]	2216	1			T14	2		T7	4		T27	1
valid_sources[0x06]	854	1			T2	2		T3	7		T26	2
valid_sources[0x07]	1849	1			T2	1		T26	1		T7	2
valid_sources[0x08]	985	1			T2	8		T26	3		T7	1
valid_sources[0x09]	1218	1			T2	6		T7	2		T11	3
valid_sources[0x0a]	856	1			T2	4		T21	11		T26	4
valid_sources[0x0b]	1762	1			T2	4		T7	2		T27	2
valid_sources[0x0c]	967	1			T14	1		T26	5		T7	4
valid_sources[0x0d]	1490	1			T26	3		T7	7		T27	2
valid_sources[0x0e]	1228	1			T2	6		T26	1		T7	3
valid_sources[0x0f]	795	1			T2	9		T26	1		T7	2
valid_sources[0x10]	886	1			T26	3		T7	5		T27	5
valid_sources[0x11]	770	1			T3	3		T14	1		T7	1
valid_sources[0x12]	1052	1			T26	2		T7	1		T27	2
valid_sources[0x13]	926	1			T26	3		T7	5		T27	1
valid_sources[0x14]	946	1			T2	3		T26	2		T7	1
valid_sources[0x15]	916	1			T26	2		T7	3		T27	3
valid_sources[0x16]	847	1			T2	6		T14	2		T26	6
valid_sources[0x17]	827	1			T26	3		T7	8		T10	1
valid_sources[0x18]	880	1			T7	2		T59	1		T11	2
valid_sources[0x19]	919	1			T26	3		T7	1		T27	2
valid_sources[0x1a]	828	1			T2	10		T26	5		T7	9
valid_sources[0x1b]	1049	1			T2	2		T3	10		T27	3
valid_sources[0x1c]	981	1			T26	1		T7	5		T27	1
valid_sources[0x1d]	1124	1			T26	1		T7	3		T9	1
valid_sources[0x1e]	1086	1			T2	1		T26	3		T7	1
valid_sources[0x1f]	1018	1			T2	7		T7	5		T27	1
valid_sources[0x20]	816	1			T4	1		T3	9		T26	2
valid_sources[0x21]	978	1			T2	1		T26	2		T7	2
valid_sources[0x22]	2764	1			T2	1		T14	1		T21	7
valid_sources[0x23]	911	1			T2	1		T7	2		T27	2
valid_sources[0x24]	821	1			T2	4		T7	2		T27	1
valid_sources[0x25]	949	1			T2	1		T26	2		T7	3
valid_sources[0x26]	943	1			T26	1		T7	1		T27	3
valid_sources[0x27]	1039	1			T2	8		T7	3		T54	2
valid_sources[0x28]	888	1			T2	3		T26	3		T7	1
valid_sources[0x29]	1060	1			T2	2		T26	2		T27	2
valid_sources[0x2a]	2001	1			T2	4		T7	1		T27	1
valid_sources[0x2b]	814	1			T3	20		T26	1		T7	4
valid_sources[0x2c]	906	1			T4	1		T2	1		T26	1
valid_sources[0x2d]	1046	1			T3	103		T7	2		T11	7
valid_sources[0x2e]	1006	1			T2	7		T26	4		T7	1
valid_sources[0x2f]	903	1			T2	1		T26	6		T7	1
valid_sources[0x30]	992	1			T2	5		T26	2		T7	6
valid_sources[0x31]	999	1			T2	9		T26	1		T7	1
valid_sources[0x32]	885	1			T2	2		T26	2		T7	1
valid_sources[0x33]	1180	1			T2	5		T26	1		T7	3
valid_sources[0x34]	1017	1			T4	2		T2	1		T26	1
valid_sources[0x35]	1026	1			T2	2		T26	3		T27	3
valid_sources[0x36]	793	1			T26	2		T7	4		T9	4
valid_sources[0x37]	1211	1			T4	1		T2	5		T14	1
valid_sources[0x38]	996	1			T2	6		T26	5		T7	2
valid_sources[0x39]	942	1			T1	29		T26	3		T7	6
valid_sources[0x3a]	917	1			T5	5		T2	3		T14	1
valid_sources[0x3b]	1937	1			T2	1		T26	3		T7	5
valid_sources[0x3c]	755	1			T2	12		T26	1		T7	4
valid_sources[0x3d]	1418	1			T2	1		T7	3		T11	4
valid_sources[0x3e]	1130	1			T14	1		T26	1		T7	3
valid_sources[0x3f]	881	1			T4	1		T2	1		T7	4
valid_sources[0x40]	825	1			T14	2		T26	2		T7	1
valid_sources[0x41]	1029	1			T15	1		T26	2		T7	1
valid_sources[0x42]	1051	1			T2	3		T26	3		T7	3
valid_sources[0x43]	1149	1			T26	2		T7	3		T11	5
valid_sources[0x44]	883	1			T2	6		T7	1		T27	3
valid_sources[0x45]	854	1			T26	5		T7	1		T10	1
valid_sources[0x46]	917	1			T2	1		T7	2		T27	3
valid_sources[0x47]	1282	1			T2	2		T27	3		T11	5
valid_sources[0x48]	934	1			T2	5		T26	2		T7	6
valid_sources[0x49]	1031	1			T26	1		T7	2		T11	5
valid_sources[0x4a]	955	1			T26	1		T7	3		T9	1
valid_sources[0x4b]	861	1			T26	3		T7	3		T27	3
valid_sources[0x4c]	877	1			T4	1		T2	9		T26	3
valid_sources[0x4d]	867	1			T2	1		T3	2		T6	45
valid_sources[0x4e]	966	1			T2	1		T3	7		T7	4
valid_sources[0x4f]	984	1			T2	3		T13	12		T26	1
valid_sources[0x50]	899	1			T7	2		T27	3		T11	2
valid_sources[0x51]	918	1			T26	1		T11	3		T20	3
valid_sources[0x52]	980	1			T14	1		T7	2		T9	2
valid_sources[0x53]	914	1			T2	6		T3	20		T26	1
valid_sources[0x54]	816	1			T2	4		T7	3		T27	2
valid_sources[0x55]	1027	1			T26	3		T7	1		T27	2
valid_sources[0x56]	864	1			T2	3		T26	1		T59	1
valid_sources[0x57]	718	1			T2	2		T21	4		T7	5
valid_sources[0x58]	818	1			T26	3		T7	8		T11	1
valid_sources[0x59]	1579	1			T2	12		T14	4		T21	4
valid_sources[0x5a]	949	1			T2	8		T26	3		T7	1
valid_sources[0x5b]	2277	1			T2	9		T21	11		T26	2
valid_sources[0x5c]	1673	1			T7	1		T9	2		T27	2
valid_sources[0x5d]	1130	1			T26	3		T7	2		T9	1
valid_sources[0x5e]	951	1			T2	5		T26	3		T7	4
valid_sources[0x5f]	893	1			T3	11		T14	1		T11	6
valid_sources[0x60]	1833	1			T2	1		T26	2		T7	1
valid_sources[0x61]	847	1			T2	2		T26	2		T7	4
valid_sources[0x62]	986	1			T2	2		T26	5		T7	4
valid_sources[0x63]	895	1			T26	1		T7	1		T27	1
valid_sources[0x64]	791	1			T2	1		T26	1		T7	1
valid_sources[0x65]	1038	1			T2	5		T26	1		T7	4
valid_sources[0x66]	1424	1			T26	2		T7	3		T11	3
valid_sources[0x67]	922	1			T7	3		T27	2		T11	6
valid_sources[0x68]	1520	1			T2	2		T26	2		T7	2
valid_sources[0x69]	860	1			T2	4		T26	4		T7	3
valid_sources[0x6a]	988	1			T2	3		T7	1		T27	1
valid_sources[0x6b]	868	1			T26	3		T7	3		T27	2
valid_sources[0x6c]	822	1			T2	8		T26	2		T7	5
valid_sources[0x6d]	886	1			T2	1		T26	2		T7	2
valid_sources[0x6e]	925	1			T7	1		T27	2		T11	3
valid_sources[0x6f]	1879	1			T2	3		T14	2		T26	1
valid_sources[0x70]	1002	1			T2	7		T26	2		T7	2
valid_sources[0x71]	1312	1			T2	1		T14	6		T26	1
valid_sources[0x72]	1013	1			T26	1		T7	5		T27	2
valid_sources[0x73]	854	1			T2	7		T26	2		T7	2
valid_sources[0x74]	1008	1			T26	2		T7	3		T11	4
valid_sources[0x75]	870	1			T2	3		T14	2		T7	1
valid_sources[0x76]	820	1			T2	6		T21	9		T7	2
valid_sources[0x77]	946	1			T2	1		T7	7		T9	1
valid_sources[0x78]	1414	1			T3	10		T26	3		T7	8
valid_sources[0x79]	1127	1			T2	7		T26	1		T7	3
valid_sources[0x7a]	871	1			T7	2		T9	1		T27	2
valid_sources[0x7b]	785	1			T26	1		T7	1		T27	1
valid_sources[0x7c]	3207	1			T2	6		T16	8		T7	2
valid_sources[0x7d]	1583	1			T14	1		T21	12		T11	2
valid_sources[0x7e]	1130	1			T2	2		T26	4		T7	1
valid_sources[0x7f]	1024	1			T26	3		T7	3		T27	1
valid_sources[0x80]	928	1			T2	4		T26	1		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

61376

1

T1

13

T4

1

T5

1

values[0x0]

all_enables

biggest_size

31716

1

T1

2

T4

3

T2

38

values[0x1]

all_enables

biggest_size

22482

1

T1

3

T4

4

T2

38