Unified Coverage Report :: Group :: dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

Group : dv_base_reg_pkg::dv_base_lockable_field_cov::regwen_val_when_new_value_written_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_lockable_field_cov.sv

119 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key0_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key1_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.key2_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_h2l	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.pwrb_in_l2h	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_debounce_ctl.debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.ac_present	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.bat_disable	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key0_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key1_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.key2_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.lid_open	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_in	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.pwrb_out	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.key_invert_ctl.z3_wakeup	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.bat_disable_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.ec_rst_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.flash_wp_l_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key0_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key1_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.key2_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.pwrb_out_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_0	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.pin_allowed_ctl.z3_wakeup_1	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_ac_debounce_ctl.ulp_ac_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_lid_debounce_ctl.ulp_lid_debounce_timer	100.00	1	100	1	64	64
lockable_field_cov_of_sysrst_ctrl_reg_block.ulp_pwrb_debounce_ctl.ulp_pwrb_debounce_timer	100.00	1	100	1	64	64

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.auto_block_enable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_debounce_ctl.debounce_timer

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key0_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key1_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.auto_block_out_ctl.key2_out_value

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_0.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_1.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_2.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_det_ctl_3.detection_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_0.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_1.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_2.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.bat_disable

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.ec_rst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.interrupt

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_out_ctl_3.rst_req

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_0.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_1.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_2.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_det_ctl_3.precondition_timer_0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_pre_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_0.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_1.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_2.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.ac_present_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key0_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key1_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.key2_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.com_sel_ctl_3.pwrb_in_sel

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.ec_rst_ctl.ec_rst_pulse

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ac_present_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.ec_rst_l_l2h

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

---

Group Instance : lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00

Variables for Group Instance lockable_field_cov_of_sysrst_ctrl_reg_block.key_intr_ctl.flash_wp_l_h2l

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_regwen	2	0	2	100.00	100	1	1	2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

157

1

T29

1

T272

2

T281

4

auto[1]

466

1

T23

5

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

270

1

T29

2

T30

1

T277

1

auto[1]

812

1

T23

6

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

168

1

T29

1

T30

1

T277

1

auto[1]

526

1

T23

6

T24

3

T25

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164

1

T30

1

T272

4

T273

2

auto[1]

537

1

T23

6

T24

2

T25

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161

1

T29

1

T277

1

T272

2

auto[1]

557

1

T23

4

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139

1

T29

1

T277

1

T272

3

auto[1]

536

1

T23

5

T24

3

T25

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

150

1

T29

1

T272

2

T273

3

auto[1]

513

1

T23

5

T24

1

T25

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

155

1

T30

1

T276

8

T277

1

auto[1]

541

1

T23

6

T25

3

T45

3

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

197

1

T29

3

T30

1

T276

3

auto[1]

3044

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

255

1

T29

1

T276

32

T272

3

auto[1]

3055

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

291

1

T29

2

T276

16

T277

1

auto[1]

2994

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

283

1

T29

2

T30

1

T276

20

auto[1]

3013

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

215

1

T277

1

T272

4

T273

3

auto[1]

1511

1

T7

20

T11

14

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

207

1

T277

1

T272

2

T273

4

auto[1]

1660

1

T11

14

T31

20

T43

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

192

1

T277

1

T272

3

T273

1

auto[1]

1552

1

T2

20

T7

20

T31

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

183

1

T29

1

T276

2

T273

1

auto[1]

1722

1

T7

20

T11

14

T33

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

282

1

T276

18

T277

1

T272

1

auto[1]

1465

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

289

1

T29

1

T276

18

T272

2

auto[1]

1446

1

T31

20

T33

20

T44

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

294

1

T29

1

T276

18

T272

1

auto[1]

1382

1

T2

20

T7

20

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

256

1

T277

1

T272

1

T281

2

auto[1]

1563

1

T2

20

T7

20

T31

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

212

1

T29

1

T272

2

T273

1

auto[1]

1778

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

230

1

T29

1

T30

1

T276

28

auto[1]

1620

1

T7

20

T11

14

T33

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

236

1

T29

1

T276

28

T272

1

auto[1]

1617

1

T7

20

T11

14

T31

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

225

1

T29

1

T276

28

T272

1

auto[1]

1812

1

T2

20

T7

20

T31

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164

1

T29

1

T276

15

T277

2

auto[1]

1637

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171

1

T29

1

T276

15

T277

1

auto[1]

1704

1

T7

20

T11

14

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

149

1

T276

15

T277

2

T272

3

auto[1]

1774

1

T7

20

T11

14

T31

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151

1

T272

1

T273

2

T281

5

auto[1]

1621

1

T7

20

T37

20

T105

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

285

1

T29

2

T276

35

T277

2

auto[1]

432

1

T28

1

T29

7

T272

6

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300

1

T29

2

T276

22

T272

4

auto[1]

430

1

T28

1

T29

6

T30

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

251

1

T29

2

T276

7

T277

1

auto[1]

463

1

T28

1

T29

7

T277

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

314

1

T29

2

T276

6

T272

3

auto[1]

338

1

T28

1

T29

8

T277

2

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

122

1

T277

1

T281

2

T284

1

auto[1]

566

1

T41

14

T70

11

T246

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

167

1

T276

9

T281

2

T375

1

auto[1]

774

1

T68

10

T41

14

T42

26

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

162

1

T277

1

T272

2

T273

1

auto[1]

926

1

T11

14

T69

8

T41

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128

1

T272

1

T273

1

T281

2

auto[1]

836

1

T43

24

T44

10

T69

8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164

1

T29

1

T276

9

T272

1

auto[1]

711

1

T11

14

T44

10

T69

8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

164

1

T276

29

T272

2

T273

1

auto[1]

679

1

T11

14

T68

10

T70

11

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

181

1

T29

1

T276

29

T273

2

auto[1]

749

1

T44

10

T69

8

T41

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

192

1

T276

29

T272

4

T273

1

auto[1]

787

1

T11

14

T43

24

T44

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187

1

T29

1

T276

29

T272

4

auto[1]

599

1

T44

10

T70

11

T246

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147

1

T29

1

T272

2

T273

1

auto[1]

742

1

T69

8

T42

26

T243

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

133

1

T29

1

T30

1

T272

3

auto[1]

734

1

T11

14

T44

10

T68

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

158

1

T29

1

T276

12

T273

3

auto[1]

701

1

T44

10

T69

8

T241

17

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161

1

T30

1

T276

12

T272

2

auto[1]

720

1

T43

24

T41

14

T242

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

138

1

T272

2

T273

3

T281

4

auto[1]

758

1

T70

11

T241

17

T242

18

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161

1

T29

1

T30

1

T276

12

auto[1]

876

1

T43

24

T44

10

T42

26

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

163

1

T29

1

T276

33

T277

1

auto[1]

692

1

T11

14

T44

10

T69

8

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

178

1

T29

1

T30

1

T276

33

auto[1]

693

1

T69

8

T41

14

T246

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134

1

T276

33

T277

1

T272

1

auto[1]

765

1

T43

24

T44

10

T41

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

132

1

T277

2

T272

1

T273

3

auto[1]

751

1

T69

8

T241

17

T239

7

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

172

1

T29

1

T30

1

T276

33

auto[1]

854

1

T11

14

T68

10

T42

26

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

161

1

T29

1

T276

4

T272

4

auto[1]

1526

1

T2

20

T31

20

T33

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160

1

T29

1

T276

4

T277

1

auto[1]

1572

1

T2

20

T7

20

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

148

1

T29

1

T276

4

T272

1

auto[1]

1432

1

T7

20

T32

20

T33

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

139

1

T29

1

T277

1

T272

2

auto[1]

1267

1

T7

20

T11

14

T33

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151

1

T29

2

T277

1

T272

2

auto[1]

1366

1

T31

20

T37

20

T105

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

249

1

T276

5

T277

1

T272

3

auto[1]

1458

1

T7

20

T32

20

T43

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

276

1

T29

1

T276

5

T277

1

auto[1]

1500

1

T2

20

T7

20

T31

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

271

1

T277

1

T272

3

T281

3

auto[1]

1408

1

T2

20

T32

20

T87

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

274

1

T277

1

T272

3

T273

2

auto[1]

1449

1

T2

20

T7

20

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

253

1

T276

5

T277

2

T272

2

auto[1]

1253

1

T2

20

T11

14

T43

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

134

1

T29

1

T30

1

T276

2

auto[1]

1458

1

T2

20

T32

20

T37

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

141

1

T277

1

T272

1

T273

4

auto[1]

1517

1

T2

20

T11

14

T43

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

136

1

T29

1

T30

1

T272

1

auto[1]

1498

1

T31

20

T32

20

T44

10

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

160

1

T29

1

T30

1

T276

2

auto[1]

1376

1

T11

14

T32

20

T33

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

151

1

T29

1

T276

2

T272

1

auto[1]

1348

1

T7

20

T11

14

T32

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

265

1

T29

1

T30

1

T276

16

auto[1]

1353

1

T7

20

T31

20

T37

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

282

1

T29

1

T277

1

T273

1

auto[1]

1463

1

T2

20

T32

20

T33

20

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

266

1

T30

1

T277

1

T272

1

auto[1]

1679

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

284

1

T29

1

T30

1

T276

16

auto[1]

1281

1

T2

20

T7

20

T11

14

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272

1

T30

1

T277

2

T281

5

auto[1]

1334

1

T7

20

T32

20

T43

24

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

258

1

T29

1

T277

2

T272

2

auto[1]

639

1

T5

1

T3

1

T59

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

128

1

T29

1

T272

1

T273

1

auto[1]

339

1

T7

1

T10

1

T37

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

147

1

T30

1

T277

1

T272

3

auto[1]

385

1

T3

1

T7

1

T12

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

140

1

T29

1

T277

1

T273

2

auto[1]

424

1

T3

2

T7

1

T38

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

114

1

T30

1

T277

1

T272

1

auto[1]

303

1

T7

1

T12

1

T38

1

Summary for Variable cp_regwen

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_regwen

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

156

1

T276

27

T277

1

T272

2

auto[1]

371

1

T3

1

T12

1

T34

1