Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T23,T24,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T23,T24,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T23,T24,T25

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T23,T24,T25
1	0	Covered	T1,T2,T3
1	1	Covered	T23,T24,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T25
0	1	Covered	T24,T94,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T23,T24,T25
0	1	Covered	T23,T24,T25
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T23,T24,T25
1	-	Covered	T23,T24,T25

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T23,T24,T25
DetectSt	168	Covered	T23,T24,T25
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T23,T24,T25

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T23,T24,T25
DebounceSt->IdleSt	163	Covered	T25,T73,T114
DetectSt->IdleSt	186	Covered	T24,T94,T97
DetectSt->StableSt	191	Covered	T23,T24,T25
IdleSt->DebounceSt	148	Covered	T23,T24,T25
StableSt->IdleSt	206	Covered	T23,T24,T25

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T23,T24,T25
0	1	Covered	T23,T24,T25
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T23,T24,T25
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T23,T24,T25
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73
DebounceSt	-	0	1	1	-	-	-	Covered	T23,T24,T25
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T114,T78
DebounceSt	-	0	0	-	-	-	-	Covered	T23,T24,T25
DetectSt	-	-	-	-	1	-	-	Covered	T24,T94,T97
DetectSt	-	-	-	-	0	1	-	Covered	T23,T24,T25
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T23,T24,T25
StableSt	-	-	-	-	-	-	0	Covered	T23,T24,T25
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	301	0	0
CntIncr_A	7040575	125251	0	0
CntNoWrap_A	7040575	6362632	0	0
DetectStDropOut_A	7040575	4	0	0
DetectedOut_A	7040575	998	0	0
DetectedPulseOut_A	7040575	139	0	0
DisabledIdleSt_A	7040575	6230831	0	0
DisabledNoDetection_A	7040575	6233165	0	0
EnterDebounceSt_A	7040575	159	0	0
EnterDetectSt_A	7040575	143	0	0
EnterStableSt_A	7040575	139	0	0
PulseIsPulse_A	7040575	139	0	0
StayInStableSt	7040575	859	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7040575	7044	0	0
gen_low_level_sva.LowLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	138	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	301	0	0
T23	3297	8	0	0
T24	0	4	0	0
T25	0	3	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	4	0	0
T49	0	8	0	0
T50	0	2	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T73	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	125251	0	0
T23	3297	211	0	0
T24	0	124	0	0
T25	0	39	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	19	0	0
T46	0	63	0	0
T47	0	30	0	0
T48	0	80	0	0
T49	0	207	0	0
T50	0	36	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T73	0	9	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362632	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	4	0	0
T24	661	1	0	0
T25	564	0	0	0
T43	29870	0	0	0
T61	495	0	0	0
T66	502	0	0	0
T94	0	1	0	0
T97	0	1	0	0
T98	0	1	0	0
T100	404	0	0	0
T101	661	0	0	0
T102	694	0	0	0
T103	425	0	0	0
T104	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	998	0	0
T23	3297	34	0	0
T24	0	8	0	0
T25	0	5	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	11	0	0
T46	0	7	0	0
T47	0	10	0	0
T48	0	19	0	0
T49	0	31	0	0
T50	0	11	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T109	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	139	0	0
T23	3297	4	0	0
T24	0	1	0	0
T25	0	1	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	1	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6230831	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6233165	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	159	0	0
T23	3297	4	0	0
T24	0	2	0	0
T25	0	2	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	1	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	143	0	0
T23	3297	4	0	0
T24	0	2	0	0
T25	0	1	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	1	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	139	0	0
T23	3297	4	0	0
T24	0	1	0	0
T25	0	1	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	1	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	139	0	0
T23	3297	4	0	0
T24	0	1	0	0
T25	0	1	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	1	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	859	0	0
T23	3297	30	0	0
T24	0	7	0	0
T25	0	4	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	10	0	0
T46	0	6	0	0
T47	0	9	0	0
T48	0	17	0	0
T49	0	27	0	0
T50	0	10	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T109	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	7044	0	0
T1	1205	8	0	0
T2	22284	12	0	0
T3	12531	39	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	5	0	0
T7	0	16	0	0
T13	456	0	0	0
T14	493	8	0	0
T15	436	2	0	0
T16	411	0	0	0
T21	0	5	0	0
T26	0	22	0	0
T52	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	138	0	0
T23	3297	4	0	0
T24	0	1	0	0
T25	0	1	0	0
T31	30619	0	0	0
T38	604	0	0	0
T40	451	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	4	0	0
T50	0	1	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T109	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Covered	T8,T85,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T6
0	1	Unreachable
1	0	Covered	T1,T3,T6

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T3,T6
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T3,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T6
DebounceSt->IdleSt	163	Covered	T8,T71,T73
DetectSt->IdleSt	186	Covered	T8,T85,T86
DetectSt->StableSt	191	Covered	T1,T3,T6
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T3,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T6
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T71,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T8,T85,T86
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T6
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	162	0	0
CntIncr_A	7040575	157555	0	0
CntNoWrap_A	7040575	6362771	0	0
DetectStDropOut_A	7040575	5	0	0
DetectedOut_A	7040575	12663	0	0
DetectedPulseOut_A	7040575	60	0	0
DisabledIdleSt_A	7040575	5124654	0	0
DisabledNoDetection_A	7040575	5127032	0	0
EnterDebounceSt_A	7040575	97	0	0
EnterDetectSt_A	7040575	65	0	0
EnterStableSt_A	7040575	60	0	0
PulseIsPulse_A	7040575	60	0	0
StayInStableSt	7040575	12603	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7040575	7044	0	0
gen_low_level_sva.LowLevelEvent_A	7040575	6365313	0	0
gen_sticky_sva.StableStDropOut_A	7040575	886951	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	162	0	0
T1	1205	2	0	0
T2	22284	0	0	0
T3	12531	2	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	4	0	0
T8	0	3	0	0
T9	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	2	0	0
T49	0	2	0	0
T60	0	6	0	0
T71	0	4	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	157555	0	0
T1	1205	40	0	0
T2	22284	0	0	0
T3	12531	79	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	132	0	0
T8	0	20	0	0
T9	0	53	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	24	0	0
T49	0	87	0	0
T60	0	264	0	0
T71	0	48	0	0
T72	0	56	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362771	0	0
T1	1205	802	0	0
T2	22284	21824	0	0
T3	12531	4842	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1082	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5	0	0
T8	62662	1	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T59	695	0	0	0
T64	523	0	0	0
T85	0	1	0	0
T86	0	1	0	0
T99	453	0	0	0
T116	0	1	0	0
T117	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	12663	0	0
T1	1205	328	0	0
T2	22284	0	0	0
T3	12531	98	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	102	0	0
T9	0	196	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	87	0	0
T49	0	142	0	0
T60	0	871	0	0
T72	0	117	0	0
T111	0	57	0	0
T112	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	60	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	1	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T72	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5124654	0	0
T1	1205	305	0	0
T2	22284	21824	0	0
T3	12531	4498	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	653	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5127032	0	0
T1	1205	306	0	0
T2	22284	21833	0	0
T3	12531	4522	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	654	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	97	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	1	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T8	0	2	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T71	0	4	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	65	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	1	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T72	0	1	0	0
T85	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	60	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	1	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T72	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	60	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	1	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T72	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	12603	0	0
T1	1205	327	0	0
T2	22284	0	0	0
T3	12531	97	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	100	0	0
T9	0	195	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	86	0	0
T49	0	141	0	0
T60	0	868	0	0
T72	0	116	0	0
T111	0	56	0	0
T112	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	7044	0	0
T1	1205	8	0	0
T2	22284	12	0	0
T3	12531	39	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	5	0	0
T7	0	16	0	0
T13	456	0	0	0
T14	493	8	0	0
T15	436	2	0	0
T16	411	0	0	0
T21	0	5	0	0
T26	0	22	0	0
T52	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	886951	0	0
T1	1205	122	0	0
T2	22284	0	0	0
T3	12531	152	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	159	0	0
T9	0	72	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	8143	0	0
T49	0	119	0	0
T60	0	137	0	0
T72	0	62	0	0
T111	0	31	0	0
T112	0	31	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T78,T83,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Unreachable
1	0	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T9
DebounceSt->IdleSt	163	Covered	T3,T6,T73
DetectSt->IdleSt	186	Covered	T78,T83,T84
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T3,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T6,T111
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T78,T83,T84
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	179	0	0
CntIncr_A	7040575	150460	0	0
CntNoWrap_A	7040575	6362754	0	0
DetectStDropOut_A	7040575	12	0	0
DetectedOut_A	7040575	231276	0	0
DetectedPulseOut_A	7040575	49	0	0
DisabledIdleSt_A	7040575	5124654	0	0
DisabledNoDetection_A	7040575	5127032	0	0
EnterDebounceSt_A	7040575	118	0	0
EnterDetectSt_A	7040575	61	0	0
EnterStableSt_A	7040575	49	0	0
PulseIsPulse_A	7040575	49	0	0
StayInStableSt	7040575	231227	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_sticky_sva.StableStDropOut_A	7040575	465001	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	179	0	0
T1	1205	2	0	0
T2	22284	0	0	0
T3	12531	2	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	2	0	0
T49	0	2	0	0
T60	0	6	0	0
T71	0	2	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	150460	0	0
T1	1205	55	0	0
T2	22284	0	0	0
T3	12531	126	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	118	0	0
T8	0	24	0	0
T9	0	61	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	2283	0	0
T49	0	76	0	0
T60	0	105	0	0
T71	0	24	0	0
T72	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362754	0	0
T1	1205	802	0	0
T2	22284	21824	0	0
T3	12531	4842	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1084	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	12	0	0
T78	13254	1	0	0
T83	0	3	0	0
T84	0	1	0	0
T113	1198	0	0	0
T116	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	503	0	0	0
T124	498	0	0	0
T125	407	0	0	0
T126	502	0	0	0
T127	701	0	0	0
T128	422	0	0	0
T129	484	0	0	0
T130	5317	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	231276	0	0
T1	1205	223	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T8	0	57	0	0
T9	0	128	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	5918	0	0
T49	0	112	0	0
T60	0	240	0	0
T71	0	94	0	0
T72	0	125	0	0
T85	0	1	0	0
T112	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	49	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5124654	0	0
T1	1205	305	0	0
T2	22284	21824	0	0
T3	12531	4498	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	653	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5127032	0	0
T1	1205	306	0	0
T2	22284	21833	0	0
T3	12531	4522	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	654	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	118	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	2	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T8	0	1	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	61	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	49	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	49	0	0
T1	1205	1	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	1	0	0
T60	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	231227	0	0
T1	1205	222	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T8	0	56	0	0
T9	0	127	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	5917	0	0
T49	0	111	0	0
T60	0	237	0	0
T71	0	93	0	0
T72	0	124	0	0
T113	0	565	0	0
T131	0	1156	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	465001	0	0
T1	1205	199	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T8	0	62126	0	0
T9	0	123	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	59	0	0
T49	0	170	0	0
T60	0	923	0	0
T71	0	128	0	0
T72	0	55	0	0
T85	0	26	0	0
T112	0	111	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T3,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T3,T6

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T9,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T60,T35
0	1	Covered	T1,T79,T80
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T60,T35
0	1	Unreachable
1	0	Covered	T9,T60,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T3,T6
DetectSt	168	Covered	T1,T9,T60
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T60,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T60
DebounceSt->IdleSt	163	Covered	T1,T3,T6
DetectSt->IdleSt	186	Covered	T1,T79,T80
DetectSt->StableSt	191	Covered	T9,T60,T35
IdleSt->DebounceSt	148	Covered	T1,T3,T6
StableSt->IdleSt	206	Covered	T9,T60,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T3,T6
0	1	Covered	T1,T3,T6
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T60
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T3,T6
IdleSt	0	-	-	-	-	-	-	Covered	T1,T2,T3
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T3,T6
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T3,T6
DetectSt	-	-	-	-	1	-	-	Covered	T1,T79,T80
DetectSt	-	-	-	-	0	1	-	Covered	T9,T60,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T60,T35
StableSt	-	-	-	-	-	-	0	Covered	T9,T60,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	188	0	0
CntIncr_A	7040575	196002	0	0
CntNoWrap_A	7040575	6362745	0	0
DetectStDropOut_A	7040575	14	0	0
DetectedOut_A	7040575	509469	0	0
DetectedPulseOut_A	7040575	50	0	0
DisabledIdleSt_A	7040575	5124654	0	0
DisabledNoDetection_A	7040575	5127032	0	0
EnterDebounceSt_A	7040575	124	0	0
EnterDetectSt_A	7040575	64	0	0
EnterStableSt_A	7040575	50	0	0
PulseIsPulse_A	7040575	50	0	0
StayInStableSt	7040575	509419	0	0
gen_high_event_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_sticky_sva.StableStDropOut_A	7040575	374413	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	188	0	0
T1	1205	7	0	0
T2	22284	0	0	0
T3	12531	2	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	2	0	0
T49	0	2	0	0
T60	0	6	0	0
T71	0	2	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	196002	0	0
T1	1205	340	0	0
T2	22284	0	0	0
T3	12531	78	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	60	0	0
T8	0	62198	0	0
T9	0	87	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	19	0	0
T49	0	92	0	0
T60	0	36	0	0
T71	0	40	0	0
T72	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362745	0	0
T1	1205	797	0	0
T2	22284	21824	0	0
T3	12531	4842	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1084	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	14	0	0
T1	1205	2	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T79	0	2	0	0
T80	0	1	0	0
T132	0	2	0	0
T133	0	4	0	0
T134	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	509469	0	0
T9	1525	202	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T35	0	44	0	0
T59	695	0	0	0
T60	0	92	0	0
T64	523	0	0	0
T71	0	128	0	0
T72	0	125	0	0
T78	0	352	0	0
T83	0	720	0	0
T85	0	5	0	0
T99	453	0	0	0
T112	0	3	0	0
T113	0	438	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	50	0	0
T9	1525	1	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T35	0	1	0	0
T59	695	0	0	0
T60	0	3	0	0
T64	523	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T78	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T99	453	0	0	0
T112	0	1	0	0
T113	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5124654	0	0
T1	1205	305	0	0
T2	22284	21824	0	0
T3	12531	4498	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	653	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5127032	0	0
T1	1205	306	0	0
T2	22284	21833	0	0
T3	12531	4522	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	654	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	124	0	0
T1	1205	5	0	0
T2	22284	0	0	0
T3	12531	2	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	2	0	0
T8	0	2	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T49	0	2	0	0
T60	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	64	0	0
T1	1205	2	0	0
T2	22284	0	0	0
T3	12531	0	0	0
T4	402	0	0	0
T5	527	0	0	0
T6	1487	0	0	0
T9	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T35	0	1	0	0
T60	0	3	0	0
T71	0	1	0	0
T72	0	1	0	0
T78	0	1	0	0
T85	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	50	0	0
T9	1525	1	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T35	0	1	0	0
T59	695	0	0	0
T60	0	3	0	0
T64	523	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T78	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T99	453	0	0	0
T112	0	1	0	0
T113	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	50	0	0
T9	1525	1	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T35	0	1	0	0
T59	695	0	0	0
T60	0	3	0	0
T64	523	0	0	0
T71	0	1	0	0
T72	0	1	0	0
T78	0	1	0	0
T83	0	2	0	0
T85	0	1	0	0
T99	453	0	0	0
T112	0	1	0	0
T113	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	509419	0	0
T9	1525	201	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T35	0	43	0	0
T59	695	0	0	0
T60	0	89	0	0
T64	523	0	0	0
T71	0	127	0	0
T72	0	124	0	0
T78	0	351	0	0
T83	0	718	0	0
T85	0	4	0	0
T99	453	0	0	0
T112	0	2	0	0
T113	0	437	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	374413	0	0
T9	1525	43	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T35	0	8203	0	0
T59	695	0	0	0
T60	0	1171	0	0
T64	523	0	0	0
T71	0	88	0	0
T72	0	72	0	0
T78	0	41	0	0
T83	0	136	0	0
T85	0	102	0	0
T99	453	0	0	0
T112	0	105	0	0
T113	0	230	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T12,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T12,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T12
1	0	Covered	T1,T4,T5
1	1	Covered	T12,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T34,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T34,T35
0	1	Covered	T12,T77,T135
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T34,T35
1	-	Covered	T12,T77,T135

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T12,T34,T35
DetectSt	168	Covered	T12,T34,T35
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T12,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T34,T35
DebounceSt->IdleSt	163	Covered	T73,T74,T136
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T12,T34,T35
IdleSt->DebounceSt	148	Covered	T12,T34,T35
StableSt->IdleSt	206	Covered	T12,T34,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T12,T34,T35
0	1	Covered	T12,T34,T35
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T34,T35
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T12,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T136
DebounceSt	-	0	0	-	-	-	-	Covered	T12,T34,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T12,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T77,T135
StableSt	-	-	-	-	-	-	0	Covered	T12,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	71	0	0
CntIncr_A	7040575	105710	0	0
CntNoWrap_A	7040575	6362862	0	0
DetectStDropOut_A	7040575	0	0	0
DetectedOut_A	7040575	1999	0	0
DetectedPulseOut_A	7040575	34	0	0
DisabledIdleSt_A	7040575	5864774	0	0
DisabledNoDetection_A	7040575	5867098	0	0
EnterDebounceSt_A	7040575	37	0	0
EnterDetectSt_A	7040575	34	0	0
EnterStableSt_A	7040575	34	0	0
PulseIsPulse_A	7040575	34	0	0
StayInStableSt	7040575	1948	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	71	0	0
T12	1213	4	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	604	0	0	0
T49	0	4	0	0
T50	0	4	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T73	0	1	0	0
T77	0	2	0	0
T99	453	0	0	0
T135	0	2	0	0
T137	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	105710	0	0
T12	1213	200	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	61	0	0
T35	0	62	0	0
T36	0	32	0	0
T38	604	0	0	0
T49	0	92	0	0
T50	0	68	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T73	0	15	0	0
T77	0	82	0	0
T99	453	0	0	0
T135	0	48538	0	0
T137	0	81	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362862	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1999	0	0
T12	1213	76	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	212	0	0
T35	0	37	0	0
T36	0	41	0	0
T38	604	0	0	0
T49	0	85	0	0
T50	0	107	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	3	0	0
T99	453	0	0	0
T135	0	40	0	0
T137	0	43	0	0
T138	0	107	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	34	0	0
T12	1213	2	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	604	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	1	0	0
T99	453	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5864774	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4594	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5867098	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4617	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	37	0	0
T12	1213	2	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	604	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T73	0	1	0	0
T77	0	1	0	0
T99	453	0	0	0
T135	0	1	0	0
T137	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	34	0	0
T12	1213	2	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	604	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	1	0	0
T99	453	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	34	0	0
T12	1213	2	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	604	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	1	0	0
T99	453	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	34	0	0
T12	1213	2	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	604	0	0	0
T49	0	2	0	0
T50	0	2	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	1	0	0
T99	453	0	0	0
T135	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1948	0	0
T12	1213	74	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	210	0	0
T35	0	35	0	0
T36	0	39	0	0
T38	604	0	0	0
T49	0	81	0	0
T50	0	104	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	2	0	0
T99	453	0	0	0
T135	0	39	0	0
T137	0	41	0	0
T138	0	104	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	17	0	0
T12	1213	2	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T50	0	1	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	1	0	0
T99	453	0	0	0
T135	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0
T141	0	2	0	0
T142	0	1	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T12,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T12,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T12,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T12,T34
1	0	Covered	T2,T3,T14
1	1	Covered	T3,T12,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T34
0	1	Covered	T141
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T12,T34
0	1	Covered	T12,T34,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T12,T34
1	-	Covered	T12,T34,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T12,T34
DetectSt	168	Covered	T3,T12,T34
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T12,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T12,T34
DebounceSt->IdleSt	163	Covered	T73,T144,T74
DetectSt->IdleSt	186	Covered	T141
DetectSt->StableSt	191	Covered	T3,T12,T34
IdleSt->DebounceSt	148	Covered	T3,T12,T34
StableSt->IdleSt	206	Covered	T3,T12,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T12,T34
0	1	Covered	T3,T12,T34
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T12,T34
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T12,T34
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T12,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T144,T142,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T12,T34
DetectSt	-	-	-	-	1	-	-	Covered	T141
DetectSt	-	-	-	-	0	1	-	Covered	T3,T12,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T34,T37
StableSt	-	-	-	-	-	-	0	Covered	T3,T12,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	126	0	0
CntIncr_A	7040575	113972	0	0
CntNoWrap_A	7040575	6362807	0	0
DetectStDropOut_A	7040575	2	0	0
DetectedOut_A	7040575	60503	0	0
DetectedPulseOut_A	7040575	58	0	0
DisabledIdleSt_A	7040575	6152424	0	0
DisabledNoDetection_A	7040575	6154747	0	0
EnterDebounceSt_A	7040575	67	0	0
EnterDetectSt_A	7040575	60	0	0
EnterStableSt_A	7040575	58	0	0
PulseIsPulse_A	7040575	58	0	0
StayInStableSt	7040575	60421	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7040575	2832	0	0
gen_low_level_sva.LowLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	126	0	0
T3	12531	2	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	6	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	2	0	0
T37	0	4	0	0
T49	0	4	0	0
T52	448	0	0	0
T73	0	1	0	0
T77	0	4	0	0
T137	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	113972	0	0
T3	12531	24	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	300	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	61	0	0
T37	0	106	0	0
T49	0	92	0	0
T52	448	0	0	0
T73	0	15	0	0
T77	0	164	0	0
T137	0	81	0	0
T146	0	67	0	0
T147	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362807	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4842	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	2	0	0
T97	669	0	0	0
T141	3250	2	0	0
T148	523	0	0	0
T149	432	0	0	0
T150	6169	0	0	0
T151	26106	0	0	0
T152	12548	0	0	0
T153	4420	0	0	0
T154	1026	0	0	0
T155	7203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	60503	0	0
T3	12531	137	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	224	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	39	0	0
T37	0	83	0	0
T49	0	255	0	0
T52	448	0	0	0
T77	0	286	0	0
T137	0	47	0	0
T138	0	110	0	0
T146	0	111	0	0
T147	0	84	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	58	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	3	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T49	0	2	0	0
T52	448	0	0	0
T77	0	2	0	0
T137	0	1	0	0
T138	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6152424	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4675	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6154747	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4698	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	67	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	3	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T49	0	2	0	0
T52	448	0	0	0
T73	0	1	0	0
T77	0	2	0	0
T137	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	60	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	3	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T49	0	2	0	0
T52	448	0	0	0
T77	0	2	0	0
T137	0	1	0	0
T138	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	58	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	3	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T49	0	2	0	0
T52	448	0	0	0
T77	0	2	0	0
T137	0	1	0	0
T138	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	58	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	3	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T49	0	2	0	0
T52	448	0	0	0
T77	0	2	0	0
T137	0	1	0	0
T138	0	2	0	0
T146	0	1	0	0
T147	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	60421	0	0
T3	12531	135	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T12	0	220	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T34	0	38	0	0
T37	0	80	0	0
T49	0	253	0	0
T52	448	0	0	0
T77	0	283	0	0
T137	0	46	0	0
T138	0	108	0	0
T146	0	109	0	0
T147	0	82	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	2832	0	0
T3	12531	29	0	0
T6	1487	0	0	0
T7	25889	1	0	0
T8	62662	0	0	0
T10	0	2	0	0
T12	0	3	0	0
T14	493	4	0	0
T15	436	3	0	0
T16	411	1	0	0
T21	502	5	0	0
T22	0	5	0	0
T26	5267	0	0	0
T52	448	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	34	0	0
T12	1213	2	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T38	604	0	0	0
T49	0	2	0	0
T53	427	0	0	0
T64	523	0	0	0
T65	526	0	0	0
T77	0	1	0	0
T81	0	1	0	0
T99	453	0	0	0
T137	0	1	0	0
T138	0	2	0	0
T156	0	1	0	0
T157	0	1	0	0