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Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.61 95.65 85.71 83.33 95.00 93.33


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.61 95.65 85.71 83.33 95.00 93.33


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.69 95.65 85.71 83.33 95.00 93.75


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.10 100.00 90.48 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.66 97.83 90.48 100.00 95.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.66 97.83 90.48 100.00 95.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_sysrst_ctrl_keyintr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT2,T13,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT2,T13,T3
11CoveredT2,T13,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT12,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T4,T5 VC_COV_UNR
1CoveredT12,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT12,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT12,T38,T39
10CoveredT2,T13,T3
11CoveredT12,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT12,T38,T39
01CoveredT133
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT12,T38,T39
01CoveredT12,T38,T34
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT12,T38,T39
1-CoveredT12,T38,T34

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T12,T38,T39
DetectSt 168 Covered T12,T38,T39
IdleSt 163 Covered T1,T4,T5
StableSt 191 Covered T12,T38,T39


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T12,T38,T39
DebounceSt->IdleSt 163 Covered T37,T135,T73
DetectSt->IdleSt 186 Covered T133
DetectSt->StableSt 191 Covered T12,T38,T39
IdleSt->DebounceSt 148 Covered T12,T38,T39
StableSt->IdleSt 206 Covered T12,T38,T34



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T12,T38,T39
0 1 Covered T12,T38,T39
0 0 Excluded T1,T4,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T12,T38,T39
0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T12,T38,T39
IdleSt 0 - - - - - - Covered T2,T13,T3
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T12,T38,T39
DebounceSt - 0 1 0 - - - Covered T37,T135,T90
DebounceSt - 0 0 - - - - Covered T12,T38,T39
DetectSt - - - - 1 - - Covered T133
DetectSt - - - - 0 1 - Covered T12,T38,T39
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T12,T38,T34
StableSt - - - - - - 0 Covered T12,T38,T39
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7040575 124 0 0
CntIncr_A 7040575 100616 0 0
CntNoWrap_A 7040575 6362809 0 0
DetectStDropOut_A 7040575 1 0 0
DetectedOut_A 7040575 52456 0 0
DetectedPulseOut_A 7040575 57 0 0
DisabledIdleSt_A 7040575 6057536 0 0
DisabledNoDetection_A 7040575 6059868 0 0
EnterDebounceSt_A 7040575 66 0 0
EnterDetectSt_A 7040575 58 0 0
EnterStableSt_A 7040575 57 0 0
PulseIsPulse_A 7040575 57 0 0
StayInStableSt 7040575 52375 0 0
gen_high_level_sva.HighLevelEvent_A 7040575 6365313 0 0
gen_not_sticky_sva.StableStDropOut_A 7040575 33 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 124 0 0
T12 1213 4 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 2 0 0
T35 0 2 0 0
T37 0 3 0 0
T38 604 2 0 0
T39 0 2 0 0
T49 0 2 0 0
T50 0 4 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 6 0 0
T99 453 0 0 0
T135 0 3 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 100616 0 0
T12 1213 200 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 61 0 0
T35 0 91 0 0
T37 0 106 0 0
T38 604 57 0 0
T39 0 47 0 0
T49 0 73 0 0
T50 0 68 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 246 0 0
T99 453 0 0 0
T135 0 97076 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6362809 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 1 0 0
T133 15867 1 0 0
T210 5833 0 0 0
T211 495 0 0 0
T212 491 0 0 0
T213 503 0 0 0
T214 402 0 0 0
T215 504 0 0 0
T216 523 0 0 0
T217 35295 0 0 0
T218 522 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 52456 0 0
T12 1213 184 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 40 0 0
T35 0 40 0 0
T37 0 8 0 0
T38 604 41 0 0
T39 0 103 0 0
T49 0 26 0 0
T50 0 42 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 126 0 0
T99 453 0 0 0
T135 0 48581 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 57 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 1 0 0
T35 0 1 0 0
T37 0 1 0 0
T38 604 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T50 0 2 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 3 0 0
T99 453 0 0 0
T135 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6057536 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6059868 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 66 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 1 0 0
T35 0 1 0 0
T37 0 2 0 0
T38 604 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T50 0 2 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 3 0 0
T99 453 0 0 0
T135 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 58 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 1 0 0
T35 0 1 0 0
T37 0 1 0 0
T38 604 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T50 0 2 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 3 0 0
T99 453 0 0 0
T135 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 57 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 1 0 0
T35 0 1 0 0
T37 0 1 0 0
T38 604 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T50 0 2 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 3 0 0
T99 453 0 0 0
T135 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 57 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 1 0 0
T35 0 1 0 0
T37 0 1 0 0
T38 604 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T50 0 2 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 3 0 0
T99 453 0 0 0
T135 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 52375 0 0
T12 1213 182 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 39 0 0
T35 0 38 0 0
T37 0 7 0 0
T38 604 40 0 0
T39 0 101 0 0
T49 0 25 0 0
T50 0 39 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 122 0 0
T99 453 0 0 0
T135 0 48579 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6365313 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 33 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T34 0 1 0 0
T37 0 1 0 0
T38 604 1 0 0
T49 0 1 0 0
T50 0 1 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T77 0 2 0 0
T90 0 1 0 0
T99 453 0 0 0
T137 0 1 0 0
T156 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT2,T13,T3
1CoveredT1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT2,T13,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT7,T10,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T4,T5 VC_COV_UNR
1CoveredT7,T10,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT7,T10,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT3,T7,T10
10CoveredT2,T13,T3
11CoveredT7,T10,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT7,T10,T38
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT7,T10,T38
01CoveredT7,T90,T157
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT7,T10,T38
1-CoveredT7,T90,T157

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T7,T10,T38
DetectSt 168 Covered T7,T10,T38
IdleSt 163 Covered T1,T4,T5
StableSt 191 Covered T7,T10,T38


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T7,T10,T38
DebounceSt->IdleSt 163 Covered T73,T156,T74
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T7,T10,T38
IdleSt->DebounceSt 148 Covered T7,T10,T38
StableSt->IdleSt 206 Covered T7,T34,T49



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T7,T10,T38
0 1 Covered T7,T10,T38
0 0 Excluded T1,T4,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T7,T10,T38
0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T7,T10,T38
IdleSt 0 - - - - - - Covered T1,T4,T5
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T7,T10,T38
DebounceSt - 0 1 0 - - - Covered T156
DebounceSt - 0 0 - - - - Covered T7,T10,T38
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T7,T10,T38
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T7,T90,T157
StableSt - - - - - - 0 Covered T7,T10,T38
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7040575 59 0 0
CntIncr_A 7040575 1571 0 0
CntNoWrap_A 7040575 6362874 0 0
DetectStDropOut_A 7040575 0 0 0
DetectedOut_A 7040575 1783 0 0
DetectedPulseOut_A 7040575 28 0 0
DisabledIdleSt_A 7040575 6155380 0 0
DisabledNoDetection_A 7040575 6157709 0 0
EnterDebounceSt_A 7040575 31 0 0
EnterDetectSt_A 7040575 28 0 0
EnterStableSt_A 7040575 28 0 0
PulseIsPulse_A 7040575 28 0 0
StayInStableSt 7040575 1739 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7040575 6289 0 0
gen_low_level_sva.LowLevelEvent_A 7040575 6365313 0 0
gen_not_sticky_sva.StableStDropOut_A 7040575 12 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 59 0 0
T7 25889 4 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 2 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 2 0 0
T38 0 2 0 0
T49 0 2 0 0
T59 695 0 0 0
T73 0 1 0 0
T90 0 4 0 0
T99 453 0 0 0
T137 0 2 0 0
T156 0 1 0 0
T181 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 1571 0 0
T7 25889 40 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 84 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 61 0 0
T38 0 57 0 0
T49 0 73 0 0
T59 695 0 0 0
T73 0 16 0 0
T90 0 48 0 0
T99 453 0 0 0
T137 0 81 0 0
T156 0 61 0 0
T181 0 44 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6362874 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 1783 0 0
T7 25889 82 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 52 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 212 0 0
T38 0 39 0 0
T49 0 302 0 0
T59 695 0 0 0
T90 0 84 0 0
T99 453 0 0 0
T137 0 44 0 0
T139 0 39 0 0
T157 0 40 0 0
T181 0 41 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 28 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T38 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T90 0 2 0 0
T99 453 0 0 0
T137 0 1 0 0
T139 0 1 0 0
T157 0 1 0 0
T181 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6155380 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4594 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6157709 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4617 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 31 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T38 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T73 0 1 0 0
T90 0 2 0 0
T99 453 0 0 0
T137 0 1 0 0
T156 0 1 0 0
T181 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 28 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T38 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T90 0 2 0 0
T99 453 0 0 0
T137 0 1 0 0
T139 0 1 0 0
T157 0 1 0 0
T181 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 28 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T38 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T90 0 2 0 0
T99 453 0 0 0
T137 0 1 0 0
T139 0 1 0 0
T157 0 1 0 0
T181 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 28 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T38 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T90 0 2 0 0
T99 453 0 0 0
T137 0 1 0 0
T139 0 1 0 0
T157 0 1 0 0
T181 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 1739 0 0
T7 25889 79 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 50 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 210 0 0
T38 0 37 0 0
T49 0 300 0 0
T59 695 0 0 0
T90 0 81 0 0
T99 453 0 0 0
T137 0 42 0 0
T139 0 37 0 0
T157 0 39 0 0
T181 0 39 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6289 0 0
T2 22284 10 0 0
T3 12531 40 0 0
T6 1487 0 0 0
T7 0 15 0 0
T13 456 1 0 0
T14 493 5 0 0
T15 436 2 0 0
T16 411 1 0 0
T21 502 5 0 0
T26 5267 21 0 0
T52 448 3 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6365313 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 12 0 0
T7 25889 1 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 0 0 0
T11 12069 0 0 0
T12 1213 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T59 695 0 0 0
T90 0 1 0 0
T99 453 0 0 0
T121 0 2 0 0
T145 0 1 0 0
T157 0 1 0 0
T158 0 1 0 0
T203 0 1 0 0
T204 0 1 0 0
T219 0 1 0 0
T220 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT2,T13,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT2,T13,T3
11CoveredT2,T13,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT7,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T4,T5 VC_COV_UNR
1CoveredT7,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT7,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT7,T10,T12
10CoveredT2,T13,T3
11CoveredT7,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT7,T10,T12
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT7,T10,T12
01CoveredT10,T12,T36
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT7,T10,T12
1-CoveredT10,T12,T36

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T7,T10,T12
DetectSt 168 Covered T7,T10,T12
IdleSt 163 Covered T1,T4,T5
StableSt 191 Covered T7,T10,T12


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T7,T10,T12
DebounceSt->IdleSt 163 Covered T37,T73,T74
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T7,T10,T12
IdleSt->DebounceSt 148 Covered T7,T10,T12
StableSt->IdleSt 206 Covered T7,T10,T12



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T7,T10,T12
0 1 Covered T7,T10,T12
0 0 Excluded T1,T4,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T7,T10,T12
0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T7,T10,T12
IdleSt 0 - - - - - - Covered T2,T13,T3
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T7,T10,T12
DebounceSt - 0 1 0 - - - Covered T37,T221,T222
DebounceSt - 0 0 - - - - Covered T7,T10,T12
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T7,T10,T12
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T10,T12,T36
StableSt - - - - - - 0 Covered T7,T10,T12
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 14 93.33
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 14 93.33




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7040575 110 0 0
CntIncr_A 7040575 21691 0 0
CntNoWrap_A 7040575 6362823 0 0
DetectStDropOut_A 7040575 0 0 0
DetectedOut_A 7040575 24106 0 0
DetectedPulseOut_A 7040575 52 0 0
DisabledIdleSt_A 7040575 6116496 0 0
DisabledNoDetection_A 7040575 6118825 0 0
EnterDebounceSt_A 7040575 58 0 0
EnterDetectSt_A 7040575 52 0 0
EnterStableSt_A 7040575 52 0 0
PulseIsPulse_A 7040575 52 0 0
StayInStableSt 7040575 24031 0 0
gen_high_level_sva.HighLevelEvent_A 7040575 6365313 0 0
gen_not_sticky_sva.StableStDropOut_A 7040575 29 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 110 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 2 0 0
T11 12069 0 0 0
T12 1213 4 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 2 0 0
T36 0 2 0 0
T37 0 1 0 0
T49 0 2 0 0
T59 695 0 0 0
T73 0 1 0 0
T99 453 0 0 0
T147 0 2 0 0
T159 0 10 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 21691 0 0
T7 25889 20 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 84 0 0
T11 12069 0 0 0
T12 1213 200 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 61 0 0
T36 0 32 0 0
T37 0 53 0 0
T49 0 73 0 0
T59 695 0 0 0
T73 0 16 0 0
T99 453 0 0 0
T147 0 24 0 0
T159 0 198 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6362823 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 24106 0 0
T7 25889 125 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 57 0 0
T11 12069 0 0 0
T12 1213 317 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 110 0 0
T36 0 76 0 0
T49 0 303 0 0
T59 695 0 0 0
T99 453 0 0 0
T138 0 218 0 0
T147 0 19 0 0
T159 0 367 0 0
T223 0 131 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 52 0 0
T7 25889 1 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T36 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T99 453 0 0 0
T138 0 2 0 0
T147 0 1 0 0
T159 0 5 0 0
T223 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6116496 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6118825 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 58 0 0
T7 25889 1 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T36 0 1 0 0
T37 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T73 0 1 0 0
T99 453 0 0 0
T147 0 1 0 0
T159 0 5 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 52 0 0
T7 25889 1 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T36 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T99 453 0 0 0
T138 0 2 0 0
T147 0 1 0 0
T159 0 5 0 0
T223 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 52 0 0
T7 25889 1 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T36 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T99 453 0 0 0
T138 0 2 0 0
T147 0 1 0 0
T159 0 5 0 0
T223 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 52 0 0
T7 25889 1 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 1 0 0
T36 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T99 453 0 0 0
T138 0 2 0 0
T147 0 1 0 0
T159 0 5 0 0
T223 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 24031 0 0
T7 25889 123 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 56 0 0
T11 12069 0 0 0
T12 1213 315 0 0
T22 561 0 0 0
T27 4716 0 0 0
T34 0 108 0 0
T36 0 75 0 0
T49 0 301 0 0
T59 695 0 0 0
T99 453 0 0 0
T138 0 215 0 0
T147 0 18 0 0
T159 0 361 0 0
T223 0 129 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6365313 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 29 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 1 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T81 0 1 0 0
T99 453 0 0 0
T138 0 1 0 0
T139 0 1 0 0
T147 0 1 0 0
T159 0 4 0 0
T170 0 1 0 0
T199 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464495.65
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323093.75
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 0 1
187 0 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211885.71
Logical211885.71
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT2,T13,T3
1CoveredT1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT2,T13,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT10,T12,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T4,T5 VC_COV_UNR
1CoveredT10,T12,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT10,T12,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT7,T10,T12
10CoveredT2,T13,T3
11CoveredT10,T12,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT10,T12,T37
01Not Covered
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT10,T12,T37
01CoveredT12,T159,T182
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT10,T12,T37
1-CoveredT12,T159,T182

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 5 83.33
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T10,T12,T37
DetectSt 168 Covered T10,T12,T37
IdleSt 163 Covered T1,T4,T5
StableSt 191 Covered T10,T12,T37


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T10,T12,T37
DebounceSt->IdleSt 163 Covered T73,T138,T74
DetectSt->IdleSt 186 Not Covered
DetectSt->StableSt 191 Covered T10,T12,T37
IdleSt->DebounceSt 148 Covered T10,T12,T37
StableSt->IdleSt 206 Covered T12,T37,T159



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T10,T12,T37
0 1 Covered T10,T12,T37
0 0 Excluded T1,T4,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T10,T12,T37
0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T10,T12,T37
IdleSt 0 - - - - - - Covered T1,T4,T5
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T10,T12,T37
DebounceSt - 0 1 0 - - - Covered T138,T145
DebounceSt - 0 0 - - - - Covered T10,T12,T37
DetectSt - - - - 1 - - Not Covered
DetectSt - - - - 0 1 - Covered T10,T12,T37
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T12,T159,T182
StableSt - - - - - - 0 Covered T10,T12,T37
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 15 93.75
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 15 93.75




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7040575 74 0 0
CntIncr_A 7040575 2013 0 0
CntNoWrap_A 7040575 6362859 0 0
DetectStDropOut_A 7040575 0 0 0
DetectedOut_A 7040575 1960 0 0
DetectedPulseOut_A 7040575 35 0 0
DisabledIdleSt_A 7040575 6152912 0 0
DisabledNoDetection_A 7040575 6155234 0 0
EnterDebounceSt_A 7040575 39 0 0
EnterDetectSt_A 7040575 35 0 0
EnterStableSt_A 7040575 35 0 0
PulseIsPulse_A 7040575 35 0 0
StayInStableSt 7040575 1900 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7040575 6392 0 0
gen_low_level_sva.LowLevelEvent_A 7040575 6365313 0 0
gen_not_sticky_sva.StableStDropOut_A 7040575 10 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 74 0 0
T10 759 2 0 0
T11 12069 0 0 0
T12 1213 4 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 2 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T73 0 1 0 0
T81 0 2 0 0
T99 453 0 0 0
T137 0 2 0 0
T138 0 1 0 0
T146 0 2 0 0
T147 0 2 0 0
T159 0 4 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 2013 0 0
T10 759 84 0 0
T11 12069 0 0 0
T12 1213 200 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 53 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T73 0 17 0 0
T81 0 74 0 0
T99 453 0 0 0
T137 0 81 0 0
T138 0 41 0 0
T146 0 67 0 0
T147 0 24 0 0
T159 0 132 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6362859 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 1960 0 0
T10 759 39 0 0
T11 12069 0 0 0
T12 1213 83 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 43 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T78 0 148 0 0
T81 0 115 0 0
T99 453 0 0 0
T137 0 44 0 0
T146 0 42 0 0
T147 0 40 0 0
T159 0 76 0 0
T160 0 43 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 35 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 1 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T78 0 1 0 0
T81 0 1 0 0
T99 453 0 0 0
T137 0 1 0 0
T146 0 1 0 0
T147 0 1 0 0
T159 0 2 0 0
T160 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6152912 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6155234 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 39 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 1 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T73 0 1 0 0
T81 0 1 0 0
T99 453 0 0 0
T137 0 1 0 0
T138 0 1 0 0
T146 0 1 0 0
T147 0 1 0 0
T159 0 2 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 35 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 1 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T78 0 1 0 0
T81 0 1 0 0
T99 453 0 0 0
T137 0 1 0 0
T146 0 1 0 0
T147 0 1 0 0
T159 0 2 0 0
T160 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 35 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 1 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T78 0 1 0 0
T81 0 1 0 0
T99 453 0 0 0
T137 0 1 0 0
T146 0 1 0 0
T147 0 1 0 0
T159 0 2 0 0
T160 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 35 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 1 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T78 0 1 0 0
T81 0 1 0 0
T99 453 0 0 0
T137 0 1 0 0
T146 0 1 0 0
T147 0 1 0 0
T159 0 2 0 0
T160 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 1900 0 0
T10 759 37 0 0
T11 12069 0 0 0
T12 1213 80 0 0
T20 487 0 0 0
T22 561 0 0 0
T27 4716 0 0 0
T37 0 41 0 0
T59 695 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T78 0 146 0 0
T81 0 113 0 0
T99 453 0 0 0
T137 0 42 0 0
T146 0 40 0 0
T147 0 38 0 0
T159 0 73 0 0
T160 0 41 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6392 0 0
T2 22284 11 0 0
T3 12531 40 0 0
T6 1487 0 0 0
T7 0 17 0 0
T13 456 1 0 0
T14 493 6 0 0
T15 436 1 0 0
T16 411 1 0 0
T21 502 5 0 0
T26 5267 29 0 0
T52 448 7 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6365313 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 10 0 0
T12 1213 1 0 0
T20 487 0 0 0
T22 561 0 0 0
T23 3297 0 0 0
T31 30619 0 0 0
T38 604 0 0 0
T53 427 0 0 0
T64 523 0 0 0
T65 526 0 0 0
T99 453 0 0 0
T158 0 1 0 0
T159 0 1 0 0
T164 0 1 0 0
T170 0 1 0 0
T182 0 1 0 0
T203 0 1 0 0
T204 0 2 0 0
T224 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
TOTAL4646100.00
CONT_ASSIGN6011100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS1253232100.00
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
60 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 1 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT1,T2,T3

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T4,T5
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT7,T10,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T4,T5 VC_COV_UNR
1CoveredT7,T10,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT7,T10,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT7,T10,T12
10CoveredT1,T2,T3
11CoveredT7,T10,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT7,T10,T12
01CoveredT81,T221
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT7,T10,T12
01CoveredT7,T10,T12
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT7,T10,T12
1-CoveredT7,T10,T12

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T7,T10,T12
DetectSt 168 Covered T7,T10,T12
IdleSt 163 Covered T1,T4,T5
StableSt 191 Covered T7,T10,T12


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T7,T10,T12
DebounceSt->IdleSt 163 Covered T73,T74,T221
DetectSt->IdleSt 186 Covered T81,T221
DetectSt->StableSt 191 Covered T7,T10,T12
IdleSt->DebounceSt 148 Covered T7,T10,T12
StableSt->IdleSt 206 Covered T7,T10,T12



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
Line No.TotalCoveredPercent
Branches 20 20 100.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 10 100.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T7,T10,T12
0 1 Covered T7,T10,T12
0 0 Excluded T1,T4,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T7,T10,T12
0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T7,T10,T12
IdleSt 0 - - - - - - Covered T1,T2,T3
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T7,T10,T12
DebounceSt - 0 1 0 - - - Covered T136,T224
DebounceSt - 0 0 - - - - Covered T7,T10,T12
DetectSt - - - - 1 - - Covered T81,T221
DetectSt - - - - 0 1 - Covered T7,T10,T12
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T7,T10,T12
StableSt - - - - - - 0 Covered T7,T10,T12
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 15 15 100.00 15 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 15 15 100.00 15 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7040575 102 0 0
CntIncr_A 7040575 58035 0 0
CntNoWrap_A 7040575 6362831 0 0
DetectStDropOut_A 7040575 2 0 0
DetectedOut_A 7040575 4083 0 0
DetectedPulseOut_A 7040575 47 0 0
DisabledIdleSt_A 7040575 6155786 0 0
DisabledNoDetection_A 7040575 6158121 0 0
EnterDebounceSt_A 7040575 54 0 0
EnterDetectSt_A 7040575 49 0 0
EnterStableSt_A 7040575 47 0 0
PulseIsPulse_A 7040575 47 0 0
StayInStableSt 7040575 4011 0 0
gen_high_level_sva.HighLevelEvent_A 7040575 6365313 0 0
gen_not_sticky_sva.StableStDropOut_A 7040575 22 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 102 0 0
T7 25889 4 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 2 0 0
T11 12069 0 0 0
T12 1213 2 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 2 0 0
T39 0 2 0 0
T49 0 2 0 0
T59 695 0 0 0
T62 0 2 0 0
T73 0 1 0 0
T90 0 4 0 0
T99 453 0 0 0
T159 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 58035 0 0
T7 25889 40 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 84 0 0
T11 12069 0 0 0
T12 1213 100 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 32 0 0
T39 0 47 0 0
T49 0 73 0 0
T59 695 0 0 0
T62 0 79 0 0
T73 0 16 0 0
T90 0 48 0 0
T99 453 0 0 0
T159 0 22 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6362831 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 2 0 0
T78 13254 0 0 0
T81 852 1 0 0
T123 503 0 0 0
T124 498 0 0 0
T125 407 0 0 0
T126 502 0 0 0
T127 701 0 0 0
T128 422 0 0 0
T129 484 0 0 0
T130 5317 0 0 0
T221 0 1 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 4083 0 0
T7 25889 86 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 44 0 0
T11 12069 0 0 0
T12 1213 563 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 109 0 0
T39 0 46 0 0
T49 0 43 0 0
T59 695 0 0 0
T62 0 51 0 0
T90 0 87 0 0
T99 453 0 0 0
T138 0 279 0 0
T159 0 65 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 47 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 1 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T62 0 1 0 0
T90 0 2 0 0
T99 453 0 0 0
T138 0 1 0 0
T159 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6155786 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6158121 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 54 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 1 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T62 0 1 0 0
T73 0 1 0 0
T90 0 2 0 0
T99 453 0 0 0
T159 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 49 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 1 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T62 0 1 0 0
T90 0 2 0 0
T99 453 0 0 0
T138 0 1 0 0
T159 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 47 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 1 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T62 0 1 0 0
T90 0 2 0 0
T99 453 0 0 0
T138 0 1 0 0
T159 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 47 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 1 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 1 0 0
T39 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T62 0 1 0 0
T90 0 2 0 0
T99 453 0 0 0
T138 0 1 0 0
T159 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 4011 0 0
T7 25889 84 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 43 0 0
T11 12069 0 0 0
T12 1213 562 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 108 0 0
T39 0 44 0 0
T49 0 42 0 0
T59 695 0 0 0
T62 0 49 0 0
T90 0 84 0 0
T99 453 0 0 0
T138 0 277 0 0
T159 0 63 0 0

gen_high_level_sva.HighLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6365313 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 22 0 0
T7 25889 2 0 0
T8 62662 0 0 0
T9 1525 0 0 0
T10 759 1 0 0
T11 12069 0 0 0
T12 1213 1 0 0
T22 561 0 0 0
T27 4716 0 0 0
T36 0 1 0 0
T49 0 1 0 0
T59 695 0 0 0
T81 0 1 0 0
T90 0 1 0 0
T99 453 0 0 0
T171 0 2 0 0
T172 0 1 0 0
T225 0 1 0 0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
TOTAL464597.83
CONT_ASSIGN5811100.00
ALWAYS6933100.00
CONT_ASSIGN7611100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10111100.00
ALWAYS10433100.00
ALWAYS125323196.88
ALWAYS21933100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
58 1 1
69 1 1
70 1 1
72 1 1
76 1 1
92 1 1
99 1 1
101 1 1
104 1 1
105 1 1
107 1 1
125 1 1
128 1 1
129 1 1
132 1 1
133 1 1
138 1 1
140 1 1
147 1 1
148 1 1
149 1 1
MISSING_ELSE
160 1 1
162 1 1
163 1 1
164 1 1
165 1 1
166 1 1
167 1 1
168 1 1
170 0 1
MISSING_ELSE
181 1 1
182 1 1
185 1 1
186 1 1
187 1 1
190 1 1
191 1 1
192 1 1
193 1 1
194 1 1
==> MISSING_ELSE
205 1 1
206 1 1
209 1 1
Exclude Annotation: VC_COV_UNR
219 1 1
220 1 1
222 1 1


Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalCoveredPercent
Conditions211990.48
Logical211990.48
Non-Logical00
Event00

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T4,T5
11CoveredT1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--
-1-StatusTestsExclude Annotation
0ExcludedT1,T4,T5 VC_COV_UNR
1CoveredT34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----
-1-StatusTests
0CoveredT1,T4,T5
1CoveredT34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----
-1--2-StatusTests
01CoveredT38,T34,T35
10CoveredT1,T2,T3
11CoveredT34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------
-1--2-StatusTests
00CoveredT34,T35,T36
01CoveredT171
10Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------
-1--2-StatusTests
00CoveredT34,T35,T36
01CoveredT34,T35,T159
10Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----
-1--2-StatusTests
0-CoveredT34,T35,T36
1-CoveredT34,T35,T159

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Summary for FSM :: state_q
TotalCoveredPercent
States 4 4 100.00 (Not included in score)
Transitions 6 6 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
DebounceSt 148 Covered T34,T35,T36
DetectSt 168 Covered T34,T35,T36
IdleSt 163 Covered T1,T4,T5
StableSt 191 Covered T34,T35,T36


transitionsLine No.CoveredTests
DebounceSt->DetectSt 168 Covered T34,T35,T36
DebounceSt->IdleSt 163 Covered T73,T74
DetectSt->IdleSt 186 Covered T171
DetectSt->StableSt 191 Covered T34,T35,T36
IdleSt->DebounceSt 148 Covered T34,T35,T36
StableSt->IdleSt 206 Covered T34,T35,T159



Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
Line No.TotalCoveredPercent
Branches 20 19 95.00
TERNARY 92 2 2 100.00
TERNARY 99 2 2 100.00
IF 104 2 2 100.00
CASE 140 10 9 90.00
IF 219 2 2 100.00
IF 69 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 92 (cnt_clr) ? -2-: 92 (cnt_en) ?

Branches:
-1--2-StatusTestsExclude Annotation
1 - Covered T34,T35,T36
0 1 Covered T34,T35,T36
0 0 Excluded T1,T4,T5 VC_COV_UNR


LineNo. Expression -1-: 99 (thresh_sel) ?

Branches:
-1-StatusTests
1 Covered T34,T35,T36
0 Covered T1,T4,T5


LineNo. Expression -1-: 104 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 140 case (state_q) -2-: 147 if ((trigger_event && cfg_enable_i)) -3-: 162 if ((!cfg_enable_i)) -4-: 165 if (cnt_done) -5-: 167 if (trigger_active) -6-: 185 if (((!cfg_enable_i) || (!trigger_active))) -7-: 190 if (cnt_done) -8-: 205 if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:
-1--2--3--4--5--6--7--8-StatusTestsExclude Annotation
IdleSt 1 - - - - - - Covered T34,T35,T36
IdleSt 0 - - - - - - Covered T1,T4,T5
DebounceSt - 1 - - - - - Covered T73,T74
DebounceSt - 0 1 1 - - - Covered T34,T35,T36
DebounceSt - 0 1 0 - - - Not Covered
DebounceSt - 0 0 - - - - Covered T34,T35,T36
DetectSt - - - - 1 - - Covered T171
DetectSt - - - - 0 1 - Covered T34,T35,T36
DetectSt - - - - 0 0 - Excluded VC_COV_UNR
StableSt - - - - - - 1 Covered T34,T35,T159
StableSt - - - - - - 0 Covered T34,T35,T36
default - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 219 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


LineNo. Expression -1-: 69 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T4,T5
0 Covered T1,T4,T5


Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 16 16 100.00 16 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 16 16 100.00 16 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CntClr_A 7040575 64 0 0
CntIncr_A 7040575 56781 0 0
CntNoWrap_A 7040575 6362869 0 0
DetectStDropOut_A 7040575 1 0 0
DetectedOut_A 7040575 2598 0 0
DetectedPulseOut_A 7040575 30 0 0
DisabledIdleSt_A 7040575 6116762 0 0
DisabledNoDetection_A 7040575 6119093 0 0
EnterDebounceSt_A 7040575 33 0 0
EnterDetectSt_A 7040575 31 0 0
EnterStableSt_A 7040575 30 0 0
PulseIsPulse_A 7040575 30 0 0
StayInStableSt 7040575 2550 0 0
gen_edge_to_low_event_sva.EdgeToLowEvent_A 7040575 7044 0 0
gen_low_level_sva.LowLevelEvent_A 7040575 6365313 0 0
gen_not_sticky_sva.StableStDropOut_A 7040575 12 0 0


CntClr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 64 0 0
T34 11206 2 0 0
T35 15294 4 0 0
T36 0 2 0 0
T37 31062 0 0 0
T73 0 1 0 0
T81 0 4 0 0
T90 0 2 0 0
T105 11942 0 0 0
T139 0 2 0 0
T159 0 2 0 0
T171 0 2 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 2 0 0

CntIncr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 56781 0 0
T34 11206 44 0 0
T35 15294 124 0 0
T36 0 32 0 0
T37 31062 0 0 0
T73 0 15 0 0
T81 0 148 0 0
T90 0 24 0 0
T105 11942 0 0 0
T139 0 32 0 0
T159 0 66 0 0
T171 0 44 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 38 0 0

CntNoWrap_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6362869 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DetectStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 1 0 0
T171 31500 1 0 0
T227 403 0 0 0
T228 425 0 0 0
T229 1759 0 0 0
T230 405 0 0 0
T231 2476 0 0 0
T232 49257 0 0 0
T233 425 0 0 0
T234 525 0 0 0
T235 17508 0 0 0

DetectedOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 2598 0 0
T34 11206 127 0 0
T35 15294 82 0 0
T36 0 41 0 0
T37 31062 0 0 0
T81 0 83 0 0
T90 0 97 0 0
T105 11942 0 0 0
T139 0 73 0 0
T140 0 16 0 0
T159 0 153 0 0
T172 0 212 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 39 0 0

DetectedPulseOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 30 0 0
T34 11206 1 0 0
T35 15294 2 0 0
T36 0 1 0 0
T37 31062 0 0 0
T81 0 2 0 0
T90 0 1 0 0
T105 11942 0 0 0
T139 0 1 0 0
T140 0 1 0 0
T159 0 1 0 0
T172 0 1 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 1 0 0

DisabledIdleSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6116762 0 0
T1 1205 804 0 0
T2 22284 21824 0 0
T3 12531 4844 0 0
T4 402 1 0 0
T5 527 126 0 0
T6 1487 1086 0 0
T13 456 55 0 0
T14 493 92 0 0
T15 436 35 0 0
T16 411 10 0 0

DisabledNoDetection_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6119093 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

EnterDebounceSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 33 0 0
T34 11206 1 0 0
T35 15294 2 0 0
T36 0 1 0 0
T37 31062 0 0 0
T73 0 1 0 0
T81 0 2 0 0
T90 0 1 0 0
T105 11942 0 0 0
T139 0 1 0 0
T159 0 1 0 0
T171 0 1 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 1 0 0

EnterDetectSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 31 0 0
T34 11206 1 0 0
T35 15294 2 0 0
T36 0 1 0 0
T37 31062 0 0 0
T81 0 2 0 0
T90 0 1 0 0
T105 11942 0 0 0
T139 0 1 0 0
T159 0 1 0 0
T171 0 1 0 0
T172 0 1 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 1 0 0

EnterStableSt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 30 0 0
T34 11206 1 0 0
T35 15294 2 0 0
T36 0 1 0 0
T37 31062 0 0 0
T81 0 2 0 0
T90 0 1 0 0
T105 11942 0 0 0
T139 0 1 0 0
T140 0 1 0 0
T159 0 1 0 0
T172 0 1 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 1 0 0

PulseIsPulse_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 30 0 0
T34 11206 1 0 0
T35 15294 2 0 0
T36 0 1 0 0
T37 31062 0 0 0
T81 0 2 0 0
T90 0 1 0 0
T105 11942 0 0 0
T139 0 1 0 0
T140 0 1 0 0
T159 0 1 0 0
T172 0 1 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 1 0 0

StayInStableSt
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 2550 0 0
T34 11206 126 0 0
T35 15294 79 0 0
T36 0 39 0 0
T37 31062 0 0 0
T81 0 80 0 0
T90 0 96 0 0
T105 11942 0 0 0
T139 0 72 0 0
T140 0 15 0 0
T159 0 152 0 0
T172 0 210 0 0
T174 900 0 0 0
T175 410 0 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0
T226 0 37 0 0

gen_edge_to_low_event_sva.EdgeToLowEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 7044 0 0
T1 1205 8 0 0
T2 22284 12 0 0
T3 12531 39 0 0
T4 402 0 0 0
T5 527 0 0 0
T6 1487 5 0 0
T7 0 16 0 0
T13 456 0 0 0
T14 493 8 0 0
T15 436 2 0 0
T16 411 0 0 0
T21 0 5 0 0
T26 0 22 0 0
T52 0 8 0 0

gen_low_level_sva.LowLevelEvent_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 6365313 0 0
T1 1205 805 0 0
T2 22284 21833 0 0
T3 12531 4868 0 0
T4 402 2 0 0
T5 527 127 0 0
T6 1487 1087 0 0
T13 456 56 0 0
T14 493 93 0 0
T15 436 36 0 0
T16 411 11 0 0

gen_not_sticky_sva.StableStDropOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 7040575 12 0 0
T34 11206 1 0 0
T35 15294 1 0 0
T37 31062 0 0 0
T81 0 1 0 0
T90 0 1 0 0
T105 11942 0 0 0
T121 0 1 0 0
T139 0 1 0 0
T140 0 1 0 0
T159 0 1 0 0
T174 900 0 0 0
T175 410 0 0 0
T180 0 1 0 0
T204 0 3 0 0
T206 507 0 0 0
T207 444 0 0 0
T208 405 0 0 0
T209 543 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%