Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T26,T27,T11
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T13,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T11
1	0	Covered	T11,T43,T44
1	1	Covered	T13,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T26,T27
0	1	Covered	T26,T27,T43
1	0	Covered	T43,T44,T41

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T11,T40
0	1	Covered	T11,T68,T69
1	0	Covered	T236

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T11,T40
1	-	Covered	T11,T68,T69

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T26,T27
DetectSt	168	Covered	T13,T26,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T13,T11,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T26,T27
DebounceSt->IdleSt	163	Covered	T237,T73,T238
DetectSt->IdleSt	186	Covered	T26,T27,T43
DetectSt->StableSt	191	Covered	T13,T11,T40
IdleSt->DebounceSt	148	Covered	T13,T26,T27
StableSt->IdleSt	206	Covered	T11,T68,T69

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T13,T26,T27
0	1	Covered	T13,T26,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T26,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T13,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T26,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T237,T73,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T27,T43
DetectSt	-	-	-	-	0	1	-	Covered	T13,T11,T40
DetectSt	-	-	-	-	0	0	-	Covered	T13,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T11,T68,T69
StableSt	-	-	-	-	-	-	0	Covered	T13,T11,T40
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	2729	0	0
CntIncr_A	7040575	99907	0	0
CntNoWrap_A	7040575	6360204	0	0
DetectStDropOut_A	7040575	359	0	0
DetectedOut_A	7040575	76456	0	0
DetectedPulseOut_A	7040575	861	0	0
DisabledIdleSt_A	7040575	5890933	0	0
DisabledNoDetection_A	7040575	5893125	0	0
EnterDebounceSt_A	7040575	1398	0	0
EnterDetectSt_A	7040575	1332	0	0
EnterStableSt_A	7040575	861	0	0
PulseIsPulse_A	7040575	861	0	0
StayInStableSt	7040575	75497	0	0
gen_high_event_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	762	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	2729	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	36	0	0
T13	456	2	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	58	0	0
T27	0	22	0	0
T40	0	2	0	0
T41	0	4	0	0
T43	0	48	0	0
T44	0	22	0	0
T52	448	0	0	0
T68	0	48	0	0
T69	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	99907	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	1170	0	0
T13	456	21	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	1537	0	0
T27	0	456	0	0
T40	0	21	0	0
T41	0	125	0	0
T43	0	1355	0	0
T44	0	549	0	0
T52	448	0	0	0
T68	0	1296	0	0
T69	0	265	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6360204	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	53	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	359	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T26	5267	29	0	0
T27	4716	11	0	0
T43	0	12	0	0
T44	0	8	0	0
T52	448	0	0	0
T59	695	0	0	0
T70	0	1	0	0
T88	0	14	0	0
T89	0	1	0	0
T130	0	13	0	0
T239	0	2	0	0
T240	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	76456	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	537	0	0
T13	456	30	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T40	0	25	0	0
T42	0	644	0	0
T52	448	0	0	0
T68	0	1404	0	0
T69	0	844	0	0
T237	0	287	0	0
T241	0	88	0	0
T242	0	1315	0	0
T243	0	2894	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	861	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	18	0	0
T13	456	1	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T40	0	1	0	0
T42	0	5	0	0
T52	448	0	0	0
T68	0	24	0	0
T69	0	5	0	0
T237	0	6	0	0
T241	0	4	0	0
T242	0	13	0	0
T243	0	22	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5890933	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	4	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5893125	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	4	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1398	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	18	0	0
T13	456	1	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	29	0	0
T27	0	11	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	24	0	0
T44	0	11	0	0
T52	448	0	0	0
T68	0	24	0	0
T69	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1332	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	18	0	0
T13	456	1	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	29	0	0
T27	0	11	0	0
T40	0	1	0	0
T41	0	2	0	0
T43	0	24	0	0
T44	0	11	0	0
T52	448	0	0	0
T68	0	24	0	0
T69	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	861	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	18	0	0
T13	456	1	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T40	0	1	0	0
T42	0	5	0	0
T52	448	0	0	0
T68	0	24	0	0
T69	0	5	0	0
T237	0	6	0	0
T241	0	4	0	0
T242	0	13	0	0
T243	0	22	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	861	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	18	0	0
T13	456	1	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T40	0	1	0	0
T42	0	5	0	0
T52	448	0	0	0
T68	0	24	0	0
T69	0	5	0	0
T237	0	6	0	0
T241	0	4	0	0
T242	0	13	0	0
T243	0	22	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	75497	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	25889	0	0	0
T11	0	518	0	0
T13	456	28	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T40	0	23	0	0
T42	0	637	0	0
T52	448	0	0	0
T68	0	1380	0	0
T69	0	836	0	0
T237	0	281	0	0
T241	0	84	0	0
T242	0	1298	0	0
T243	0	2869	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	762	0	0
T11	12069	17	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	3	0	0
T64	523	0	0	0
T65	526	0	0	0
T68	0	24	0	0
T69	0	2	0	0
T73	0	5	0	0
T99	453	0	0	0
T237	0	6	0	0
T241	0	4	0	0
T242	0	9	0	0
T243	0	19	0	0
T244	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T13,T3
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T3
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T13,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T13,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T3,T26
1	1	Covered	T2,T13,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T7,T34,T37
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T11
0	1	Covered	T2,T3,T31
1	0	Covered	T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T11
1	-	Covered	T2,T3,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T13,T3
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T3,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T13,T23,T32
DetectSt->IdleSt	186	Covered	T3,T7,T34
DetectSt->StableSt	191	Covered	T2,T3,T11
IdleSt->DebounceSt	148	Covered	T2,T13,T3
StableSt->IdleSt	206	Covered	T2,T3,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T13,T3
0	1	Covered	T2,T13,T3
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T13,T3
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T23,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T13,T3
DetectSt	-	-	-	-	1	-	-	Covered	T7,T34,T37
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T11
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T31
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	943	0	0
CntIncr_A	7040575	49532	0	0
CntNoWrap_A	7040575	6361990	0	0
DetectStDropOut_A	7040575	51	0	0
DetectedOut_A	7040575	13860	0	0
DetectedPulseOut_A	7040575	379	0	0
DisabledIdleSt_A	7040575	5967761	0	0
DisabledNoDetection_A	7040575	5969406	0	0
EnterDebounceSt_A	7040575	511	0	0
EnterDetectSt_A	7040575	436	0	0
EnterStableSt_A	7040575	379	0	0
PulseIsPulse_A	7040575	379	0	0
StayInStableSt	7040575	13457	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	353	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	943	0	0
T2	22284	12	0	0
T3	12531	5	0	0
T6	1487	0	0	0
T7	0	12	0	0
T11	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T23	0	1	0	0
T26	5267	0	0	0
T31	0	16	0	0
T32	0	11	0	0
T33	0	2	0	0
T34	0	2	0	0
T37	0	4	0	0
T52	448	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	49532	0	0
T2	22284	636	0	0
T3	12531	322	0	0
T6	1487	0	0	0
T7	0	578	0	0
T11	0	45	0	0
T13	456	20	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T23	0	20	0	0
T26	5267	0	0	0
T31	0	720	0	0
T32	0	553	0	0
T33	0	143	0	0
T34	0	20	0	0
T52	448	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6361990	0	0
T1	1205	804	0	0
T2	22284	21812	0	0
T3	12531	4839	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	51	0	0
T7	25889	6	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T59	695	0	0	0
T87	0	1	0	0
T90	0	4	0	0
T91	0	7	0	0
T92	0	6	0	0
T93	0	7	0	0
T95	0	2	0	0
T96	0	1	0	0
T99	453	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	13860	0	0
T2	22284	115	0	0
T3	12531	6	0	0
T6	1487	0	0	0
T11	0	55	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	112	0	0
T32	0	357	0	0
T33	0	35	0	0
T52	448	0	0	0
T105	0	48	0	0
T106	0	3	0	0
T107	0	123	0	0
T108	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	379	0	0
T2	22284	6	0	0
T3	12531	2	0	0
T6	1487	0	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	8	0	0
T32	0	5	0	0
T33	0	1	0	0
T52	448	0	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	4	0	0
T108	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5967761	0	0
T1	1205	804	0	0
T2	22284	18132	0	0
T3	12531	4412	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	26	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5969406	0	0
T1	1205	805	0	0
T2	22284	18132	0	0
T3	12531	4433	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	26	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	511	0	0
T2	22284	6	0	0
T3	12531	3	0	0
T6	1487	0	0	0
T7	0	6	0	0
T11	0	1	0	0
T13	456	1	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T23	0	1	0	0
T26	5267	0	0	0
T31	0	8	0	0
T32	0	6	0	0
T33	0	1	0	0
T34	0	1	0	0
T52	448	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	436	0	0
T2	22284	6	0	0
T3	12531	3	0	0
T6	1487	0	0	0
T7	0	6	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	8	0	0
T32	0	5	0	0
T33	0	1	0	0
T34	0	1	0	0
T37	0	2	0	0
T52	448	0	0	0
T105	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	379	0	0
T2	22284	6	0	0
T3	12531	2	0	0
T6	1487	0	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	8	0	0
T32	0	5	0	0
T33	0	1	0	0
T52	448	0	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	4	0	0
T108	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	379	0	0
T2	22284	6	0	0
T3	12531	2	0	0
T6	1487	0	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	8	0	0
T32	0	5	0	0
T33	0	1	0	0
T52	448	0	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	4	0	0
T108	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	13457	0	0
T2	22284	109	0	0
T3	12531	4	0	0
T6	1487	0	0	0
T11	0	53	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	104	0	0
T32	0	352	0	0
T33	0	34	0	0
T52	448	0	0	0
T105	0	45	0	0
T106	0	2	0	0
T107	0	119	0	0
T108	0	83	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	353	0	0
T2	22284	6	0	0
T3	12531	2	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	8	0	0
T32	0	5	0	0
T33	0	1	0	0
T52	448	0	0	0
T105	0	3	0	0
T106	0	1	0	0
T107	0	4	0	0
T108	0	2	0	0
T110	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T26,T27,T11
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T11
1	0	Covered	T11,T43,T44
1	1	Covered	T26,T27,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T11
0	1	Covered	T26,T27,T44
1	0	Covered	T43,T44,T68

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T41,T70
0	1	Covered	T11,T41,T70
1	0	Covered	T42,T73,T245

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T41,T42
1	-	Covered	T11,T41,T70

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T27,T11
DetectSt	168	Covered	T26,T27,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T27,T11
DebounceSt->IdleSt	163	Covered	T237,T73,T238
DetectSt->IdleSt	186	Covered	T26,T27,T43
DetectSt->StableSt	191	Covered	T11,T41,T42
IdleSt->DebounceSt	148	Covered	T26,T27,T11
StableSt->IdleSt	206	Covered	T11,T41,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T11
0	1	Covered	T26,T27,T11
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T26,T27,T11
IdleSt	0	-	-	-	-	-	-	Covered	T26,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T27,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T237,T73,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T27,T11
DetectSt	-	-	-	-	1	-	-	Covered	T26,T27,T43
DetectSt	-	-	-	-	0	1	-	Covered	T11,T41,T42
DetectSt	-	-	-	-	0	0	-	Covered	T26,T27,T11
StableSt	-	-	-	-	-	-	1	Covered	T11,T41,T42
StableSt	-	-	-	-	-	-	0	Covered	T11,T41,T70
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	2997	0	0
CntIncr_A	7040575	117042	0	0
CntNoWrap_A	7040575	6359936	0	0
DetectStDropOut_A	7040575	461	0	0
DetectedOut_A	7040575	68299	0	0
DetectedPulseOut_A	7040575	787	0	0
DisabledIdleSt_A	7040575	5896557	0	0
DisabledNoDetection_A	7040575	5898763	0	0
EnterDebounceSt_A	7040575	1536	0	0
EnterDetectSt_A	7040575	1463	0	0
EnterStableSt_A	7040575	787	0	0
PulseIsPulse_A	7040575	787	0	0
StayInStableSt	7040575	67428	0	0
gen_high_event_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	649	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	2997	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	24	0	0
T12	1213	0	0	0
T26	5267	56	0	0
T27	4716	50	0	0
T41	0	48	0	0
T42	0	40	0	0
T43	0	40	0	0
T44	0	12	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	54	0	0
T69	0	18	0	0
T70	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	117042	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	924	0	0
T12	1213	0	0	0
T26	5267	1486	0	0
T27	4716	1049	0	0
T41	0	1464	0	0
T42	0	2290	0	0
T43	0	1138	0	0
T44	0	302	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	1469	0	0
T69	0	517	0	0
T70	0	407	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6359936	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	461	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T26	5267	28	0	0
T27	4716	25	0	0
T42	0	6	0	0
T44	0	2	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	17	0	0
T69	0	7	0	0
T73	0	1	0	0
T88	0	26	0	0
T89	0	7	0	0
T241	0	17	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	68299	0	0
T11	12069	79	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	1943	0	0
T42	0	1	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	446	0	0
T73	0	313	0	0
T99	453	0	0	0
T237	0	281	0	0
T242	0	2265	0	0
T243	0	2542	0	0
T244	0	2220	0	0
T246	0	111	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	787	0	0
T11	12069	12	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	24	0	0
T42	0	1	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	11	0	0
T73	0	5	0	0
T99	453	0	0	0
T237	0	6	0	0
T242	0	21	0	0
T243	0	22	0	0
T244	0	23	0	0
T246	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5896557	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5898763	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1536	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	12	0	0
T12	1213	0	0	0
T26	5267	28	0	0
T27	4716	25	0	0
T41	0	24	0	0
T42	0	20	0	0
T43	0	20	0	0
T44	0	6	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	27	0	0
T69	0	9	0	0
T70	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1463	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	12	0	0
T12	1213	0	0	0
T26	5267	28	0	0
T27	4716	25	0	0
T41	0	24	0	0
T42	0	20	0	0
T43	0	20	0	0
T44	0	6	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	27	0	0
T69	0	9	0	0
T70	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	787	0	0
T11	12069	12	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	24	0	0
T42	0	1	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	11	0	0
T73	0	5	0	0
T99	453	0	0	0
T237	0	6	0	0
T242	0	21	0	0
T243	0	22	0	0
T244	0	23	0	0
T246	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	787	0	0
T11	12069	12	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	24	0	0
T42	0	1	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	11	0	0
T73	0	5	0	0
T99	453	0	0	0
T237	0	6	0	0
T242	0	21	0	0
T243	0	22	0	0
T244	0	23	0	0
T246	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	67428	0	0
T11	12069	67	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	1916	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	434	0	0
T73	0	308	0	0
T99	453	0	0	0
T237	0	275	0	0
T242	0	2241	0	0
T243	0	2517	0	0
T244	0	2195	0	0
T246	0	109	0	0
T247	0	1752	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	649	0	0
T11	12069	12	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	21	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	10	0	0
T73	0	4	0	0
T99	453	0	0	0
T237	0	6	0	0
T242	0	18	0	0
T243	0	19	0	0
T244	0	21	0	0
T246	0	2	0	0
T247	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T26
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T26
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T3,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T3,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T26
1	1	Covered	T2,T3,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T7
0	1	Covered	T7,T49,T90
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T31,T32
0	1	Covered	T2,T31,T32
1	0	Covered	T73

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T31,T32
1	-	Covered	T2,T31,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T7
DetectSt	168	Covered	T2,T3,T7
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T31,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T7
DebounceSt->IdleSt	163	Covered	T7,T31,T107
DetectSt->IdleSt	186	Covered	T3,T7,T49
DetectSt->StableSt	191	Covered	T2,T31,T32
IdleSt->DebounceSt	148	Covered	T2,T3,T7
StableSt->IdleSt	206	Covered	T2,T31,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T7
0	1	Covered	T2,T3,T7
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T31,T107
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T49,T73
DetectSt	-	-	-	-	0	1	-	Covered	T2,T31,T32
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T7
StableSt	-	-	-	-	-	-	1	Covered	T2,T31,T32
StableSt	-	-	-	-	-	-	0	Covered	T2,T31,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	890	0	0
CntIncr_A	7040575	50277	0	0
CntNoWrap_A	7040575	6362043	0	0
DetectStDropOut_A	7040575	87	0	0
DetectedOut_A	7040575	13068	0	0
DetectedPulseOut_A	7040575	334	0	0
DisabledIdleSt_A	7040575	5983364	0	0
DisabledNoDetection_A	7040575	5985099	0	0
EnterDebounceSt_A	7040575	465	0	0
EnterDetectSt_A	7040575	428	0	0
EnterStableSt_A	7040575	334	0	0
PulseIsPulse_A	7040575	334	0	0
StayInStableSt	7040575	12712	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	311	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	890	0	0
T2	22284	4	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	0	9	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	25	0	0
T32	0	12	0	0
T33	0	16	0	0
T37	0	8	0	0
T52	448	0	0	0
T87	0	2	0	0
T105	0	2	0	0
T107	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	50277	0	0
T2	22284	144	0	0
T3	12531	272	0	0
T6	1487	0	0	0
T7	0	421	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	1215	0	0
T32	0	750	0	0
T33	0	1368	0	0
T37	0	152	0	0
T52	448	0	0	0
T87	0	97	0	0
T105	0	99	0	0
T107	0	494	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362043	0	0
T1	1205	804	0	0
T2	22284	21820	0	0
T3	12531	4843	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	87	0	0
T7	25889	4	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T22	561	0	0	0
T27	4716	0	0	0
T49	0	5	0	0
T59	695	0	0	0
T90	0	4	0	0
T91	0	1	0	0
T99	453	0	0	0
T182	0	1	0	0
T248	0	4	0	0
T249	0	10	0	0
T250	0	3	0	0
T251	0	8	0	0
T252	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	13068	0	0
T2	22284	106	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	64	0	0
T32	0	261	0	0
T33	0	69	0	0
T37	0	21	0	0
T52	448	0	0	0
T87	0	14	0	0
T105	0	16	0	0
T107	0	437	0	0
T108	0	37	0	0
T110	0	317	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	334	0	0
T2	22284	2	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	12	0	0
T32	0	6	0	0
T33	0	8	0	0
T37	0	4	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	1	0	0
T107	0	8	0	0
T108	0	8	0	0
T110	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5983364	0	0
T1	1205	804	0	0
T2	22284	18132	0	0
T3	12531	4568	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5985099	0	0
T1	1205	805	0	0
T2	22284	18132	0	0
T3	12531	4591	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	465	0	0
T2	22284	2	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	0	5	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	13	0	0
T32	0	6	0	0
T33	0	8	0	0
T37	0	4	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	1	0	0
T107	0	10	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	428	0	0
T2	22284	2	0	0
T3	12531	1	0	0
T6	1487	0	0	0
T7	0	4	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	12	0	0
T32	0	6	0	0
T33	0	8	0	0
T37	0	4	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	1	0	0
T107	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	334	0	0
T2	22284	2	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	12	0	0
T32	0	6	0	0
T33	0	8	0	0
T37	0	4	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	1	0	0
T107	0	8	0	0
T108	0	8	0	0
T110	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	334	0	0
T2	22284	2	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	12	0	0
T32	0	6	0	0
T33	0	8	0	0
T37	0	4	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	1	0	0
T107	0	8	0	0
T108	0	8	0	0
T110	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	12712	0	0
T2	22284	104	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	52	0	0
T32	0	255	0	0
T33	0	61	0	0
T37	0	17	0	0
T52	448	0	0	0
T87	0	13	0	0
T105	0	15	0	0
T107	0	429	0	0
T108	0	29	0	0
T110	0	310	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	311	0	0
T2	22284	2	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	12	0	0
T32	0	6	0	0
T33	0	8	0	0
T37	0	4	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	1	0	0
T107	0	8	0	0
T108	0	8	0	0
T110	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T26,T27,T11
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T11
1	0	Covered	T11,T43,T44
1	1	Covered	T26,T27,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T11
0	1	Covered	T26,T27,T44
1	0	Covered	T44,T68,T69

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T43,T42
0	1	Covered	T11,T43,T42
1	0	Covered	T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T43,T42
1	-	Covered	T11,T43,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T27,T11
DetectSt	168	Covered	T26,T27,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T43,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T27,T11
DebounceSt->IdleSt	163	Covered	T237,T73,T238
DetectSt->IdleSt	186	Covered	T26,T27,T44
DetectSt->StableSt	191	Covered	T11,T43,T42
IdleSt->DebounceSt	148	Covered	T26,T27,T11
StableSt->IdleSt	206	Covered	T11,T43,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T11
0	1	Covered	T26,T27,T11
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T26,T27,T11
IdleSt	0	-	-	-	-	-	-	Covered	T26,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T27,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T237,T73,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T27,T11
DetectSt	-	-	-	-	1	-	-	Covered	T26,T27,T44
DetectSt	-	-	-	-	0	1	-	Covered	T11,T43,T42
DetectSt	-	-	-	-	0	0	-	Covered	T26,T27,T11
StableSt	-	-	-	-	-	-	1	Covered	T11,T43,T42
StableSt	-	-	-	-	-	-	0	Covered	T11,T43,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	2914	0	0
CntIncr_A	7040575	112660	0	0
CntNoWrap_A	7040575	6360019	0	0
DetectStDropOut_A	7040575	470	0	0
DetectedOut_A	7040575	79857	0	0
DetectedPulseOut_A	7040575	841	0	0
DisabledIdleSt_A	7040575	5886818	0	0
DisabledNoDetection_A	7040575	5888999	0	0
EnterDebounceSt_A	7040575	1487	0	0
EnterDetectSt_A	7040575	1429	0	0
EnterStableSt_A	7040575	841	0	0
PulseIsPulse_A	7040575	841	0	0
StayInStableSt	7040575	78908	0	0
gen_high_event_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	730	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	2914	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	50	0	0
T12	1213	0	0	0
T26	5267	58	0	0
T27	4716	42	0	0
T41	0	49	0	0
T42	0	28	0	0
T43	0	22	0	0
T44	0	14	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	54	0	0
T69	0	50	0	0
T70	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	112660	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	1400	0	0
T12	1213	0	0	0
T26	5267	1537	0	0
T27	4716	882	0	0
T41	0	1567	0	0
T42	0	1064	0	0
T43	0	550	0	0
T44	0	351	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	1469	0	0
T69	0	1434	0	0
T70	0	858	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6360019	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	470	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T26	5267	29	0	0
T27	4716	21	0	0
T41	0	10	0	0
T44	0	4	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	17	0	0
T69	0	23	0	0
T73	0	1	0	0
T88	0	27	0	0
T89	0	27	0	0
T239	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	79857	0	0
T11	12069	1733	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	2323	0	0
T43	0	1140	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	1097	0	0
T99	453	0	0	0
T237	0	352	0	0
T241	0	1447	0	0
T242	0	747	0	0
T243	0	434	0	0
T244	0	2149	0	0
T246	0	1323	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	841	0	0
T11	12069	25	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	14	0	0
T43	0	11	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	26	0	0
T99	453	0	0	0
T237	0	8	0	0
T241	0	14	0	0
T242	0	5	0	0
T243	0	13	0	0
T244	0	18	0	0
T246	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5886818	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5888999	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1487	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	25	0	0
T12	1213	0	0	0
T26	5267	29	0	0
T27	4716	21	0	0
T41	0	25	0	0
T42	0	14	0	0
T43	0	11	0	0
T44	0	7	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	27	0	0
T69	0	25	0	0
T70	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1429	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	25	0	0
T12	1213	0	0	0
T26	5267	29	0	0
T27	4716	21	0	0
T41	0	25	0	0
T42	0	14	0	0
T43	0	11	0	0
T44	0	7	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	27	0	0
T69	0	25	0	0
T70	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	841	0	0
T11	12069	25	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	14	0	0
T43	0	11	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	26	0	0
T99	453	0	0	0
T237	0	8	0	0
T241	0	14	0	0
T242	0	5	0	0
T243	0	13	0	0
T244	0	18	0	0
T246	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	841	0	0
T11	12069	25	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	14	0	0
T43	0	11	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	26	0	0
T99	453	0	0	0
T237	0	8	0	0
T241	0	14	0	0
T242	0	5	0	0
T243	0	13	0	0
T244	0	18	0	0
T246	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	78908	0	0
T11	12069	1707	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	2302	0	0
T43	0	1123	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	1070	0	0
T99	453	0	0	0
T237	0	344	0	0
T241	0	1429	0	0
T242	0	739	0	0
T243	0	421	0	0
T244	0	2128	0	0
T246	0	1308	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	730	0	0
T11	12069	24	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	7	0	0
T43	0	5	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	25	0	0
T99	453	0	0	0
T237	0	8	0	0
T241	0	10	0	0
T242	0	2	0	0
T243	0	13	0	0
T244	0	15	0	0
T246	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T26
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T26
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T26
1	1	Covered	T2,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T11
0	1	Covered	T31,T33,T108
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T11
0	1	Covered	T2,T7,T11
1	0	Covered	T73,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T11
1	-	Covered	T2,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T11
DetectSt	168	Covered	T2,T7,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T11
DebounceSt->IdleSt	163	Covered	T7,T11,T31
DetectSt->IdleSt	186	Covered	T31,T33,T108
DetectSt->StableSt	191	Covered	T2,T7,T11
IdleSt->DebounceSt	148	Covered	T2,T7,T11
StableSt->IdleSt	206	Covered	T2,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T11
0	1	Covered	T2,T7,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T11,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T31,T33,T108
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T11
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	982	0	0
CntIncr_A	7040575	53375	0	0
CntNoWrap_A	7040575	6361951	0	0
DetectStDropOut_A	7040575	88	0	0
DetectedOut_A	7040575	16397	0	0
DetectedPulseOut_A	7040575	377	0	0
DisabledIdleSt_A	7040575	5962156	0	0
DisabledNoDetection_A	7040575	5963853	0	0
EnterDebounceSt_A	7040575	513	0	0
EnterDetectSt_A	7040575	469	0	0
EnterStableSt_A	7040575	377	0	0
PulseIsPulse_A	7040575	377	0	0
StayInStableSt	7040575	15976	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	329	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	982	0	0
T2	22284	12	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	21	0	0
T11	0	3	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	21	0	0
T32	0	6	0	0
T33	0	12	0	0
T37	0	26	0	0
T43	0	12	0	0
T52	448	0	0	0
T87	0	11	0	0
T105	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	53375	0	0
T2	22284	714	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	840	0	0
T11	0	99	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	1075	0	0
T32	0	255	0	0
T33	0	1073	0	0
T37	0	492	0	0
T43	0	270	0	0
T52	448	0	0	0
T87	0	613	0	0
T105	0	189	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6361951	0	0
T1	1205	804	0	0
T2	22284	21812	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	88	0	0
T31	30619	10	0	0
T32	23421	0	0	0
T33	0	6	0	0
T40	451	0	0	0
T53	427	0	0	0
T54	489	0	0	0
T55	415	0	0	0
T56	427	0	0	0
T57	499	0	0	0
T58	522	0	0	0
T90	0	6	0	0
T91	0	1	0	0
T92	0	3	0	0
T108	0	2	0	0
T182	0	1	0	0
T253	0	6	0	0
T254	0	4	0	0
T255	0	8	0	0
T256	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	16397	0	0
T2	22284	37	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	148	0	0
T11	0	37	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T32	0	249	0	0
T37	0	86	0	0
T43	0	320	0	0
T52	448	0	0	0
T87	0	26	0	0
T105	0	156	0	0
T107	0	9	0	0
T110	0	210	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	377	0	0
T2	22284	6	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	9	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T32	0	3	0	0
T37	0	12	0	0
T43	0	6	0	0
T52	448	0	0	0
T87	0	5	0	0
T105	0	3	0	0
T107	0	2	0	0
T110	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5962156	0	0
T1	1205	804	0	0
T2	22284	18132	0	0
T3	12531	4568	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5963853	0	0
T1	1205	805	0	0
T2	22284	18132	0	0
T3	12531	4591	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	513	0	0
T2	22284	6	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	12	0	0
T11	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	11	0	0
T32	0	3	0	0
T33	0	6	0	0
T37	0	14	0	0
T43	0	6	0	0
T52	448	0	0	0
T87	0	6	0	0
T105	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	469	0	0
T2	22284	6	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	9	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	10	0	0
T32	0	3	0	0
T33	0	6	0	0
T37	0	12	0	0
T43	0	6	0	0
T52	448	0	0	0
T87	0	5	0	0
T105	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	377	0	0
T2	22284	6	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	9	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T32	0	3	0	0
T37	0	12	0	0
T43	0	6	0	0
T52	448	0	0	0
T87	0	5	0	0
T105	0	3	0	0
T107	0	2	0	0
T110	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	377	0	0
T2	22284	6	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	9	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T32	0	3	0	0
T37	0	12	0	0
T43	0	6	0	0
T52	448	0	0	0
T87	0	5	0	0
T105	0	3	0	0
T107	0	2	0	0
T110	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	15976	0	0
T2	22284	31	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	139	0	0
T11	0	36	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T32	0	246	0	0
T37	0	74	0	0
T43	0	314	0	0
T52	448	0	0	0
T87	0	21	0	0
T105	0	153	0	0
T107	0	7	0	0
T110	0	207	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	329	0	0
T2	22284	6	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	9	0	0
T11	0	1	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T32	0	3	0	0
T37	0	12	0	0
T43	0	6	0	0
T52	448	0	0	0
T87	0	5	0	0
T105	0	3	0	0
T107	0	2	0	0
T110	0	3	0	0