Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T26,T27,T11
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T27,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T27,T11
1	0	Covered	T11,T43,T68
1	1	Covered	T26,T27,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T27,T11
0	1	Covered	T26,T27,T68
1	0	Covered	T68,T41,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T43,T44
0	1	Covered	T11,T43,T44
1	0	Covered	T41,T70,T257

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T43,T44
1	-	Covered	T11,T43,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T27,T11
DetectSt	168	Covered	T26,T27,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T27,T11
DebounceSt->IdleSt	163	Covered	T237,T73,T238
DetectSt->IdleSt	186	Covered	T26,T27,T68
DetectSt->StableSt	191	Covered	T11,T43,T44
IdleSt->DebounceSt	148	Covered	T26,T27,T11
StableSt->IdleSt	206	Covered	T11,T43,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T26,T27,T11
0	1	Covered	T26,T27,T11
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T27,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T26,T27,T11
IdleSt	0	-	-	-	-	-	-	Covered	T26,T27,T11
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T27,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T237,T73,T238
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T27,T11
DetectSt	-	-	-	-	1	-	-	Covered	T26,T27,T68
DetectSt	-	-	-	-	0	1	-	Covered	T11,T43,T44
DetectSt	-	-	-	-	0	0	-	Covered	T26,T27,T11
StableSt	-	-	-	-	-	-	1	Covered	T11,T43,T44
StableSt	-	-	-	-	-	-	0	Covered	T11,T43,T44
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	2852	0	0
CntIncr_A	7040575	104223	0	0
CntNoWrap_A	7040575	6360081	0	0
DetectStDropOut_A	7040575	370	0	0
DetectedOut_A	7040575	70926	0	0
DetectedPulseOut_A	7040575	806	0	0
DisabledIdleSt_A	7040575	5892389	0	0
DisabledNoDetection_A	7040575	5894567	0	0
EnterDebounceSt_A	7040575	1457	0	0
EnterDetectSt_A	7040575	1396	0	0
EnterStableSt_A	7040575	806	0	0
PulseIsPulse_A	7040575	806	0	0
StayInStableSt	7040575	70009	0	0
gen_high_event_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	676	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	2852	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	26	0	0
T12	1213	0	0	0
T26	5267	58	0	0
T27	4716	8	0	0
T41	0	28	0	0
T42	0	28	0	0
T43	0	40	0	0
T44	0	32	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	54	0	0
T69	0	4	0	0
T70	0	50	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	104223	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	897	0	0
T12	1213	0	0	0
T26	5267	1537	0	0
T27	4716	166	0	0
T41	0	877	0	0
T42	0	1078	0	0
T43	0	1000	0	0
T44	0	720	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	1476	0	0
T69	0	113	0	0
T70	0	1010	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6360081	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	370	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	0	0	0
T12	1213	0	0	0
T26	5267	29	0	0
T27	4716	4	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	15	0	0
T69	0	2	0	0
T70	0	14	0	0
T73	0	1	0	0
T88	0	26	0	0
T89	0	10	0	0
T130	0	7	0	0
T244	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	70926	0	0
T11	12069	188	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	3	0	0
T42	0	2309	0	0
T43	0	2320	0	0
T44	0	1544	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	6	0	0
T99	453	0	0	0
T237	0	23	0	0
T241	0	2278	0	0
T242	0	2097	0	0
T246	0	1435	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	806	0	0
T11	12069	13	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	3	0	0
T42	0	14	0	0
T43	0	20	0	0
T44	0	16	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	6	0	0
T99	453	0	0	0
T237	0	1	0	0
T241	0	22	0	0
T242	0	21	0	0
T246	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5892389	0	0
T1	1205	804	0	0
T2	22284	21824	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5894567	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1457	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	13	0	0
T12	1213	0	0	0
T26	5267	29	0	0
T27	4716	4	0	0
T41	0	14	0	0
T42	0	14	0	0
T43	0	20	0	0
T44	0	16	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	27	0	0
T69	0	2	0	0
T70	0	25	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	1396	0	0
T7	25889	0	0	0
T8	62662	0	0	0
T9	1525	0	0	0
T10	759	0	0	0
T11	12069	13	0	0
T12	1213	0	0	0
T26	5267	29	0	0
T27	4716	4	0	0
T41	0	14	0	0
T42	0	14	0	0
T43	0	20	0	0
T44	0	16	0	0
T52	448	0	0	0
T59	695	0	0	0
T68	0	27	0	0
T69	0	2	0	0
T70	0	25	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	806	0	0
T11	12069	13	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	3	0	0
T42	0	14	0	0
T43	0	20	0	0
T44	0	16	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	6	0	0
T99	453	0	0	0
T237	0	1	0	0
T241	0	22	0	0
T242	0	21	0	0
T246	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	806	0	0
T11	12069	13	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T41	0	3	0	0
T42	0	14	0	0
T43	0	20	0	0
T44	0	16	0	0
T64	523	0	0	0
T65	526	0	0	0
T70	0	6	0	0
T99	453	0	0	0
T237	0	1	0	0
T241	0	22	0	0
T242	0	21	0	0
T246	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	70009	0	0
T11	12069	175	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	2288	0	0
T43	0	2289	0	0
T44	0	1528	0	0
T64	523	0	0	0
T65	526	0	0	0
T73	0	326	0	0
T99	453	0	0	0
T237	0	22	0	0
T239	0	601	0	0
T241	0	2250	0	0
T242	0	2073	0	0
T246	0	1418	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	676	0	0
T11	12069	13	0	0
T12	1213	0	0	0
T20	487	0	0	0
T22	561	0	0	0
T23	3297	0	0	0
T31	30619	0	0	0
T38	604	0	0	0
T42	0	7	0	0
T43	0	9	0	0
T44	0	16	0	0
T64	523	0	0	0
T65	526	0	0	0
T73	0	5	0	0
T99	453	0	0	0
T237	0	1	0	0
T239	0	3	0	0
T241	0	16	0	0
T242	0	18	0	0
T246	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T3,T26
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T26
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T7,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T7,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T2,T3,T26
1	1	Covered	T2,T7,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T31
0	1	Covered	T258,T259,T91
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T31
0	1	Covered	T2,T7,T31
1	0	Covered	T73,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T31
1	-	Covered	T2,T7,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T31
DetectSt	168	Covered	T2,T7,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T7,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T31
DebounceSt->IdleSt	163	Covered	T7,T31,T32
DetectSt->IdleSt	186	Covered	T258,T73,T259
DetectSt->StableSt	191	Covered	T2,T7,T31
IdleSt->DebounceSt	148	Covered	T2,T7,T31
StableSt->IdleSt	206	Covered	T2,T7,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T31
0	1	Covered	T2,T7,T31
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T31,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T31
DetectSt	-	-	-	-	1	-	-	Covered	T258,T73,T259
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T31
DetectSt	-	-	-	-	0	0	-	Covered	T2,T7,T31
StableSt	-	-	-	-	-	-	1	Covered	T2,T7,T31
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7040575	806	0	0
CntIncr_A	7040575	41252	0	0
CntNoWrap_A	7040575	6362127	0	0
DetectStDropOut_A	7040575	43	0	0
DetectedOut_A	7040575	14944	0	0
DetectedPulseOut_A	7040575	337	0	0
DisabledIdleSt_A	7040575	5976678	0	0
DisabledNoDetection_A	7040575	5978384	0	0
EnterDebounceSt_A	7040575	422	0	0
EnterDetectSt_A	7040575	384	0	0
EnterStableSt_A	7040575	337	0	0
PulseIsPulse_A	7040575	337	0	0
StayInStableSt	7040575	14575	0	0
gen_high_level_sva.HighLevelEvent_A	7040575	6365313	0	0
gen_not_sticky_sva.StableStDropOut_A	7040575	302	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	806	0	0
T2	22284	8	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	5	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	5	0	0
T32	0	11	0	0
T33	0	8	0	0
T37	0	12	0	0
T43	0	14	0	0
T44	0	6	0	0
T52	448	0	0	0
T87	0	2	0	0
T105	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	41252	0	0
T2	22284	256	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	169	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	145	0	0
T32	0	863	0	0
T33	0	476	0	0
T37	0	216	0	0
T43	0	301	0	0
T44	0	177	0	0
T52	448	0	0	0
T87	0	105	0	0
T105	0	206	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6362127	0	0
T1	1205	804	0	0
T2	22284	21816	0	0
T3	12531	4844	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	43	0	0
T73	6432	0	0	0
T91	0	1	0	0
T95	0	2	0	0
T121	0	1	0	0
T171	0	2	0	0
T202	0	11	0	0
T244	15768	0	0	0
T251	0	10	0	0
T258	21136	3	0	0
T259	0	4	0	0
T260	0	4	0	0
T261	0	1	0	0
T262	525	0	0	0
T263	403	0	0	0
T264	406	0	0	0
T265	8401	0	0	0
T266	404	0	0	0
T267	422	0	0	0
T268	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	14944	0	0
T2	22284	246	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	60	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	88	0	0
T32	0	45	0	0
T33	0	239	0	0
T37	0	44	0	0
T43	0	375	0	0
T44	0	233	0	0
T52	448	0	0	0
T87	0	6	0	0
T105	0	24	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	337	0	0
T2	22284	4	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	2	0	0
T32	0	5	0	0
T33	0	4	0	0
T37	0	6	0	0
T43	0	7	0	0
T44	0	3	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5976678	0	0
T1	1205	804	0	0
T2	22284	18132	0	0
T3	12531	4568	0	0
T4	402	1	0	0
T5	527	126	0	0
T6	1487	1086	0	0
T13	456	55	0	0
T14	493	92	0	0
T15	436	35	0	0
T16	411	10	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	5978384	0	0
T1	1205	805	0	0
T2	22284	18132	0	0
T3	12531	4591	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	422	0	0
T2	22284	4	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	3	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	3	0	0
T32	0	6	0	0
T33	0	4	0	0
T37	0	6	0	0
T43	0	7	0	0
T44	0	3	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	384	0	0
T2	22284	4	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	2	0	0
T32	0	5	0	0
T33	0	4	0	0
T37	0	6	0	0
T43	0	7	0	0
T44	0	3	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	337	0	0
T2	22284	4	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	2	0	0
T32	0	5	0	0
T33	0	4	0	0
T37	0	6	0	0
T43	0	7	0	0
T44	0	3	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	337	0	0
T2	22284	4	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	2	0	0
T32	0	5	0	0
T33	0	4	0	0
T37	0	6	0	0
T43	0	7	0	0
T44	0	3	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	14575	0	0
T2	22284	242	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	58	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	86	0	0
T32	0	40	0	0
T33	0	235	0	0
T37	0	38	0	0
T43	0	363	0	0
T44	0	230	0	0
T52	448	0	0	0
T87	0	5	0	0
T105	0	22	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	6365313	0	0
T1	1205	805	0	0
T2	22284	21833	0	0
T3	12531	4868	0	0
T4	402	2	0	0
T5	527	127	0	0
T6	1487	1087	0	0
T13	456	56	0	0
T14	493	93	0	0
T15	436	36	0	0
T16	411	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7040575	302	0	0
T2	22284	4	0	0
T3	12531	0	0	0
T6	1487	0	0	0
T7	0	2	0	0
T13	456	0	0	0
T14	493	0	0	0
T15	436	0	0	0
T16	411	0	0	0
T21	502	0	0	0
T26	5267	0	0	0
T31	0	2	0	0
T32	0	5	0	0
T33	0	4	0	0
T37	0	6	0	0
T43	0	2	0	0
T44	0	3	0	0
T52	448	0	0	0
T87	0	1	0	0
T105	0	2	0	0