Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1306785379	10519	0	0
auto_block_debounce_ctl_rd_A	1306785379	1945	0	0
auto_block_out_ctl_rd_A	1306785379	2589	0	0
com_det_ctl_0_rd_A	1306785379	3734	0	0
com_det_ctl_1_rd_A	1306785379	3771	0	0
com_det_ctl_2_rd_A	1306785379	4073	0	0
com_det_ctl_3_rd_A	1306785379	3767	0	0
com_out_ctl_0_rd_A	1306785379	4636	0	0
com_out_ctl_1_rd_A	1306785379	4615	0	0
com_out_ctl_2_rd_A	1306785379	4655	0	0
com_out_ctl_3_rd_A	1306785379	4501	0	0
com_pre_det_ctl_0_rd_A	1306785379	1370	0	0
com_pre_det_ctl_1_rd_A	1306785379	1250	0	0
com_pre_det_ctl_2_rd_A	1306785379	1384	0	0
com_pre_det_ctl_3_rd_A	1306785379	1429	0	0
com_pre_sel_ctl_0_rd_A	1306785379	4840	0	0
com_pre_sel_ctl_1_rd_A	1306785379	4655	0	0
com_pre_sel_ctl_2_rd_A	1306785379	4803	0	0
com_pre_sel_ctl_3_rd_A	1306785379	4812	0	0
com_sel_ctl_0_rd_A	1306785379	4749	0	0
com_sel_ctl_1_rd_A	1306785379	4624	0	0
com_sel_ctl_2_rd_A	1306785379	4875	0	0
com_sel_ctl_3_rd_A	1306785379	4719	0	0
ec_rst_ctl_rd_A	1306785379	2470	0	0
intr_enable_rd_A	1306785379	2147	0	0
key_intr_ctl_rd_A	1306785379	4484	0	0
key_intr_debounce_ctl_rd_A	1306785379	1443	0	0
key_invert_ctl_rd_A	1306785379	5882	0	0
pin_allowed_ctl_rd_A	1306785379	6693	0	0
pin_out_ctl_rd_A	1306785379	5409	0	0
pin_out_value_rd_A	1306785379	5608	0	0
regwen_rd_A	1306785379	1491	0	0
ulp_ac_debounce_ctl_rd_A	1306785379	1483	0	0
ulp_ctl_rd_A	1306785379	1489	0	0
ulp_lid_debounce_ctl_rd_A	1306785379	1426	0	0
ulp_pwrb_debounce_ctl_rd_A	1306785379	1514	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	10519	0	0
T3	267203	4	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	13	0	0
T35	0	21	0	0
T49	0	7	0	0
T50	0	7	0	0
T52	107495	0	0	0
T78	0	28	0	0
T157	0	2	0	0
T291	0	2	0	0
T292	0	12	0	0
T293	0	21	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1945	0	0
T3	267203	39	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T25	0	17	0	0
T26	136960	0	0	0
T49	0	48	0	0
T50	0	20	0	0
T51	0	13	0	0
T52	107495	0	0	0
T109	0	7	0	0
T292	0	31	0	0
T294	0	6	0	0
T295	0	2	0	0
T296	0	7	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	2589	0	0
T3	267203	29	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T25	0	9	0	0
T26	136960	0	0	0
T34	0	7	0	0
T49	0	27	0	0
T50	0	32	0	0
T51	0	7	0	0
T52	107495	0	0	0
T109	0	5	0	0
T294	0	5	0	0
T295	0	4	0	0
T296	0	24	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	3734	0	0
T3	267203	23	0	0
T6	125623	0	0	0
T7	126905	82	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	53	0	0
T32	0	57	0	0
T49	0	80	0	0
T52	107495	0	0	0
T87	0	73	0	0
T107	0	51	0	0
T110	0	70	0	0
T241	0	57	0	0
T246	0	81	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	3771	0	0
T3	267203	21	0	0
T6	125623	0	0	0
T7	126905	72	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	57	0	0
T32	0	66	0	0
T34	0	8	0	0
T52	107495	0	0	0
T87	0	76	0	0
T107	0	40	0	0
T110	0	89	0	0
T241	0	30	0	0
T246	0	91	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4073	0	0
T3	267203	24	0	0
T6	125623	0	0	0
T7	126905	68	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	57	0	0
T32	0	72	0	0
T34	0	2	0	0
T52	107495	0	0	0
T87	0	73	0	0
T107	0	58	0	0
T110	0	67	0	0
T241	0	58	0	0
T246	0	72	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	3767	0	0
T3	267203	19	0	0
T6	125623	0	0	0
T7	126905	51	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	62	0	0
T32	0	77	0	0
T34	0	17	0	0
T52	107495	0	0	0
T87	0	61	0	0
T107	0	34	0	0
T110	0	55	0	0
T241	0	65	0	0
T246	0	78	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4636	0	0
T3	267203	30	0	0
T6	125623	0	0	0
T7	126905	51	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	51	0	0
T32	0	55	0	0
T34	0	9	0	0
T52	107495	0	0	0
T87	0	68	0	0
T107	0	16	0	0
T110	0	71	0	0
T241	0	40	0	0
T246	0	87	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4615	0	0
T3	267203	32	0	0
T6	125623	0	0	0
T7	126905	82	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	84	0	0
T32	0	75	0	0
T34	0	10	0	0
T52	107495	0	0	0
T87	0	77	0	0
T107	0	33	0	0
T110	0	51	0	0
T241	0	64	0	0
T246	0	71	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4655	0	0
T3	267203	35	0	0
T6	125623	0	0	0
T7	126905	66	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	76	0	0
T32	0	66	0	0
T34	0	4	0	0
T52	107495	0	0	0
T87	0	55	0	0
T107	0	35	0	0
T110	0	51	0	0
T241	0	50	0	0
T246	0	83	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4501	0	0
T3	267203	31	0	0
T6	125623	0	0	0
T7	126905	47	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	70	0	0
T32	0	78	0	0
T34	0	17	0	0
T52	107495	0	0	0
T87	0	72	0	0
T107	0	49	0	0
T110	0	55	0	0
T241	0	53	0	0
T246	0	100	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1370	0	0
T3	267203	15	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	8	0	0
T49	0	15	0	0
T50	0	15	0	0
T52	107495	0	0	0
T115	0	8	0	0
T182	0	7	0	0
T202	0	29	0	0
T292	0	16	0	0
T297	0	10	0	0
T298	0	13	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1250	0	0
T3	267203	45	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	10	0	0
T49	0	13	0	0
T50	0	4	0	0
T52	107495	0	0	0
T115	0	4	0	0
T182	0	8	0	0
T202	0	14	0	0
T292	0	16	0	0
T297	0	16	0	0
T298	0	11	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1384	0	0
T3	267203	28	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	19	0	0
T49	0	19	0	0
T50	0	14	0	0
T52	107495	0	0	0
T115	0	12	0	0
T182	0	4	0	0
T202	0	17	0	0
T292	0	21	0	0
T297	0	12	0	0
T298	0	11	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1429	0	0
T3	267203	26	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	6	0	0
T49	0	15	0	0
T50	0	17	0	0
T52	107495	0	0	0
T115	0	12	0	0
T182	0	12	0	0
T202	0	12	0	0
T292	0	44	0	0
T297	0	22	0	0
T298	0	26	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4840	0	0
T3	267203	21	0	0
T6	125623	0	0	0
T7	126905	85	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	75	0	0
T32	0	83	0	0
T34	0	17	0	0
T52	107495	0	0	0
T87	0	88	0	0
T107	0	27	0	0
T110	0	81	0	0
T241	0	49	0	0
T246	0	57	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4655	0	0
T3	267203	21	0	0
T6	125623	0	0	0
T7	126905	82	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	79	0	0
T32	0	63	0	0
T34	0	3	0	0
T52	107495	0	0	0
T87	0	81	0	0
T107	0	31	0	0
T110	0	68	0	0
T241	0	56	0	0
T246	0	72	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4803	0	0
T3	267203	20	0	0
T6	125623	0	0	0
T7	126905	81	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	60	0	0
T32	0	85	0	0
T34	0	6	0	0
T52	107495	0	0	0
T87	0	71	0	0
T107	0	51	0	0
T110	0	56	0	0
T241	0	53	0	0
T246	0	91	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4812	0	0
T3	267203	13	0	0
T6	125623	0	0	0
T7	126905	67	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	62	0	0
T32	0	70	0	0
T34	0	21	0	0
T52	107495	0	0	0
T87	0	77	0	0
T107	0	69	0	0
T110	0	95	0	0
T241	0	52	0	0
T246	0	83	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4749	0	0
T3	267203	27	0	0
T6	125623	0	0	0
T7	126905	73	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	70	0	0
T32	0	77	0	0
T34	0	13	0	0
T52	107495	0	0	0
T87	0	67	0	0
T107	0	38	0	0
T110	0	64	0	0
T241	0	58	0	0
T246	0	77	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4624	0	0
T3	267203	20	0	0
T6	125623	0	0	0
T7	126905	61	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	86	0	0
T32	0	60	0	0
T34	0	11	0	0
T52	107495	0	0	0
T87	0	59	0	0
T107	0	20	0	0
T110	0	64	0	0
T241	0	57	0	0
T246	0	81	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4875	0	0
T3	267203	37	0	0
T6	125623	0	0	0
T7	126905	71	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	60	0	0
T32	0	70	0	0
T34	0	9	0	0
T52	107495	0	0	0
T87	0	58	0	0
T107	0	44	0	0
T110	0	78	0	0
T241	0	47	0	0
T246	0	82	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4719	0	0
T3	267203	24	0	0
T6	125623	0	0	0
T7	126905	76	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T31	0	88	0	0
T32	0	84	0	0
T34	0	7	0	0
T52	107495	0	0	0
T87	0	69	0	0
T107	0	36	0	0
T110	0	78	0	0
T241	0	54	0	0
T246	0	81	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	2470	0	0
T3	267203	34	0	0
T6	125623	0	0	0
T7	126905	40	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	1	0	0
T31	0	40	0	0
T32	0	35	0	0
T34	0	39	0	0
T52	107495	0	0	0
T87	0	19	0	0
T101	0	6	0	0
T102	0	3	0	0
T107	0	34	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	2147	0	0
T3	267203	77	0	0
T6	125623	0	0	0
T7	126905	37	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	14	0	0
T49	0	53	0	0
T50	0	18	0	0
T52	107495	0	0	0
T90	0	18	0	0
T115	0	41	0	0
T182	0	7	0	0
T292	0	49	0	0
T299	0	9	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	4484	0	0
T3	267203	36	0	0
T6	125623	0	0	0
T7	126905	4	0	0
T8	145793	0	0	0
T12	0	1	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	18	0	0
T38	0	4	0	0
T49	0	21	0	0
T50	0	18	0	0
T52	107495	0	0	0
T90	0	2	0	0
T138	0	7	0	0
T226	0	7	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1443	0	0
T3	267203	13	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	22	0	0
T49	0	5	0	0
T50	0	16	0	0
T52	107495	0	0	0
T115	0	11	0	0
T182	0	6	0	0
T202	0	9	0	0
T292	0	32	0	0
T297	0	16	0	0
T298	0	11	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	5882	0	0
T3	267203	158	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	159	0	0
T49	0	13	0	0
T50	0	139	0	0
T52	107495	0	0	0
T54	0	65	0	0
T57	0	59	0	0
T63	0	65	0	0
T300	0	22	0	0
T301	0	26	0	0
T302	0	72	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	6693	0	0
T3	267203	92	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	82	0	0
T22	0	85	0	0
T26	136960	0	0	0
T34	0	114	0	0
T49	0	18	0	0
T50	0	236	0	0
T52	107495	0	0	0
T123	0	72	0	0
T303	0	62	0	0
T304	0	70	0	0
T305	0	67	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	5409	0	0
T3	267203	77	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	71	0	0
T22	0	56	0	0
T26	136960	0	0	0
T34	0	125	0	0
T49	0	18	0	0
T50	0	225	0	0
T52	107495	0	0	0
T123	0	68	0	0
T303	0	47	0	0
T304	0	80	0	0
T305	0	61	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	5608	0	0
T3	267203	100	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	82	0	0
T22	0	76	0	0
T26	136960	0	0	0
T34	0	128	0	0
T49	0	13	0	0
T50	0	232	0	0
T52	107495	0	0	0
T123	0	61	0	0
T303	0	65	0	0
T304	0	70	0	0
T305	0	80	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1491	0	0
T3	267203	32	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	0	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	28	0	0
T49	0	4	0	0
T50	0	11	0	0
T52	107495	0	0	0
T115	0	9	0	0
T182	0	5	0	0
T202	0	21	0	0
T292	0	26	0	0
T297	0	11	0	0
T298	0	10	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1483	0	0
T3	267203	35	0	0
T6	125623	0	0	0
T7	126905	1	0	0
T8	145793	3	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	13	0	0
T49	0	40	0	0
T50	0	14	0	0
T52	107495	0	0	0
T60	0	15	0	0
T72	0	10	0	0
T182	0	12	0	0
T292	0	30	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1489	0	0
T3	267203	31	0	0
T6	125623	0	0	0
T7	126905	9	0	0
T8	145793	4	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	6	0	0
T49	0	21	0	0
T50	0	16	0	0
T52	107495	0	0	0
T60	0	8	0	0
T72	0	7	0	0
T182	0	16	0	0
T292	0	10	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1426	0	0
T3	267203	22	0	0
T6	125623	0	0	0
T7	126905	2	0	0
T8	145793	3	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	22	0	0
T49	0	32	0	0
T50	0	11	0	0
T52	107495	0	0	0
T60	0	7	0	0
T72	0	8	0	0
T182	0	10	0	0
T292	0	32	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1306785379	1514	0	0
T3	267203	35	0	0
T6	125623	0	0	0
T7	126905	0	0	0
T8	145793	9	0	0
T14	118539	0	0	0
T15	17434	0	0	0
T16	49325	0	0	0
T21	193547	0	0	0
T26	136960	0	0	0
T34	0	10	0	0
T49	0	46	0	0
T50	0	6	0	0
T52	107495	0	0	0
T60	0	20	0	0
T72	0	12	0	0
T115	0	14	0	0
T182	0	3	0	0
T292	0	36	0	0