Unified Coverage Report :: Module

Line Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Module : prim_pulse_sync

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T5,T2
1	1	Covered	T1,T3,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T5,T2
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T5,T2

Branch Coverage for Module : prim_pulse_sync

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Module : prim_pulse_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	2147483647	222264	0	0
SrcPulseCheck_M	2147483647	224230	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	2147483647	222264
T2	1158768	27
T3	2505075	7
T6	1142503	0
T7	126905	30
T11	0	9
T13	1994142	2
T14	1070795	0
T15	160394	0
T16	447213	0
T21	1745939	0
T23	797994	34
T24	0	16
T25	0	16
T26	1274776	3
T27	0	3
T31	352126	39
T32	0	9
T33	0	5
T38	605310	0
T40	434214	2
T45	0	16
T46	0	16
T47	0	14
T48	0	16
T49	0	60
T50	0	16
T51	0	12
T52	971039	0
T53	60738	0
T54	490322	0
T55	412226	0
T56	103508	0
T57	85880	0
T58	523106	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	2147483647	224230
T2	1158768	27
T3	2250403	7
T6	1018367	0
T7	25889	30
T11	0	9
T13	1773432	2
T14	952749	0
T15	143396	0
T16	398299	0
T21	1552894	0
T23	797994	34
T24	0	16
T25	0	16
T26	1143083	3
T27	0	3
T31	352126	39
T32	0	9
T33	0	5
T38	605310	0
T40	434214	2
T45	0	16
T46	0	16
T47	0	14
T48	0	16
T49	0	60
T50	0	16
T51	0	12
T52	863992	0
T53	60738	0
T54	490322	0
T55	412226	0
T56	103508	0
T57	85880	0
T58	523106	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T5,T2,T13
1	1	Covered	T17,T18,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T17,T18,T19
1	1	Covered	T5,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1906	0	0
SrcPulseCheck_M	1306785379	1959	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1906
T2	22284	9
T3	12531	4
T5	527	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	2
T26	5267	1
T27	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1959
T2	122562	9
T3	267203	4
T5	36917	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	2
T26	136960	1
T27	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T5,T2,T13
1	1	Covered	T17,T18,T19

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T17,T18,T19
1	1	Covered	T5,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1948	0	0
SrcPulseCheck_M	7289997	1948	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1948
T2	122562	9
T3	267203	4
T5	36917	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	2
T26	136960	1
T27	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1948
T2	22284	9
T3	12531	4
T5	527	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	2
T26	5267	1
T27	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T6,T9
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	924	0	0
SrcPulseCheck_M	1306785379	976	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	924
T1	1205	2
T2	22284	0
T3	12531	1
T4	402	0
T5	527	0
T6	1487	3
T7	0	1
T8	0	1
T9	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	976
T1	57920	2
T2	122562	0
T3	267203	1
T4	193182	0
T5	36917	0
T6	125623	3
T7	0	1
T8	0	1
T9	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T6,T9
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	964	0	0
SrcPulseCheck_M	7289997	964	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	964
T1	57920	2
T2	122562	0
T3	267203	1
T4	193182	0
T5	36917	0
T6	125623	3
T7	0	1
T8	0	1
T9	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	964
T1	1205	2
T2	22284	0
T3	12531	1
T4	402	0
T5	527	0
T6	1487	3
T7	0	1
T8	0	1
T9	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T6,T9
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	948	0	0
SrcPulseCheck_M	1306785379	1004	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	948
T1	1205	2
T2	22284	0
T3	12531	1
T4	402	0
T5	527	0
T6	1487	3
T7	0	1
T8	0	1
T9	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1004
T1	57920	2
T2	122562	0
T3	267203	1
T4	193182	0
T5	36917	0
T6	125623	3
T7	0	1
T8	0	1
T9	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T6,T9
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	992	0	0
SrcPulseCheck_M	7289997	992	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	992
T1	57920	2
T2	122562	0
T3	267203	1
T4	193182	0
T5	36917	0
T6	125623	3
T7	0	1
T8	0	1
T9	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	992
T1	1205	2
T2	22284	0
T3	12531	1
T4	402	0
T5	527	0
T6	1487	3
T7	0	1
T8	0	1
T9	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T6,T9
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	941	0	0
SrcPulseCheck_M	1306785379	996	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	941
T1	1205	2
T2	22284	0
T3	12531	1
T4	402	0
T5	527	0
T6	1487	3
T7	0	1
T8	0	1
T9	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	996
T1	57920	2
T2	122562	0
T3	267203	1
T4	193182	0
T5	36917	0
T6	125623	3
T7	0	1
T8	0	1
T9	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T6,T9

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T6,T9
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	984	0	0
SrcPulseCheck_M	7289997	984	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	984
T1	57920	2
T2	122562	0
T3	267203	1
T4	193182	0
T5	36917	0
T6	125623	3
T7	0	1
T8	0	1
T9	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	984
T1	1205	2
T2	22284	0
T3	12531	1
T4	402	0
T5	527	0
T6	1487	3
T7	0	1
T8	0	1
T9	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T34	0	1
T35	0	1
T49	0	5
T60	0	3

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	911	0	0
SrcPulseCheck_M	1306785379	972	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	911
T1	1205	2
T2	22284	0
T3	12531	2
T4	402	0
T5	527	0
T6	1487	4
T8	0	2
T9	0	2
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T35	0	2
T49	0	2
T60	0	6
T71	0	2
T72	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	972
T1	57920	2
T2	122562	0
T3	267203	2
T4	193182	0
T5	36917	0
T6	125623	4
T8	0	2
T9	0	2
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T35	0	2
T49	0	2
T60	0	6
T71	0	2
T72	0	2

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T3,T6

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	959	0	0
SrcPulseCheck_M	7289997	959	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	959
T1	57920	2
T2	122562	0
T3	267203	2
T4	193182	0
T5	36917	0
T6	125623	4
T8	0	2
T9	0	2
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T35	0	2
T49	0	2
T60	0	6
T71	0	2
T72	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	959
T1	1205	2
T2	22284	0
T3	12531	2
T4	402	0
T5	527	0
T6	1487	4
T8	0	2
T9	0	2
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T35	0	2
T49	0	2
T60	0	6
T71	0	2
T72	0	2

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T31,T33

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T1,T2,T3
1	0	Covered	T6,T31,T33
1	1	Covered	T1,T2,T3

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1107	0	0
SrcPulseCheck_M	1306785379	1166	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1107
T1	1205	1
T2	22284	8
T3	12531	1
T4	402	0
T5	527	0
T6	1487	2
T7	0	9
T8	0	1
T9	0	1
T11	0	1
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T31	0	8
T32	0	8

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1166
T1	57920	1
T2	122562	8
T3	267203	1
T4	193182	0
T5	36917	0
T6	125623	2
T7	0	9
T8	0	1
T9	0	1
T11	0	1
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T31	0	8
T32	0	8

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T20
1	0	Covered	T3,T14,T20
1	1	Covered	T3,T14,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T20
1	0	Covered	T3,T14,T20
1	1	Covered	T3,T14,T20

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	3017	0	0
SrcPulseCheck_M	1306785379	3075	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	3017
T3	12531	40
T6	1487	0
T7	25889	0
T8	62662	0
T14	493	20
T15	436	0
T16	411	0
T20	0	20
T21	502	0
T26	5267	0
T34	0	60
T37	0	40
T52	448	0
T54	0	20
T57	0	20
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	3075
T3	267203	40
T6	125623	0
T7	126905	0
T8	145793	0
T14	118539	20
T15	17434	0
T16	49325	0
T20	0	20
T21	193547	0
T26	136960	0
T34	0	60
T37	0	40
T52	107495	0
T54	0	20
T57	0	20
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T20
1	0	Covered	T3,T14,T20
1	1	Covered	T3,T14,T20

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T20
1	0	Covered	T3,T14,T20
1	1	Covered	T3,T14,T20

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	3065	0	0
SrcPulseCheck_M	7289997	3065	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	3065
T3	267203	40
T6	125623	0
T7	126905	0
T8	145793	0
T14	118539	20
T15	17434	0
T16	49325	0
T20	0	20
T21	193547	0
T26	136960	0
T34	0	60
T37	0	40
T52	107495	0
T54	0	20
T57	0	20
T61	0	20
T62	0	20
T63	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	3065
T3	12531	40
T6	1487	0
T7	25889	0
T8	62662	0
T14	493	20
T15	436	0
T16	411	0
T20	0	20
T21	502	0
T26	5267	0
T34	0	60
T37	0	40
T52	448	0
T54	0	20
T57	0	20
T61	0	20
T62	0	20
T63	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T21
1	0	Covered	T3,T14,T21
1	1	Covered	T3,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T21
1	0	Covered	T3,T21,T22
1	1	Covered	T3,T14,T21

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	6528	0	0
SrcPulseCheck_M	1306785379	6587	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	6528
T3	12531	55
T6	1487	0
T7	25889	0
T8	62662	0
T14	493	1
T15	436	0
T16	411	0
T20	0	1
T21	502	20
T22	0	20
T23	0	20
T26	5267	0
T52	448	0
T54	0	1
T57	0	1
T64	0	20
T65	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	6587
T3	267203	56
T6	125623	0
T7	126905	0
T8	145793	0
T14	118539	1
T15	17434	0
T16	49325	0
T20	0	1
T21	193547	20
T22	0	20
T23	0	20
T26	136960	0
T52	107495	0
T54	0	1
T57	0	1
T64	0	20
T65	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T21
1	0	Covered	T3,T14,T21
1	1	Covered	T3,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T14,T21
1	0	Covered	T3,T21,T22
1	1	Covered	T3,T14,T21

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	6570	0	0
SrcPulseCheck_M	7289997	6571	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	6570
T3	267203	55
T6	125623	0
T7	126905	0
T8	145793	0
T14	118539	1
T15	17434	0
T16	49325	0
T20	0	1
T21	193547	20
T22	0	20
T23	0	20
T26	136960	0
T52	107495	0
T54	0	1
T57	0	1
T64	0	20
T65	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	6571
T3	12531	55
T6	1487	0
T7	25889	0
T8	62662	0
T14	493	1
T15	436	0
T16	411	0
T20	0	1
T21	502	20
T22	0	20
T23	0	20
T26	5267	0
T52	448	0
T54	0	1
T57	0	1
T64	0	20
T65	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T5,T2,T13
1	1	Covered	T3,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T3,T21,T22
1	1	Covered	T5,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	7647	0	0
SrcPulseCheck_M	1306785379	7710	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	7647
T2	22284	9
T3	12531	60
T5	527	1
T6	1487	0
T7	0	10
T13	456	1
T14	493	1
T15	436	0
T16	411	0
T21	502	20
T26	5267	1
T27	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	7710
T2	122562	9
T3	267203	61
T5	36917	1
T6	125623	0
T7	0	10
T13	221166	1
T14	118539	1
T15	17434	0
T16	49325	0
T21	193547	20
T26	136960	1
T27	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T5,T2,T13
1	1	Covered	T3,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T5,T2,T13
1	0	Covered	T3,T21,T22
1	1	Covered	T5,T2,T13

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	7693	0	0
SrcPulseCheck_M	7289997	7693	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	7693
T2	122562	9
T3	267203	60
T5	36917	1
T6	125623	0
T7	0	10
T13	221166	1
T14	118539	1
T15	17434	0
T16	49325	0
T21	193547	20
T26	136960	1
T27	0	1
T59	0	1

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	7693
T2	22284	9
T3	12531	60
T5	527	1
T6	1487	0
T7	0	10
T13	456	1
T14	493	1
T15	436	0
T16	411	0
T21	502	20
T26	5267	1
T27	0	1
T59	0	1

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T21,T22
1	0	Covered	T3,T21,T22
1	1	Covered	T3,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T21,T22
1	0	Covered	T3,T21,T22
1	1	Covered	T3,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	6439	0	0
SrcPulseCheck_M	1306785379	6499	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	6439
T3	12531	53
T6	1487	0
T7	25889	0
T8	62662	0
T14	493	0
T15	436	0
T16	411	0
T21	502	20
T22	0	20
T23	0	20
T26	5267	0
T34	0	80
T52	448	0
T58	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	6499
T3	267203	54
T6	125623	0
T7	126905	0
T8	145793	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	20
T22	0	20
T23	0	20
T26	136960	0
T34	0	80
T52	107495	0
T58	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T21,T22
1	0	Covered	T3,T21,T22
1	1	Covered	T3,T21,T22

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T21,T22
1	0	Covered	T3,T21,T22
1	1	Covered	T3,T21,T22

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	6483	0	0
SrcPulseCheck_M	7289997	6483	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	6483
T3	267203	53
T6	125623	0
T7	126905	0
T8	145793	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	20
T22	0	20
T23	0	20
T26	136960	0
T34	0	80
T52	107495	0
T58	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	6483
T3	12531	53
T6	1487	0
T7	25889	0
T8	62662	0
T14	493	0
T15	436	0
T16	411	0
T21	502	20
T22	0	20
T23	0	20
T26	5267	0
T34	0	80
T52	448	0
T58	0	20
T64	0	20
T65	0	20
T66	0	20
T67	0	20

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T7,T10
1	0	Covered	T73,T74,T17
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	957	0	0
SrcPulseCheck_M	1306785379	1017	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	957
T3	12531	2
T6	1487	0
T7	25889	1
T8	62662	0
T10	0	1
T12	0	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	0
T34	0	2
T35	0	2
T36	0	1
T37	0	1
T38	0	1
T39	0	1
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1017
T3	267203	2
T6	125623	0
T7	126905	1
T8	145793	0
T10	0	1
T12	0	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	0
T34	0	2
T35	0	2
T36	0	1
T37	0	1
T38	0	1
T39	0	1
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T7,T10
1	0	Covered	T3,T7,T10
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T3,T7,T10
1	0	Covered	T73,T74,T17
1	1	Covered	T3,T7,T10

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1005	0	0
SrcPulseCheck_M	7289997	1005	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1005
T3	267203	2
T6	125623	0
T7	126905	1
T8	145793	0
T10	0	1
T12	0	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	0
T34	0	2
T35	0	2
T36	0	1
T37	0	1
T38	0	1
T39	0	1
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1005
T3	12531	2
T6	1487	0
T7	25889	1
T8	62662	0
T10	0	1
T12	0	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	0
T34	0	2
T35	0	2
T36	0	1
T37	0	1
T38	0	1
T39	0	1
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1884	0	0
SrcPulseCheck_M	1306785379	1945	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1884
T2	22284	9
T3	12531	5
T6	1487	0
T7	0	11
T10	0	1
T11	0	3
T12	0	1
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	1
T27	0	1
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1945
T2	122562	9
T3	267203	5
T6	125623	0
T7	0	11
T10	0	1
T11	0	3
T12	0	1
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	1
T27	0	1
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1932	0	0
SrcPulseCheck_M	7289997	1932	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1932
T2	122562	9
T3	267203	5
T6	125623	0
T7	0	11
T10	0	1
T11	0	3
T12	0	1
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	1
T27	0	1
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1932
T2	22284	9
T3	12531	5
T6	1487	0
T7	0	11
T10	0	1
T11	0	3
T12	0	1
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	1
T27	0	1
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1263	0	0
SrcPulseCheck_M	1306785379	1321	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1263
T23	3297	10
T24	0	5
T25	0	5
T31	30619	0
T38	604	0
T40	451	0
T45	0	5
T46	0	5
T47	0	4
T48	0	5
T49	0	18
T50	0	5
T51	0	3
T53	427	0
T54	489	0
T55	415	0
T56	427	0
T57	499	0
T58	522	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1321
T23	395700	10
T24	0	5
T25	0	5
T31	145444	0
T38	302051	0
T40	216656	0
T45	0	5
T46	0	5
T47	0	4
T48	0	5
T49	0	18
T50	0	5
T51	0	3
T53	29942	0
T54	244672	0
T55	205698	0
T56	51327	0
T57	42441	0
T58	261031	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1309	0	0
SrcPulseCheck_M	7289997	1309	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1309
T23	395700	10
T24	0	5
T25	0	5
T31	145444	0
T38	302051	0
T40	216656	0
T45	0	5
T46	0	5
T47	0	4
T48	0	5
T49	0	18
T50	0	5
T51	0	3
T53	29942	0
T54	244672	0
T55	205698	0
T56	51327	0
T57	42441	0
T58	261031	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1309
T23	3297	10
T24	0	5
T25	0	5
T31	30619	0
T38	604	0
T40	451	0
T45	0	5
T46	0	5
T47	0	4
T48	0	5
T49	0	18
T50	0	5
T51	0	3
T53	427	0
T54	489	0
T55	415	0
T56	427	0
T57	499	0
T58	522	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1081	0	0
SrcPulseCheck_M	1306785379	1140	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1081
T23	3297	6
T24	0	3
T25	0	3
T31	30619	0
T38	604	0
T40	451	0
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	0	12
T50	0	3
T51	0	3
T53	427	0
T54	489	0
T55	415	0
T56	427	0
T57	499	0
T58	522	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1140
T23	395700	6
T24	0	3
T25	0	3
T31	145444	0
T38	302051	0
T40	216656	0
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	0	12
T50	0	3
T51	0	3
T53	29942	0
T54	244672	0
T55	205698	0
T56	51327	0
T57	42441	0
T58	261031	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T23,T24,T25
1	0	Covered	T23,T24,T25
1	1	Covered	T23,T24,T25

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1128	0	0
SrcPulseCheck_M	7289997	1128	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1128
T23	395700	6
T24	0	3
T25	0	3
T31	145444	0
T38	302051	0
T40	216656	0
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	0	12
T50	0	3
T51	0	3
T53	29942	0
T54	244672	0
T55	205698	0
T56	51327	0
T57	42441	0
T58	261031	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1128
T23	3297	6
T24	0	3
T25	0	3
T31	30619	0
T38	604	0
T40	451	0
T45	0	3
T46	0	3
T47	0	3
T48	0	3
T49	0	12
T50	0	3
T51	0	3
T53	427	0
T54	489	0
T55	415	0
T56	427	0
T57	499	0
T58	522	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T26,T27,T11
1	1	Covered	T13,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	6782	0	0
SrcPulseCheck_M	1306785379	6842	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	6782
T3	12531	0
T6	1487	0
T7	25889	0
T11	0	69
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T40	0	1
T41	0	78
T43	0	82
T44	0	67
T52	448	0
T68	0	51
T69	0	54

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	6842
T3	267203	0
T6	125623	0
T7	126905	0
T11	0	69
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T40	0	1
T41	0	78
T43	0	82
T44	0	67
T52	107495	0
T68	0	51
T69	0	54

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T26,T27,T11
1	1	Covered	T13,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	6830	0	0
SrcPulseCheck_M	7289997	6830	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	6830
T3	267203	0
T6	125623	0
T7	126905	0
T11	0	69
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T40	0	1
T41	0	78
T43	0	82
T44	0	67
T52	107495	0
T68	0	51
T69	0	54

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	6830
T3	12531	0
T6	1487	0
T7	25889	0
T11	0	69
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T40	0	1
T41	0	78
T43	0	82
T44	0	67
T52	448	0
T68	0	51
T69	0	54

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	6879	0	0
SrcPulseCheck_M	1306785379	6938	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	6879
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	75
T12	1213	0
T26	5267	51
T27	4716	51
T41	0	53
T42	0	77
T43	0	82
T44	0	67
T52	448	0
T59	695	0
T68	0	75
T69	0	59
T70	0	67

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	6938
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	75
T12	241612	0
T26	136960	51
T27	226389	51
T41	0	54
T42	0	77
T43	0	82
T44	0	67
T52	107495	0
T59	52196	0
T68	0	75
T69	0	59
T70	0	67

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	6926	0	0
SrcPulseCheck_M	7289997	6926	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	6926
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	75
T12	241612	0
T26	136960	51
T27	226389	51
T41	0	54
T42	0	77
T43	0	82
T44	0	67
T52	107495	0
T59	52196	0
T68	0	75
T69	0	59
T70	0	67

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	6926
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	75
T12	1213	0
T26	5267	51
T27	4716	51
T41	0	54
T42	0	77
T43	0	82
T44	0	67
T52	448	0
T59	695	0
T68	0	75
T69	0	59
T70	0	67

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	6781	0	0
SrcPulseCheck_M	1306785379	6839	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	6781
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	62
T12	1213	0
T26	5267	51
T27	4716	51
T41	0	78
T42	0	63
T43	0	71
T44	0	67
T52	448	0
T59	695	0
T68	0	75
T69	0	59
T70	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	6839
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	62
T12	241612	0
T26	136960	51
T27	226389	51
T41	0	78
T42	0	63
T43	0	71
T44	0	67
T52	107495	0
T59	52196	0
T68	0	75
T69	0	59
T70	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	6827	0	0
SrcPulseCheck_M	7289997	6827	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	6827
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	62
T12	241612	0
T26	136960	51
T27	226389	51
T41	0	78
T42	0	63
T43	0	71
T44	0	67
T52	107495	0
T59	52196	0
T68	0	75
T69	0	59
T70	0	52

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	6827
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	62
T12	1213	0
T26	5267	51
T27	4716	51
T41	0	78
T42	0	63
T43	0	71
T44	0	67
T52	448	0
T59	695	0
T68	0	75
T69	0	59
T70	0	52

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	6819	0	0
SrcPulseCheck_M	1306785379	6880	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	6819
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	74
T12	1213	0
T26	5267	51
T27	4716	51
T41	0	78
T42	0	63
T43	0	62
T44	0	51
T52	448	0
T59	695	0
T68	0	75
T69	0	59
T70	0	78

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	6880
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	74
T12	241612	0
T26	136960	51
T27	226389	51
T41	0	78
T42	0	63
T43	0	62
T44	0	51
T52	107495	0
T59	52196	0
T68	0	75
T69	0	59
T70	0	78

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	6869	0	0
SrcPulseCheck_M	7289997	6869	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	6869
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	74
T12	241612	0
T26	136960	51
T27	226389	51
T41	0	78
T42	0	63
T43	0	62
T44	0	51
T52	107495	0
T59	52196	0
T68	0	75
T69	0	59
T70	0	78

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	6869
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	74
T12	1213	0
T26	5267	51
T27	4716	51
T41	0	78
T42	0	63
T43	0	62
T44	0	51
T52	448	0
T59	695	0
T68	0	75
T69	0	59
T70	0	78

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T73,T74,T17
1	1	Covered	T13,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1171	0	0
SrcPulseCheck_M	1306785379	1227	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1171
T3	12531	0
T6	1487	0
T7	25889	0
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T40	0	1
T41	0	4
T43	0	12
T44	0	1
T52	448	0
T68	0	1
T69	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1227
T3	267203	0
T6	125623	0
T7	126905	0
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T40	0	1
T41	0	4
T43	0	12
T44	0	1
T52	107495	0
T68	0	1
T69	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T13,T26,T27
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T13,T26,T27
1	0	Covered	T73,T74,T17
1	1	Covered	T13,T26,T27

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1215	0	0
SrcPulseCheck_M	7289997	1215	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1215
T3	267203	0
T6	125623	0
T7	126905	0
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T40	0	1
T41	0	4
T43	0	12
T44	0	1
T52	107495	0
T68	0	1
T69	0	4

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1215
T3	12531	0
T6	1487	0
T7	25889	0
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T40	0	1
T41	0	4
T43	0	12
T44	0	1
T52	448	0
T68	0	1
T69	0	4

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T73,T74,T17
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1149	0	0
SrcPulseCheck_M	1306785379	1205	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1149
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	3
T12	1213	0
T26	5267	1
T27	4716	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	448	0
T59	695	0
T68	0	1
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1205
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	3
T12	241612	0
T26	136960	1
T27	226389	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	107495	0
T59	52196	0
T68	0	1
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T73,T74,T17
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1193	0	0
SrcPulseCheck_M	7289997	1193	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1193
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	3
T12	241612	0
T26	136960	1
T27	226389	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	107495	0
T59	52196	0
T68	0	1
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1193
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	3
T12	1213	0
T26	5267	1
T27	4716	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	448	0
T59	695	0
T68	0	1
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T73,T74,T17
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1163	0	0
SrcPulseCheck_M	1306785379	1220	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1163
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	3
T12	1213	0
T26	5267	1
T27	4716	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	448	0
T59	695	0
T68	0	1
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1220
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	3
T12	241612	0
T26	136960	1
T27	226389	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	107495	0
T59	52196	0
T68	0	1
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T73,T74,T17
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1207	0	0
SrcPulseCheck_M	7289997	1207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1207
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	3
T12	241612	0
T26	136960	1
T27	226389	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	107495	0
T59	52196	0
T68	0	1
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1207
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	3
T12	1213	0
T26	5267	1
T27	4716	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	448	0
T59	695	0
T68	0	1
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T73,T74,T17
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1140	0	0
SrcPulseCheck_M	1306785379	1195	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1140
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	3
T12	1213	0
T26	5267	1
T27	4716	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	448	0
T59	695	0
T68	0	1
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1195
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	3
T12	241612	0
T26	136960	1
T27	226389	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	107495	0
T59	52196	0
T68	0	1
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T26,T27,T11
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T26,T27,T11
1	0	Covered	T73,T74,T17
1	1	Covered	T26,T27,T11

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1183	0	0
SrcPulseCheck_M	7289997	1183	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1183
T7	126905	0
T8	145793	0
T9	227520	0
T10	280896	0
T11	301741	3
T12	241612	0
T26	136960	1
T27	226389	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	107495	0
T59	52196	0
T68	0	1
T69	0	4
T70	0	2

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1183
T7	25889	0
T8	62662	0
T9	1525	0
T10	759	0
T11	12069	3
T12	1213	0
T26	5267	1
T27	4716	1
T41	0	4
T42	0	10
T43	0	12
T44	0	1
T52	448	0
T59	695	0
T68	0	1
T69	0	4
T70	0	2

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	7403	0	0
SrcPulseCheck_M	1306785379	7461	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	7403
T2	22284	9
T3	12531	3
T6	1487	0
T7	0	10
T11	0	69
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	51
T27	0	51
T31	0	13
T40	0	1
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	7461
T2	122562	9
T3	267203	3
T6	125623	0
T7	0	10
T11	0	69
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	51
T27	0	51
T31	0	13
T40	0	1
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	7451	0	0
SrcPulseCheck_M	7289997	7451	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	7451
T2	122562	9
T3	267203	3
T6	125623	0
T7	0	10
T11	0	69
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	51
T27	0	51
T31	0	13
T40	0	1
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	7451
T2	22284	9
T3	12531	3
T6	1487	0
T7	0	10
T11	0	69
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	51
T27	0	51
T31	0	13
T40	0	1
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	7457	0	0
SrcPulseCheck_M	1306785379	7514	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	7457
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	75
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	82
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	7514
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	75
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	82
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	7502	0	0
SrcPulseCheck_M	7289997	7502	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	7502
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	75
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	82
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	7502
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	75
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	82
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	7364	0	0
SrcPulseCheck_M	1306785379	7420	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	7364
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	62
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	71
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	7420
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	62
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	71
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	7408	0	0
SrcPulseCheck_M	7289997	7408	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	7408
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	62
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	71
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	7408
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	62
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	71
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	7372	0	0
SrcPulseCheck_M	1306785379	7430	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	7372
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	74
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	62
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	7430
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	74
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	62
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T26,T27,T11

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T26,T27,T11
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	7419	0	0
SrcPulseCheck_M	7289997	7419	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	7419
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	74
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	62
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	7419
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	74
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	51
T27	0	51
T31	0	13
T32	0	9
T33	0	5
T43	0	62
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1814	0	0
SrcPulseCheck_M	1306785379	1872	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1814
T2	22284	9
T3	12531	3
T6	1487	0
T7	0	10
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	1
T27	0	1
T31	0	13
T40	0	1
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1872
T2	122562	9
T3	267203	3
T6	125623	0
T7	0	10
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	1
T27	0	1
T31	0	13
T40	0	1
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1860	0	0
SrcPulseCheck_M	7289997	1860	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1860
T2	122562	9
T3	267203	3
T6	125623	0
T7	0	10
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	1
T27	0	1
T31	0	13
T40	0	1
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1860
T2	22284	9
T3	12531	3
T6	1487	0
T7	0	10
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	1
T27	0	1
T31	0	13
T40	0	1
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1733	0	0
SrcPulseCheck_M	1306785379	1791	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1733
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1791
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1779	0	0
SrcPulseCheck_M	7289997	1779	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1779
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1779
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1701	0	0
SrcPulseCheck_M	1306785379	1759	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1701
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1759
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1747	0	0
SrcPulseCheck_M	7289997	1747	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1747
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1747
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1710	0	0
SrcPulseCheck_M	1306785379	1766	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1710
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1766
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1755	0	0
SrcPulseCheck_M	7289997	1755	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1755
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1755
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1774	0	0
SrcPulseCheck_M	1306785379	1831	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1774
T2	22284	9
T3	12531	3
T6	1487	0
T7	0	10
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	1
T27	0	1
T31	0	13
T40	0	1
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1831
T2	122562	9
T3	267203	3
T6	125623	0
T7	0	10
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	1
T27	0	1
T31	0	13
T40	0	1
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T2,T13,T3
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T13,T3
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T13,T3

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1820	0	0
SrcPulseCheck_M	7289997	1820	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1820
T2	122562	9
T3	267203	3
T6	125623	0
T7	0	10
T11	0	3
T13	221166	1
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T23	0	1
T26	136960	1
T27	0	1
T31	0	13
T40	0	1
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1820
T2	22284	9
T3	12531	3
T6	1487	0
T7	0	10
T11	0	3
T13	456	1
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T23	0	1
T26	5267	1
T27	0	1
T31	0	13
T40	0	1
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1694	0	0
SrcPulseCheck_M	1306785379	1753	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1694
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1753
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1740	0	0
SrcPulseCheck_M	7289997	1740	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1740
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1740
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1740	0	0
SrcPulseCheck_M	1306785379	1799	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1740
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1799
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1786	0	0
SrcPulseCheck_M	7289997	1786	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1786
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1786
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	7289997	1736	0	0
SrcPulseCheck_M	1306785379	1791	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	7289997	1736
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	1306785379	1791
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	31	3	3	100.00
CONT_ASSIGN	49	0	0
CONT_ASSIGN	52	0	0
ALWAYS	55	0	0
ALWAYS	89	3	3	100.00
CONT_ASSIGN	97	1	1	100.00

Line No.	Covered	Statements
31	1	1
32	1	1
34	1	1
49		unreachable
52		unreachable
55		unreachable
56		unreachable
58		unreachable
89	1	1
90	1	1
92	1	1
97	1	1

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       34
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T2,T3,T26
1	1	Covered	T73,T74,T17

 LINE       97
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T4,T5
0	1	Covered	T2,T3,T26
1	0	Covered	T73,T74,T17
1	1	Covered	T2,T3,T26

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	31	2	2	100.00
IF	89	2	2	100.00



	LineNo.	Expression
-1-:	31	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5



	LineNo.	Expression
-1-:	89	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1306785379	1780	0	0
SrcPulseCheck_M	7289997	1780	0	0

DstPulseCheck_A

Name	Attempts	Real Successes
Total	1306785379	1780
T2	122562	9
T3	267203	1
T6	125623	0
T7	0	10
T11	0	3
T13	221166	0
T14	118539	0
T15	17434	0
T16	49325	0
T21	193547	0
T26	136960	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	107495	0

SrcPulseCheck_M

Name	Attempts	Real Successes
Total	7289997	1780
T2	22284	9
T3	12531	1
T6	1487	0
T7	0	10
T11	0	3
T13	456	0
T14	493	0
T15	436	0
T16	411	0
T21	502	0
T26	5267	1
T27	0	1
T31	0	13
T32	0	9
T33	0	5
T43	0	12
T52	448	0

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ec_rst_ctl_cdc

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_arb

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_ulp_ac_debounce_ctl_cdc