Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.56	97.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	97.56	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.56	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	2	60	96.77

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	2	29	93.55	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2033

1

T8

24

T9

52

T12

24

auto[1]

761

1

T8

8

T12

20

T32

11

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2195

1

T8

32

T9

37

T12

44

auto[1]

599

1

T9

15

T32

13

T43

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2239

1

T8

32

T9

52

T12

43

auto[1]

555

1

T12

1

T32

11

T43

3

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2146

1

T8

32

T9

36

T12

44

auto[1]

648

1

T9

16

T32

16

T43

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2599

1

T8

32

T9

37

T12

43

auto[1]

195

1

T9

15

T12

1

T40

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2593

1

T8

18

T9

48

T12

43

auto[1]

201

1

T8

14

T9

4

T12

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2434

1

T8

32

T9

25

T12

24

auto[1]

360

1

T9

27

T12

20

T40

5

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2507

1

T8

26

T9

41

T12

43

auto[1]

287

1

T8

6

T9

11

T12

1

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2531

1

T8

32

T9

36

T12

34

auto[1]

263

1

T9

16

T12

10

T41

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2126

1

T8

18

T9

41

T12

34

auto[1]

668

1

T8

14

T9

11

T12

10

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	2	29	93.55	2
Automatically Generated Cross Bins	31	2	29	93.55	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	895	1			T32	16		T43	17		T31	18
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	34	1			T350	5		T351	8		T352	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	93	1			T79	42		T334	16		T341	3
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	10	1			T127	3		T344	2		T353	2
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	84	1			T70	3		T354	3		T340	18
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	34	1			T69	7		T127	1		T245	8
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	16	1			T97	1		T348	6		T262	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	12	1			T41	1		T245	6		T355	5
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	161	1			T12	10		T41	5		T68	12
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	7	1			T40	2		T356	2		T357	3
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	53	1			T9	8		T12	10		T41	1
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	8	1			T9	8		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	25	1			T41	4		T70	2		T358	2
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	16	1			T9	7		T359	5		T360	3
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T361	2		T362	1		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	64	1			T8	8		T40	2		T97	1
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	20	1			T192	3		T356	1		T361	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	11	1			T334	4		T363	3		T364	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	5	1			T127	1		T355	4		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	31	1			T8	6		T69	6		T248	3
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	5	1			T12	1		T247	3		T365	1
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	1	1			T251	1		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	2	1			T192	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	14	1			T255	3		T352	1		T346	4
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	2	1			T366	2		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	7	1			T363	2		T367	5		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[1]	5	1			T127	1		T340	4		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	11	1			T9	4		T355	2		T368	5
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	2	1			T366	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

213

1

T12

10

T43

11

T31

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

181

1

T8

6

T9

4

T126

13

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

91

1

T8

8

T12

10

T31

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

138

1

T9

8

T127

1

T336

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

90

1

T24

8

T348

5

T334

12

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T126

10

T142

9

T185

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

24

1

T255

4

T369

3

T338

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

86

1

T12

1

T127

1

T75

13

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

49

1

T128

3

T97

1

T147

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T93

5

T370

1

T158

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T185

3

T371

2

T372

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

79

1

T335

6

T337

2

T373

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

28

1

T32

3

T40

2

T75

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

14

1

T31

3

T211

2

T164

5

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T43

3

T335

1

T249

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

78

1

T41

1

T68

4

T74

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

38

1

T74

2

T147

5

T370

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

81

1

T9

7

T41

4

T69

7

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T24

3

T68

4

T70

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T9

8

T126

10

T142

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

31

1

T32

5

T339

1

T123

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

15

1

T43

3

T40

2

T74

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T41

5

T68

4

T338

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

67

1

T41

1

T127

4

T245

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

24

1

T75

3

T336

3

T374

4

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

14

1

T126

5

T128

1

T158

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

6

1

T31

2

T211

2

T375

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

32

1

T79

14

T147

4

T373

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T32

3

T373

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

13

1

T32

5

T24

1

T249

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T250

1

T343

1

T376

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded