Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1079

1

T13

10

T14

18

T54

11

auto[1]

1061

1

T13

10

T14

22

T54

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

500

1

T13

4

T14

11

T54

2

from_0to1

503

1

T13

4

T14

10

T54

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T13

6

T14

22

T54

13

auto[1]

1060

1

T13

14

T14

18

T54

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1062

1

T13

9

T14

18

T54

10

auto[1]

1078

1

T13

11

T14

22

T54

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

68

1

T14

2

T54

1

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T14

2

T11

2

T38

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T14

1

T11

3

T46

2

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T14

2

T63

1

T46

1

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T11

1

T46

1

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

66

1

T13

1

T14

1

T11

2

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T13

1

T14

1

T60

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T54

1

T63

2

T46

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T14

2

T11

2

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T14

1

T54

1

T11

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T13

1

T63

3

T46

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T13

3

T14

1

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T14

1

T54

1

T11

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T14

3

T11

2

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

52

1

T13

2

T14

1

T11

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T14

3

T54

1

T11

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T13

11

T14

19

T54

9

auto[1]

1063

1

T13

9

T14

21

T54

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

489

1

T13

5

T14

9

T54

5

from_0to1

501

1

T13

5

T14

8

T54

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1070

1

T13

8

T14

22

T54

10

auto[1]

1070

1

T13

12

T14

18

T54

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T13

11

T14

25

T54

11

auto[1]

1059

1

T13

9

T14

15

T54

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T13

1

T54

1

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T14

1

T54

1

T63

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T54

1

T11

2

T38

2

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T14

2

T60

2

T129

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T14

1

T11

1

T63

1

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T63

1

T46

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T13

2

T54

1

T11

2

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T13

2

T54

1

T63

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T13

1

T14

3

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

47

1

T13

1

T14

1

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T14

1

T11

1

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

67

1

T13

2

T14

1

T11

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T14

1

T54

1

T11

2

auto[1]

from_0to1

auto[0]

auto[1]

65

1

T14

2

T54

1

T11

1

auto[1]

from_0to1

auto[1]

auto[0]

47

1

T13

1

T54

2

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

72

1

T14

4

T11

2

T46

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T13

9

T14

20

T54

15

auto[1]

1044

1

T13

11

T14

20

T54

5

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T13

3

T14

9

T54

7

from_0to1

514

1

T13

4

T14

9

T54

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T13

8

T14

20

T54

6

auto[1]

1062

1

T13

12

T14

20

T54

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1118

1

T13

9

T14

19

T54

12

auto[1]

1022

1

T13

11

T14

21

T54

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T13

1

T14

3

T54

1

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T54

1

T11

1

T63

2

auto[0]

from_1to0

auto[1]

auto[0]

76

1

T14

1

T54

3

T46

2

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T14

3

T11

2

T60

2

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T14

1

T54

1

T11

2

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T13

1

T54

1

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T13

1

T14

3

T54

1

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T14

1

T54

1

T11

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T14

1

T11

1

T63

1

auto[1]

from_1to0

auto[0]

auto[1]

48

1

T13

2

T38

1

T385

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T14

1

T54

1

T11

3

auto[1]

from_1to0

auto[1]

auto[1]

51

1

T54

1

T11

1

T46

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T13

1

T11

3

T46

2

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T14

2

T54

1

T11

1

auto[1]

from_0to1

auto[1]

auto[0]

73

1

T13

1

T14

1

T54

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T14

1

T11

1

T60

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T13

15

T14

18

T54

13

auto[1]

1048

1

T13

5

T14

22

T54

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

525

1

T13

4

T14

10

T54

5

from_0to1

527

1

T13

4

T14

10

T54

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T13

7

T14

20

T54

8

auto[1]

1074

1

T13

13

T14

20

T54

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1059

1

T13

13

T14

14

T54

14

auto[1]

1081

1

T13

7

T14

26

T54

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T14

1

T38

1

T60

3

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T14

3

T11

2

T46

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T13

4

T54

2

T46

1

auto[0]

from_1to0

auto[1]

auto[1]

64

1

T14

2

T11

2

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T13

2

T14

1

T54

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T14

2

T54

1

T11

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T13

1

T11

1

T38

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T14

2

T54

2

T11

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T14

1

T54

1

T46

1

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T54

1

T11

2

T63

3

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T54

1

T11

2

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T14

3

T11

1

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T14

1

T54

1

T63

2

auto[1]

from_0to1

auto[0]

auto[1]

82

1

T13

1

T14

1

T11

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T14

1

T11

2

T63

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T14

2

T11

3

T60

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1043

1

T13

11

T14

22

T54

11

auto[1]

1097

1

T13

9

T14

18

T54

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

510

1

T13

6

T14

8

T54

5

from_0to1

521

1

T13

6

T14

8

T54

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1060

1

T13

8

T14

19

T54

11

auto[1]

1080

1

T13

12

T14

21

T54

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T13

6

T14

20

T54

6

auto[1]

1087

1

T13

14

T14

20

T54

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T13

2

T14

2

T11

1

auto[0]

from_1to0

auto[0]

auto[1]

55

1

T13

1

T14

1

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

57

1

T13

1

T14

2

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T54

1

T11

1

T38

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T13

1

T38

1

T143

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T14

1

T54

1

T11

2

auto[0]

from_0to1

auto[1]

auto[0]

49

1

T11

3

T141

1

T385

1

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T13

1

T14

3

T11

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T14

1

T54

2

T11

2

auto[1]

from_1to0

auto[0]

auto[1]

82

1

T13

1

T14

2

T54

1

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T11

2

T46

1

T129

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T13

1

T11

1

T46

2

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T14

1

T54

1

T11

2

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T13

2

T14

1

T54

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T60

1

T129

2

T143

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T13

2

T14

2

T54

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1109

1

T13

11

T14

19

T54

6

auto[1]

1031

1

T13

9

T14

21

T54

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

539

1

T13

5

T14

12

T54

6

from_0to1

533

1

T13

5

T14

13

T54

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1048

1

T13

9

T14

17

T54

9

auto[1]

1092

1

T13

11

T14

23

T54

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1066

1

T13

9

T14

15

T54

7

auto[1]

1074

1

T13

11

T14

25

T54

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T14

1

T11

1

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T13

1

T14

2

T54

1

auto[0]

from_1to0

auto[1]

auto[0]

81

1

T14

2

T11

3

T63

1

auto[0]

from_1to0

auto[1]

auto[1]

83

1

T14

2

T54

1

T11

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T14

2

T54

1

T11

3

auto[0]

from_0to1

auto[0]

auto[1]

80

1

T13

1

T14

1

T11

3

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T13

1

T11

1

T46

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T14

2

T38

1

T60

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T13

2

T14

1

T54

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T13

1

T14

2

T63

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T13

1

T14

1

T54

1

auto[1]

from_1to0

auto[1]

auto[1]

57

1

T14

1

T54

2

T63

1

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T14

1

T54

1

T63

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T13

1

T14

2

T63

2

auto[1]

from_0to1

auto[1]

auto[0]

79

1

T13

2

T14

3

T54

1

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T14

2

T54

2

T11

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T13

11

T14

19

T54

8

auto[1]

1052

1

T13

9

T14

21

T54

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

516

1

T13

3

T14

10

T54

5

from_0to1

520

1

T13

4

T14

9

T54

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T13

11

T14

21

T54

8

auto[1]

1077

1

T13

9

T14

19

T54

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T13

12

T14

18

T54

9

auto[1]

1073

1

T13

8

T14

22

T54

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

69

1

T13

2

T14

3

T11

2

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T11

2

T63

1

T46

2

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T14

2

T54

2

T11

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T13

1

T14

2

T11

3

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T14

1

T11

1

T38

2

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T13

2

T54

2

T11

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T46

1

T38

1

T60

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T14

2

T11

3

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T14

1

T54

1

T11

1

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T14

1

T11

2

T38

1

auto[1]

from_1to0

auto[1]

auto[0]

60

1

T14

1

T63

1

T129

2

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T54

2

T38

1

T60

2

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T13

1

T14

1

T54

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T14

2

T11

3

T63

1

auto[1]

from_0to1

auto[1]

auto[0]

75

1

T14

2

T11

1

T60

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T13

1

T14

1

T54

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1103

1

T13

14

T14

20

T54

9

auto[1]

1037

1

T13

6

T14

20

T54

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T13

4

T14

10

T54

6

from_0to1

507

1

T13

4

T14

10

T54

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T13

6

T14

17

T54

10

auto[1]

1073

1

T13

14

T14

23

T54

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1092

1

T13

12

T14

19

T54

10

auto[1]

1048

1

T13

8

T14

21

T54

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

65

1

T14

1

T11

1

T63

1

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T13

1

T14

3

T38

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T54

3

T11

2

T38

1

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T13

1

T14

1

T54

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T13

1

T11

2

T38

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T14

2

T54

1

T11

2

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T13

2

T14

1

T46

1

auto[0]

from_0to1

auto[1]

auto[1]

79

1

T13

1

T54

1

T11

1

auto[1]

from_1to0

auto[0]

auto[0]

80

1

T14

1

T54

1

T11

4

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T13

1

T54

1

T63

2

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T13

1

T14

4

T63

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T11

1

T46

2

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T46

2

T38

1

T129

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T14

1

T54

1

T38

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T14

2

T54

2

T11

2

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T14

4

T54

1

T11

2