Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	157438	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

120148

1

T4

21

T5

14

T1

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141939	1			T4	2		T5	16		T1	11
values[0x0]	67554	1			T4	29		T5	3		T1	2
values[0x1]	68093	1			T4	32		T5	4		T1	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	127479	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

150107

1

T4

28

T5

15

T1

6

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1055	1			T18	3		T8	5		T9	6
valid_sources[0x01]	1144	1			T13	3		T3	1		T18	1
valid_sources[0x02]	1216	1			T4	2		T18	1		T8	2
valid_sources[0x03]	804	1			T13	5		T18	2		T49	1
valid_sources[0x04]	941	1			T3	1		T8	3		T9	3
valid_sources[0x05]	886	1			T18	1		T25	1		T8	3
valid_sources[0x06]	821	1			T8	4		T9	5		T12	11
valid_sources[0x07]	855	1			T18	1		T7	1		T8	3
valid_sources[0x08]	2091	1			T18	2		T25	2		T8	4
valid_sources[0x09]	980	1			T13	3		T18	1		T8	3
valid_sources[0x0a]	1618	1			T4	1		T18	3		T25	1
valid_sources[0x0b]	776	1			T18	3		T8	8		T9	2
valid_sources[0x0c]	868	1			T4	3		T13	3		T18	1
valid_sources[0x0d]	1296	1			T8	4		T9	2		T12	4
valid_sources[0x0e]	993	1			T8	3		T53	3		T9	4
valid_sources[0x0f]	1009	1			T13	3		T3	1		T8	2
valid_sources[0x10]	943	1			T8	7		T9	2		T12	6
valid_sources[0x11]	957	1			T4	1		T18	2		T25	1
valid_sources[0x12]	880	1			T18	1		T49	1		T25	1
valid_sources[0x13]	804	1			T18	4		T49	1		T8	3
valid_sources[0x14]	802	1			T13	6		T18	1		T49	1
valid_sources[0x15]	996	1			T49	1		T8	4		T9	7
valid_sources[0x16]	827	1			T8	4		T9	1		T26	1
valid_sources[0x17]	752	1			T18	4		T8	6		T9	5
valid_sources[0x18]	1661	1			T13	2		T15	1		T18	5
valid_sources[0x19]	1114	1			T18	2		T8	7		T62	1
valid_sources[0x1a]	928	1			T4	1		T25	1		T8	5
valid_sources[0x1b]	908	1			T15	2		T7	1		T8	11
valid_sources[0x1c]	1024	1			T18	2		T8	2		T9	5
valid_sources[0x1d]	1440	1			T8	5		T52	5		T12	5
valid_sources[0x1e]	793	1			T4	3		T5	5		T18	1
valid_sources[0x1f]	862	1			T13	2		T18	3		T8	5
valid_sources[0x20]	880	1			T15	1		T18	1		T8	6
valid_sources[0x21]	929	1			T8	2		T9	2		T12	2
valid_sources[0x22]	850	1			T15	1		T18	3		T8	4
valid_sources[0x23]	1497	1			T18	5		T8	5		T9	4
valid_sources[0x24]	890	1			T15	1		T25	2		T8	4
valid_sources[0x25]	872	1			T18	1		T49	1		T8	4
valid_sources[0x26]	776	1			T18	1		T8	3		T9	4
valid_sources[0x27]	868	1			T1	3		T18	6		T8	3
valid_sources[0x28]	1259	1			T18	1		T51	2		T8	1
valid_sources[0x29]	868	1			T8	9		T54	14		T9	4
valid_sources[0x2a]	1118	1			T18	1		T8	4		T9	5
valid_sources[0x2b]	940	1			T4	4		T13	5		T15	1
valid_sources[0x2c]	920	1			T15	2		T18	1		T8	9
valid_sources[0x2d]	838	1			T13	3		T15	1		T3	6
valid_sources[0x2e]	1084	1			T18	4		T49	1		T50	1
valid_sources[0x2f]	981	1			T8	2		T9	3		T12	1
valid_sources[0x30]	744	1			T8	3		T9	1		T32	2
valid_sources[0x31]	1110	1			T8	3		T9	5		T12	1
valid_sources[0x32]	1993	1			T13	3		T8	4		T9	7
valid_sources[0x33]	859	1			T8	4		T9	3		T32	2
valid_sources[0x34]	962	1			T13	4		T18	4		T7	1
valid_sources[0x35]	1400	1			T18	2		T8	1		T9	5
valid_sources[0x36]	819	1			T13	2		T18	1		T25	1
valid_sources[0x37]	815	1			T15	1		T8	1		T9	6
valid_sources[0x38]	1048	1			T4	1		T5	1		T18	2
valid_sources[0x39]	932	1			T15	2		T8	4		T9	2
valid_sources[0x3a]	974	1			T18	4		T8	6		T9	5
valid_sources[0x3b]	1088	1			T18	1		T8	3		T9	1
valid_sources[0x3c]	1875	1			T13	3		T8	2		T9	6
valid_sources[0x3d]	914	1			T18	2		T8	4		T9	6
valid_sources[0x3e]	876	1			T18	3		T25	1		T8	6
valid_sources[0x3f]	1048	1			T15	1		T18	1		T25	1
valid_sources[0x40]	1415	1			T18	7		T8	5		T53	2
valid_sources[0x41]	1047	1			T15	1		T17	1		T18	1
valid_sources[0x42]	895	1			T27	17		T9	6		T28	1
valid_sources[0x43]	798	1			T4	3		T8	5		T9	4
valid_sources[0x44]	1790	1			T13	1		T18	2		T8	3
valid_sources[0x45]	1091	1			T4	2		T18	1		T8	9
valid_sources[0x46]	1462	1			T3	5		T18	1		T49	2
valid_sources[0x47]	1208	1			T18	1		T9	4		T26	1
valid_sources[0x48]	1573	1			T18	1		T25	1		T8	9
valid_sources[0x49]	1037	1			T18	3		T8	4		T9	3
valid_sources[0x4a]	1774	1			T3	1		T8	7		T9	8
valid_sources[0x4b]	1074	1			T4	4		T18	3		T8	5
valid_sources[0x4c]	784	1			T18	6		T25	2		T8	3
valid_sources[0x4d]	2004	1			T18	1		T49	1		T8	3
valid_sources[0x4e]	920	1			T8	3		T9	2		T12	6
valid_sources[0x4f]	858	1			T16	10		T8	4		T9	3
valid_sources[0x50]	819	1			T15	3		T8	2		T9	4
valid_sources[0x51]	1036	1			T1	2		T18	1		T8	5
valid_sources[0x52]	1011	1			T4	4		T15	4		T18	6
valid_sources[0x53]	806	1			T18	5		T49	1		T8	6
valid_sources[0x54]	1004	1			T15	2		T18	7		T7	1
valid_sources[0x55]	901	1			T18	1		T25	1		T8	11
valid_sources[0x56]	1036	1			T49	1		T25	1		T8	3
valid_sources[0x57]	947	1			T18	2		T8	7		T53	1
valid_sources[0x58]	1627	1			T18	2		T8	6		T9	2
valid_sources[0x59]	912	1			T18	1		T8	3		T9	5
valid_sources[0x5a]	977	1			T18	3		T8	3		T9	3
valid_sources[0x5b]	997	1			T18	7		T8	5		T9	7
valid_sources[0x5c]	953	1			T18	4		T8	4		T53	1
valid_sources[0x5d]	904	1			T13	4		T15	2		T8	4
valid_sources[0x5e]	836	1			T4	1		T13	3		T18	2
valid_sources[0x5f]	1263	1			T1	1		T18	1		T7	1
valid_sources[0x60]	962	1			T3	1		T18	1		T8	2
valid_sources[0x61]	1020	1			T13	1		T18	2		T8	3
valid_sources[0x62]	960	1			T13	4		T15	1		T18	2
valid_sources[0x63]	948	1			T4	1		T13	6		T8	3
valid_sources[0x64]	1672	1			T25	1		T8	3		T9	4
valid_sources[0x65]	828	1			T1	1		T18	1		T8	3
valid_sources[0x66]	1093	1			T18	3		T25	1		T8	3
valid_sources[0x67]	1012	1			T4	3		T15	1		T8	3
valid_sources[0x68]	1094	1			T13	1		T18	2		T8	3
valid_sources[0x69]	1409	1			T4	1		T18	1		T49	1
valid_sources[0x6a]	1718	1			T18	1		T8	5		T9	4
valid_sources[0x6b]	1043	1			T8	7		T9	4		T12	3
valid_sources[0x6c]	1064	1			T13	2		T15	1		T18	5
valid_sources[0x6d]	989	1			T13	1		T18	2		T8	5
valid_sources[0x6e]	1705	1			T13	3		T8	5		T9	1
valid_sources[0x6f]	824	1			T18	2		T7	1		T8	4
valid_sources[0x70]	1060	1			T13	2		T18	4		T8	6
valid_sources[0x71]	874	1			T8	3		T9	2		T12	2
valid_sources[0x72]	837	1			T3	2		T25	1		T7	1
valid_sources[0x73]	1123	1			T18	1		T8	4		T9	2
valid_sources[0x74]	951	1			T8	2		T52	1		T9	8
valid_sources[0x75]	829	1			T8	10		T9	4		T12	9
valid_sources[0x76]	901	1			T18	4		T8	4		T9	4
valid_sources[0x77]	1331	1			T18	2		T25	1		T8	4
valid_sources[0x78]	867	1			T18	3		T8	3		T9	5
valid_sources[0x79]	801	1			T4	1		T8	6		T9	7
valid_sources[0x7a]	795	1			T13	2		T18	1		T8	7
valid_sources[0x7b]	1297	1			T18	2		T8	3		T9	1
valid_sources[0x7c]	1882	1			T15	1		T18	2		T8	2
valid_sources[0x7d]	871	1			T18	4		T8	5		T9	4
valid_sources[0x7e]	1058	1			T13	4		T18	1		T8	2
valid_sources[0x7f]	1800	1			T18	4		T25	1		T8	3
valid_sources[0x80]	1679	1			T4	3		T13	4		T18	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63803

1

T4

1

T5

11

T1

1

values[0x0]

all_enables

biggest_size

33096

1

T4

16

T5

1

T13

17

values[0x1]

all_enables

biggest_size

23249

1

T4

4

T5

2

T1

1