Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T27,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T13,T27,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T13,T27,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T27,T28
1	0	Covered	T4,T5,T1
1	1	Covered	T13,T27,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T28
0	1	Covered	T46,T102,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T27,T28
0	1	Covered	T13,T27,T28
1	0	Covered	T55,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T27,T28
1	-	Covered	T13,T27,T28

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T13,T27,T28
DetectSt	168	Covered	T13,T27,T28
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T13,T27,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T27,T28
DebounceSt->IdleSt	163	Covered	T28,T44,T47
DetectSt->IdleSt	186	Covered	T46,T102,T107
DetectSt->StableSt	191	Covered	T13,T27,T28
IdleSt->DebounceSt	148	Covered	T13,T27,T28
StableSt->IdleSt	206	Covered	T13,T27,T28

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T13,T27,T28
0	1	Covered	T13,T27,T28
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T13,T27,T28
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T13,T27,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T27,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T44,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T13,T27,T28
DetectSt	-	-	-	-	1	-	-	Covered	T46,T102,T107
DetectSt	-	-	-	-	0	1	-	Covered	T13,T27,T28
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T27,T28
StableSt	-	-	-	-	-	-	0	Covered	T13,T27,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	256	0	0
CntIncr_A	9094833	212550	0	0
CntNoWrap_A	9094833	8426913	0	0
DetectStDropOut_A	9094833	3	0	0
DetectedOut_A	9094833	847	0	0
DetectedPulseOut_A	9094833	115	0	0
DisabledIdleSt_A	9094833	8208632	0	0
DisabledNoDetection_A	9094833	8210988	0	0
EnterDebounceSt_A	9094833	139	0	0
EnterDetectSt_A	9094833	118	0	0
EnterStableSt_A	9094833	115	0	0
PulseIsPulse_A	9094833	115	0	0
StayInStableSt	9094833	732	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	6927	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	113	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	256	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	2	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	4	0	0
T28	0	5	0	0
T38	0	4	0	0
T44	0	1	0	0
T46	0	6	0	0
T47	0	1	0	0
T48	0	6	0	0
T49	430	0	0	0
T91	0	4	0	0
T92	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	212550	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	55	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	73	0	0
T28	0	227	0	0
T38	0	87	0	0
T44	0	15	0	0
T46	0	194	0	0
T47	0	21	0	0
T48	0	94	0	0
T49	430	0	0	0
T91	0	86	0	0
T92	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426913	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	441	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3	0	0
T46	2439	1	0	0
T47	656	0	0	0
T57	2176	0	0	0
T66	753	0	0	0
T69	16314	0	0	0
T102	0	1	0	0
T107	0	1	0	0
T109	522	0	0	0
T110	420	0	0	0
T111	454	0	0	0
T112	422	0	0	0
T113	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	847	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	5	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	8	0	0
T28	0	18	0	0
T38	0	10	0	0
T46	0	8	0	0
T48	0	20	0	0
T49	430	0	0	0
T91	0	13	0	0
T92	0	11	0	0
T114	0	18	0	0
T118	0	12	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	115	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	1	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T38	0	2	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	430	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T114	0	2	0	0
T118	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8208632	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	343	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8210988	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	346	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	139	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	1	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	2	0	0
T28	0	3	0	0
T38	0	2	0	0
T44	0	1	0	0
T46	0	3	0	0
T47	0	1	0	0
T48	0	3	0	0
T49	430	0	0	0
T91	0	2	0	0
T92	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	118	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	1	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T38	0	2	0	0
T46	0	3	0	0
T48	0	3	0	0
T49	430	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T114	0	2	0	0
T118	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	115	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	1	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T38	0	2	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	430	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T114	0	2	0	0
T118	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	115	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	1	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T38	0	2	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	430	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T114	0	2	0	0
T118	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	732	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	4	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	6	0	0
T28	0	16	0	0
T38	0	8	0	0
T46	0	6	0	0
T48	0	17	0	0
T49	430	0	0	0
T91	0	11	0	0
T92	0	10	0	0
T114	0	16	0	0
T118	0	10	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6927	0	0
T1	703	1	0	0
T2	107379	1	0	0
T3	823731	7	0	0
T4	528	5	0	0
T5	1054	5	0	0
T13	2046	11	0	0
T14	2737	14	0	0
T15	522	3	0	0
T16	413	0	0	0
T17	427	2	0	0
T18	0	17	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	113	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	1	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T27	0	2	0	0
T28	0	2	0	0
T38	0	2	0	0
T46	0	2	0	0
T48	0	3	0	0
T49	430	0	0	0
T91	0	2	0	0
T92	0	1	0	0
T114	0	2	0	0
T118	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T23,T24
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T24
0	1	Covered	T38,T87,T88
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T24
0	1	Unreachable
1	0	Covered	T3,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T23,T24
DetectSt	168	Covered	T3,T23,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T23,T24
DebounceSt->IdleSt	163	Covered	T72,T123,T55
DetectSt->IdleSt	186	Covered	T38,T87,T88
DetectSt->StableSt	191	Covered	T3,T23,T24
IdleSt->DebounceSt	148	Covered	T3,T23,T24
StableSt->IdleSt	206	Covered	T3,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T23,T24
0	1	Covered	T3,T23,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T23,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T72,T123,T124
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T38,T87,T88
DetectSt	-	-	-	-	0	1	-	Covered	T3,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T3,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	206	0	0
CntIncr_A	9094833	186482	0	0
CntNoWrap_A	9094833	8426963	0	0
DetectStDropOut_A	9094833	5	0	0
DetectedOut_A	9094833	271524	0	0
DetectedPulseOut_A	9094833	73	0	0
DisabledIdleSt_A	9094833	6784059	0	0
DisabledNoDetection_A	9094833	6786453	0	0
EnterDebounceSt_A	9094833	129	0	0
EnterDetectSt_A	9094833	78	0	0
EnterStableSt_A	9094833	73	0	0
PulseIsPulse_A	9094833	73	0	0
StayInStableSt	9094833	271451	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	6927	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_sticky_sva.StableStDropOut_A	9094833	933976	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	206	0	0
T3	823731	2	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	4	0	0
T24	0	2	0	0
T25	495	0	0	0
T38	0	8	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	6	0	0
T60	0	2	0	0
T61	0	2	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	186482	0	0
T3	823731	64387	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	124	0	0
T24	0	28	0	0
T25	495	0	0	0
T38	0	172	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	153	0	0
T60	0	41	0	0
T61	0	63	0	0
T71	0	31	0	0
T72	0	42	0	0
T73	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426963	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823328	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	5	0	0
T38	149237	3	0	0
T58	1618	0	0	0
T59	941	0	0	0
T60	2801	0	0	0
T70	15041	0	0	0
T87	0	1	0	0
T88	0	1	0	0
T125	527	0	0	0
T126	38282	0	0	0
T127	18276	0	0	0
T128	30352	0	0	0
T129	510	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	271524	0	0
T3	823731	170803	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	461	0	0
T24	0	118	0	0
T25	495	0	0	0
T38	0	44	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	331	0	0
T60	0	153	0	0
T61	0	322	0	0
T71	0	107	0	0
T73	0	72	0	0
T89	0	156	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	73	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6784059	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	588086	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6786453	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	588087	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	129	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	4	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	78	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	4	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	73	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	73	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T71	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	271451	0	0
T3	823731	170802	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	459	0	0
T24	0	117	0	0
T25	495	0	0	0
T38	0	43	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	328	0	0
T60	0	152	0	0
T61	0	321	0	0
T71	0	106	0	0
T73	0	71	0	0
T89	0	155	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6927	0	0
T1	703	1	0	0
T2	107379	1	0	0
T3	823731	7	0	0
T4	528	5	0	0
T5	1054	5	0	0
T13	2046	11	0	0
T14	2737	14	0	0
T15	522	3	0	0
T16	413	0	0	0
T17	427	2	0	0
T18	0	17	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	933976	0	0
T3	823731	37	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	149	0	0
T24	0	522	0	0
T25	495	0	0	0
T38	0	56146	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	598	0	0
T60	0	165	0	0
T61	0	368	0	0
T71	0	179187	0	0
T73	0	60	0	0
T89	0	105	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T23,T24
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T38
0	1	Covered	T3,T58,T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T38
0	1	Unreachable
1	0	Covered	T3,T23,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T23,T24
DetectSt	168	Covered	T3,T23,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T23,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T23,T38
DebounceSt->IdleSt	163	Covered	T24,T58,T60
DetectSt->IdleSt	186	Covered	T3,T58,T86
DetectSt->StableSt	191	Covered	T3,T23,T38
IdleSt->DebounceSt	148	Covered	T3,T23,T24
StableSt->IdleSt	206	Covered	T3,T23,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T23,T24
0	1	Covered	T3,T23,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T23,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T23,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T58,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T3,T58,T86
DetectSt	-	-	-	-	0	1	-	Covered	T3,T23,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T23,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T23,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	224	0	0
CntIncr_A	9094833	94379	0	0
CntNoWrap_A	9094833	8426945	0	0
DetectStDropOut_A	9094833	14	0	0
DetectedOut_A	9094833	418084	0	0
DetectedPulseOut_A	9094833	72	0	0
DisabledIdleSt_A	9094833	6784059	0	0
DisabledNoDetection_A	9094833	6786453	0	0
EnterDebounceSt_A	9094833	139	0	0
EnterDetectSt_A	9094833	86	0	0
EnterStableSt_A	9094833	72	0	0
PulseIsPulse_A	9094833	72	0	0
StayInStableSt	9094833	418012	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_sticky_sva.StableStDropOut_A	9094833	891249	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	224	0	0
T3	823731	4	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	4	0	0
T24	0	3	0	0
T25	495	0	0	0
T38	0	2	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	9	0	0
T60	0	4	0	0
T61	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	94379	0	0
T3	823731	42	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	108	0	0
T24	0	243	0	0
T25	495	0	0	0
T38	0	26415	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	474	0	0
T60	0	388	0	0
T61	0	72	0	0
T71	0	48	0	0
T72	0	89	0	0
T73	0	67	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426945	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823326	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	14	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	1	0	0
T86	0	1	0	0
T130	0	1	0	0
T131	0	1	0	0
T132	0	4	0	0
T133	0	3	0	0
T134	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	418084	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	497	0	0
T25	495	0	0	0
T38	0	114045	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	81	0	0
T61	0	297	0	0
T71	0	177	0	0
T72	0	79	0	0
T73	0	78	0	0
T89	0	54	0	0
T122	0	54	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	72	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	2	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6784059	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	588086	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6786453	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	588087	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	139	0	0
T3	823731	2	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	3	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	6	0	0
T60	0	4	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	86	0	0
T3	823731	2	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0
T122	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	72	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	2	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	72	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	2	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T89	0	1	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	418012	0	0
T23	1827	495	0	0
T31	22349	0	0	0
T32	20103	0	0	0
T38	0	114044	0	0
T40	12838	0	0	0
T42	664	0	0	0
T43	31380	0	0	0
T56	567	0	0	0
T58	0	79	0	0
T61	0	296	0	0
T62	493	0	0	0
T71	0	176	0	0
T72	0	78	0	0
T73	0	77	0	0
T89	0	53	0	0
T90	485	0	0	0
T122	0	53	0	0
T135	0	9	0	0
T136	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	891249	0	0
T3	823731	117599	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	127	0	0
T25	495	0	0	0
T38	0	105	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	230	0	0
T61	0	376	0	0
T71	0	179090	0	0
T72	0	62	0	0
T73	0	54	0	0
T89	0	222	0	0
T122	0	532	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T23,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T23,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T23,T24
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T23,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T24
0	1	Covered	T60,T81,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T23,T24
0	1	Unreachable
1	0	Covered	T3,T23,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T23,T24
DetectSt	168	Covered	T3,T23,T24
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T23,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T23,T24
DebounceSt->IdleSt	163	Covered	T60,T73,T89
DetectSt->IdleSt	186	Covered	T60,T81,T82
DetectSt->StableSt	191	Covered	T3,T23,T24
IdleSt->DebounceSt	148	Covered	T3,T23,T24
StableSt->IdleSt	206	Covered	T3,T23,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T23,T24
0	1	Covered	T3,T23,T24
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T23,T24
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T23,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T23,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T60,T73,T89
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T23,T24
DetectSt	-	-	-	-	1	-	-	Covered	T60,T81,T82
DetectSt	-	-	-	-	0	1	-	Covered	T3,T23,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T23,T24
StableSt	-	-	-	-	-	-	0	Covered	T3,T23,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	251	0	0
CntIncr_A	9094833	217724	0	0
CntNoWrap_A	9094833	8426918	0	0
DetectStDropOut_A	9094833	34	0	0
DetectedOut_A	9094833	476023	0	0
DetectedPulseOut_A	9094833	58	0	0
DisabledIdleSt_A	9094833	6784059	0	0
DisabledNoDetection_A	9094833	6786453	0	0
EnterDebounceSt_A	9094833	160	0	0
EnterDetectSt_A	9094833	92	0	0
EnterStableSt_A	9094833	58	0	0
PulseIsPulse_A	9094833	58	0	0
StayInStableSt	9094833	475965	0	0
gen_high_event_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_sticky_sva.StableStDropOut_A	9094833	621632	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	251	0	0
T3	823731	2	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	4	0	0
T24	0	2	0	0
T25	495	0	0	0
T38	0	2	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	6	0	0
T60	0	5	0	0
T61	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0
T73	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	217724	0	0
T3	823731	71	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	68	0	0
T24	0	81	0	0
T25	495	0	0	0
T38	0	22	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	222	0	0
T60	0	168	0	0
T61	0	89	0	0
T71	0	36214	0	0
T72	0	10	0	0
T73	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426918	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823328	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	34	0	0
T60	2801	1	0	0
T81	0	5	0	0
T82	0	1	0	0
T86	0	1	0	0
T126	38282	0	0	0
T127	18276	0	0	0
T128	30352	0	0	0
T129	510	0	0	0
T130	0	2	0	0
T132	0	3	0	0
T137	0	1	0	0
T138	0	2	0	0
T139	0	3	0	0
T140	0	3	0	0
T141	504	0	0	0
T142	39254	0	0	0
T143	502	0	0	0
T144	460	0	0	0
T145	447	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	476023	0	0
T3	823731	87	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	174	0	0
T24	0	361	0	0
T25	495	0	0	0
T38	0	146	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	798	0	0
T61	0	617	0	0
T71	0	143066	0	0
T72	0	7	0	0
T73	0	1	0	0
T122	0	465	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	58	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T122	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6784059	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	588086	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6786453	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	588087	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	160	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T60	0	4	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	92	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T60	0	1	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	58	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T122	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	58	0	0
T3	823731	1	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	2	0	0
T24	0	1	0	0
T25	495	0	0	0
T38	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	3	0	0
T61	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T73	0	1	0	0
T122	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	475965	0	0
T3	823731	86	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	172	0	0
T24	0	360	0	0
T25	495	0	0	0
T38	0	145	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	795	0	0
T61	0	616	0	0
T71	0	143065	0	0
T72	0	6	0	0
T122	0	464	0	0
T135	0	1	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	621632	0	0
T3	823731	235078	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T23	0	503	0	0
T24	0	243	0	0
T25	495	0	0	0
T38	0	140414	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T58	0	98	0	0
T61	0	59	0	0
T71	0	47	0	0
T72	0	233	0	0
T73	0	38	0	0
T122	0	73	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T36
1	0	Covered	T4,T5,T1
1	1	Covered	T11,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T37
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T36,T37
0	1	Covered	T11,T37,T146
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T36,T37
1	-	Covered	T11,T37,T146

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T36,T37
DetectSt	168	Covered	T11,T36,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T36,T37
DebounceSt->IdleSt	163	Covered	T147,T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T36,T37
IdleSt->DebounceSt	148	Covered	T11,T36,T37
StableSt->IdleSt	206	Covered	T11,T37,T146

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T36,T37
0	1	Covered	T11,T36,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T36,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T147
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T36,T37
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T37,T146
StableSt	-	-	-	-	-	-	0	Covered	T11,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	86	0	0
CntIncr_A	9094833	107472	0	0
CntNoWrap_A	9094833	8427083	0	0
DetectStDropOut_A	9094833	0	0	0
DetectedOut_A	9094833	3268	0	0
DetectedPulseOut_A	9094833	42	0	0
DisabledIdleSt_A	9094833	8186986	0	0
DisabledNoDetection_A	9094833	8189326	0	0
EnterDebounceSt_A	9094833	44	0	0
EnterDetectSt_A	9094833	42	0	0
EnterStableSt_A	9094833	42	0	0
PulseIsPulse_A	9094833	42	0	0
StayInStableSt	9094833	3204	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	86	0	0
T11	8504	4	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	2	0	0
T37	0	4	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	2	0	0
T83	0	4	0	0
T136	402	0	0	0
T146	0	2	0	0
T147	0	1	0	0
T148	0	2	0	0
T149	0	4	0	0
T150	0	2	0	0
T151	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	107472	0	0
T11	8504	22	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	43	0	0
T37	0	28	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	46	0	0
T83	0	32	0	0
T136	402	0	0	0
T146	0	18	0	0
T147	0	15	0	0
T148	0	37	0	0
T149	0	144	0	0
T150	0	92	0	0
T151	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427083	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3268	0	0
T11	8504	122	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	46	0	0
T37	0	45	0	0
T42	664	0	0	0
T55	0	15	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	39	0	0
T83	0	99	0	0
T136	402	0	0	0
T146	0	40	0	0
T148	0	90	0	0
T149	0	80	0	0
T150	0	257	0	0
T151	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	42	0	0
T11	8504	2	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	1	0	0
T37	0	2	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	1	0	0
T83	0	2	0	0
T136	402	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8186986	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8189326	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	44	0	0
T11	8504	2	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	1	0	0
T37	0	2	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	1	0	0
T83	0	2	0	0
T136	402	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	42	0	0
T11	8504	2	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	1	0	0
T37	0	2	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	1	0	0
T83	0	2	0	0
T136	402	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	42	0	0
T11	8504	2	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	1	0	0
T37	0	2	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	1	0	0
T83	0	2	0	0
T136	402	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	42	0	0
T11	8504	2	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	1	0	0
T37	0	2	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	1	0	0
T83	0	2	0	0
T136	402	0	0	0
T146	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T151	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3204	0	0
T11	8504	119	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	44	0	0
T37	0	42	0	0
T42	664	0	0	0
T55	0	14	0	0
T56	567	0	0	0
T62	493	0	0	0
T75	0	37	0	0
T83	0	96	0	0
T136	402	0	0	0
T146	0	39	0	0
T148	0	88	0	0
T149	0	77	0	0
T150	0	256	0	0
T151	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	19	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T37	0	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T83	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	422	0	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T33,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T33,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T33,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T33
1	0	Covered	T4,T1,T13
1	1	Covered	T11,T33,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T37
0	1	Covered	T155,T156,T157
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T37
0	1	Covered	T11,T33,T37
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T33,T37
1	-	Covered	T11,T33,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T33,T37
DetectSt	168	Covered	T11,T33,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T33,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T33,T37
DebounceSt->IdleSt	163	Covered	T11,T38,T72
DetectSt->IdleSt	186	Covered	T155,T156,T157
DetectSt->StableSt	191	Covered	T11,T33,T37
IdleSt->DebounceSt	148	Covered	T11,T33,T37
StableSt->IdleSt	206	Covered	T11,T33,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T33,T37
0	1	Covered	T11,T33,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T33,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T33,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T33,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T72,T158
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T33,T37
DetectSt	-	-	-	-	1	-	-	Covered	T155,T156,T157
DetectSt	-	-	-	-	0	1	-	Covered	T11,T33,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T33,T37
StableSt	-	-	-	-	-	-	0	Covered	T11,T33,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	131	0	0
CntIncr_A	9094833	88022	0	0
CntNoWrap_A	9094833	8427038	0	0
DetectStDropOut_A	9094833	4	0	0
DetectedOut_A	9094833	39408	0	0
DetectedPulseOut_A	9094833	59	0	0
DisabledIdleSt_A	9094833	8215938	0	0
DisabledNoDetection_A	9094833	8218278	0	0
EnterDebounceSt_A	9094833	69	0	0
EnterDetectSt_A	9094833	63	0	0
EnterStableSt_A	9094833	59	0	0
PulseIsPulse_A	9094833	59	0	0
StayInStableSt	9094833	39325	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	2675	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	131	0	0
T11	8504	3	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	4	0	0
T36	583	0	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	3	0	0
T136	402	0	0	0
T146	0	4	0	0
T151	422	0	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	88022	0	0
T11	8504	22	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	82	0	0
T36	583	0	0	0
T37	0	28	0	0
T38	0	228	0	0
T39	0	89	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	94	0	0
T136	402	0	0	0
T146	0	36	0	0
T151	422	0	0	0
T159	0	41	0	0
T160	0	65316	0	0
T161	0	86	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427038	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	4	0	0
T155	1988	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T162	0	1	0	0
T163	4817	0	0	0
T164	33684	0	0	0
T165	512	0	0	0
T166	448	0	0	0
T167	610	0	0	0
T168	423	0	0	0
T169	401	0	0	0
T170	522	0	0	0
T171	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	39408	0	0
T11	8504	43	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	251	0	0
T36	583	0	0	0
T37	0	114	0	0
T38	0	273	0	0
T39	0	79	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	39	0	0
T136	402	0	0	0
T146	0	64	0	0
T151	422	0	0	0
T159	0	41	0	0
T160	0	178	0	0
T161	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	59	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	1	0	0
T136	402	0	0	0
T146	0	2	0	0
T151	422	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8215938	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8218278	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	69	0	0
T11	8504	2	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	2	0	0
T136	402	0	0	0
T146	0	2	0	0
T151	422	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	63	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	1	0	0
T136	402	0	0	0
T146	0	2	0	0
T151	422	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	59	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	1	0	0
T136	402	0	0	0
T146	0	2	0	0
T151	422	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	59	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	1	0	0
T136	402	0	0	0
T146	0	2	0	0
T151	422	0	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	39325	0	0
T11	8504	42	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	248	0	0
T36	583	0	0	0
T37	0	112	0	0
T38	0	271	0	0
T39	0	78	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	38	0	0
T136	402	0	0	0
T146	0	61	0	0
T151	422	0	0	0
T159	0	40	0	0
T160	0	177	0	0
T161	0	35	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	2675	0	0
T1	703	1	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T4	528	4	0	0
T5	1054	0	0	0
T6	0	13	0	0
T13	2046	11	0	0
T14	2737	16	0	0
T15	522	6	0	0
T16	413	0	0	0
T17	427	2	0	0
T25	0	3	0	0
T49	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	34	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	1	0	0
T36	583	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T147	0	1	0	0
T151	422	0	0	0
T159	0	1	0	0
T160	0	1	0	0