Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T11,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T33,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T11,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T33,T39
0	1	Covered	T11,T33,T159
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T33,T39
1	-	Covered	T11,T33,T159

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T33
DetectSt	168	Covered	T11,T33,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T33,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T33,T39
DebounceSt->IdleSt	163	Covered	T7,T150,T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T33,T39
IdleSt->DebounceSt	148	Covered	T7,T11,T33
StableSt->IdleSt	206	Covered	T11,T33,T159

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T11,T33
0	1	Covered	T7,T11,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T33,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T33,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T150
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T33,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T33,T159
StableSt	-	-	-	-	-	-	0	Covered	T11,T33,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	104	0	0
CntIncr_A	9094833	60177	0	0
CntNoWrap_A	9094833	8427065	0	0
DetectStDropOut_A	9094833	0	0	0
DetectedOut_A	9094833	6960	0	0
DetectedPulseOut_A	9094833	50	0	0
DisabledIdleSt_A	9094833	7995221	0	0
DisabledNoDetection_A	9094833	7997550	0	0
EnterDebounceSt_A	9094833	54	0	0
EnterDetectSt_A	9094833	50	0	0
EnterStableSt_A	9094833	50	0	0
PulseIsPulse_A	9094833	50	0	0
StayInStableSt	9094833	6887	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	104	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	4	0	0
T39	0	2	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T98	0	2	0	0
T147	0	2	0	0
T148	0	2	0	0
T150	0	2	0	0
T159	0	4	0	0
T172	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	60177	0	0
T7	715	55	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	11	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	82	0	0
T39	0	89	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T98	0	41	0	0
T147	0	15	0	0
T148	0	37	0	0
T150	0	184	0	0
T159	0	82	0	0
T172	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427065	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6960	0	0
T11	8504	86	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	33	0	0
T36	583	0	0	0
T39	0	280	0	0
T42	664	0	0	0
T55	0	15	0	0
T56	567	0	0	0
T62	493	0	0	0
T78	0	40	0	0
T98	0	118	0	0
T136	402	0	0	0
T147	0	45	0	0
T148	0	43	0	0
T151	422	0	0	0
T159	0	82	0	0
T172	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	50	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T39	0	1	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T78	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	422	0	0	0
T159	0	2	0	0
T172	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7995221	0	0
T1	703	302	0	0
T2	107379	4	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7997550	0	0
T1	703	303	0	0
T2	107379	4	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	54	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	2	0	0
T39	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T98	0	1	0	0
T147	0	1	0	0
T148	0	1	0	0
T150	0	2	0	0
T159	0	2	0	0
T172	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	50	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T39	0	1	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T78	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	422	0	0	0
T159	0	2	0	0
T172	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	50	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T39	0	1	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T78	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	422	0	0	0
T159	0	2	0	0
T172	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	50	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T39	0	1	0	0
T42	664	0	0	0
T55	0	1	0	0
T56	567	0	0	0
T62	493	0	0	0
T78	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T147	0	1	0	0
T148	0	1	0	0
T151	422	0	0	0
T159	0	2	0	0
T172	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6887	0	0
T11	8504	85	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	31	0	0
T36	583	0	0	0
T39	0	278	0	0
T42	664	0	0	0
T55	0	14	0	0
T56	567	0	0	0
T62	493	0	0	0
T78	0	39	0	0
T98	0	116	0	0
T136	402	0	0	0
T147	0	43	0	0
T148	0	42	0	0
T151	422	0	0	0
T159	0	79	0	0
T172	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	26	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T78	0	1	0	0
T136	402	0	0	0
T138	0	2	0	0
T148	0	1	0	0
T151	422	0	0	0
T154	0	1	0	0
T159	0	1	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T36
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T11,T36
0	1	Covered	T78,T155,T176
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T11,T36
0	1	Covered	T11,T36,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T11,T36
1	-	Covered	T11,T36,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T11,T36
DetectSt	168	Covered	T2,T11,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T11,T36
DebounceSt->IdleSt	163	Covered	T149,T158,T177
DetectSt->IdleSt	186	Covered	T78,T155,T176
DetectSt->StableSt	191	Covered	T2,T11,T36
IdleSt->DebounceSt	148	Covered	T2,T11,T36
StableSt->IdleSt	206	Covered	T11,T36,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T11,T36
0	1	Covered	T2,T11,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T11,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T149,T158,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T11,T36
DetectSt	-	-	-	-	1	-	-	Covered	T78,T155,T176
DetectSt	-	-	-	-	0	1	-	Covered	T2,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T36,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	156	0	0
CntIncr_A	9094833	241503	0	0
CntNoWrap_A	9094833	8427013	0	0
DetectStDropOut_A	9094833	4	0	0
DetectedOut_A	9094833	152062	0	0
DetectedPulseOut_A	9094833	71	0	0
DisabledIdleSt_A	9094833	7777549	0	0
DisabledNoDetection_A	9094833	7779884	0	0
EnterDebounceSt_A	9094833	81	0	0
EnterDetectSt_A	9094833	75	0	0
EnterStableSt_A	9094833	71	0	0
PulseIsPulse_A	9094833	71	0	0
StayInStableSt	9094833	151964	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	3087	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	43	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	156	0	0
T2	107379	2	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	6	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	6	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	4	0	0
T161	0	4	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	241503	0	0
T2	107379	61443	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	108	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	123	0	0
T34	0	17	0	0
T35	0	38	0	0
T36	0	43	0	0
T37	0	14	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	82	0	0
T161	0	161	0	0
T178	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427013	0	0
T1	703	302	0	0
T2	107379	106976	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	4	0	0
T55	8348	0	0	0
T78	781	1	0	0
T155	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T179	505	0	0	0
T180	606	0	0	0
T181	522	0	0	0
T182	509	0	0	0
T183	436	0	0	0
T184	502	0	0	0
T185	32479	0	0	0
T186	684	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	152062	0	0
T2	107379	38	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	225	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	220	0	0
T34	0	71	0	0
T35	0	161	0	0
T36	0	42	0	0
T37	0	62	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	27	0	0
T161	0	229	0	0
T178	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	71	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	3	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	2	0	0
T161	0	2	0	0
T178	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7777549	0	0
T1	703	302	0	0
T2	107379	4	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7779884	0	0
T1	703	303	0	0
T2	107379	4	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	81	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	3	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	2	0	0
T161	0	2	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	75	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	3	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	2	0	0
T161	0	2	0	0
T178	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	71	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	3	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	2	0	0
T161	0	2	0	0
T178	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	71	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	3	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	3	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	2	0	0
T161	0	2	0	0
T178	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	151964	0	0
T2	107379	36	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T11	0	221	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	216	0	0
T34	0	69	0	0
T35	0	159	0	0
T36	0	41	0	0
T37	0	60	0	0
T49	430	0	0	0
T50	425	0	0	0
T159	0	25	0	0
T161	0	225	0	0
T178	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3087	0	0
T1	703	1	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T4	528	6	0	0
T5	1054	0	0	0
T13	2046	8	0	0
T14	2737	20	0	0
T15	522	5	0	0
T16	413	0	0	0
T17	427	3	0	0
T19	0	4	0	0
T25	0	7	0	0
T49	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	43	0	0
T11	8504	2	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	2	0	0
T36	583	1	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T83	0	2	0	0
T136	402	0	0	0
T147	0	1	0	0
T149	0	1	0	0
T151	422	0	0	0
T152	0	1	0	0
T159	0	2	0	0
T173	0	2	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T36,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T36,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T36,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T36,T37
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T36,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T36,T38
0	1	Covered	T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T36,T38
0	1	Covered	T36,T38,T35
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T36,T38
1	-	Covered	T36,T38,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T36,T38
DetectSt	168	Covered	T7,T36,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T36,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T36,T38
DebounceSt->IdleSt	163	Covered	T76
DetectSt->IdleSt	186	Covered	T83
DetectSt->StableSt	191	Covered	T7,T36,T38
IdleSt->DebounceSt	148	Covered	T7,T36,T38
StableSt->IdleSt	206	Covered	T36,T38,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T36,T38
0	1	Covered	T7,T36,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T36,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T36,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T36,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T36,T38
DetectSt	-	-	-	-	1	-	-	Covered	T83
DetectSt	-	-	-	-	0	1	-	Covered	T7,T36,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T38,T35
StableSt	-	-	-	-	-	-	0	Covered	T7,T36,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	119	0	0
CntIncr_A	9094833	68571	0	0
CntNoWrap_A	9094833	8427050	0	0
DetectStDropOut_A	9094833	1	0	0
DetectedOut_A	9094833	6126	0	0
DetectedPulseOut_A	9094833	58	0	0
DisabledIdleSt_A	9094833	8201568	0	0
DisabledNoDetection_A	9094833	8203912	0	0
EnterDebounceSt_A	9094833	60	0	0
EnterDetectSt_A	9094833	59	0	0
EnterStableSt_A	9094833	58	0	0
PulseIsPulse_A	9094833	58	0	0
StayInStableSt	9094833	6040	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	119	0	0
T7	715	2	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	2	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	4	0	0
T146	0	2	0	0
T159	0	4	0	0
T160	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	68571	0	0
T7	715	55	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	38	0	0
T36	0	43	0	0
T38	0	93	0	0
T39	0	89	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	94	0	0
T146	0	18	0	0
T159	0	82	0	0
T160	0	65316	0	0
T188	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427050	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1	0	0
T78	781	0	0	0
T83	650	1	0	0
T179	505	0	0	0
T180	606	0	0	0
T181	522	0	0	0
T189	523	0	0	0
T190	1098	0	0	0
T191	5927	0	0	0
T192	20847	0	0	0
T193	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6126	0	0
T7	715	250	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	81	0	0
T36	0	40	0	0
T38	0	211	0	0
T39	0	281	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	82	0	0
T146	0	39	0	0
T159	0	109	0	0
T160	0	179	0	0
T188	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	58	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	2	0	0
T146	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8201568	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8203912	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	60	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	2	0	0
T146	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	59	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	2	0	0
T146	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	58	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	2	0	0
T146	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	58	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	2	0	0
T146	0	1	0	0
T159	0	2	0	0
T160	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6040	0	0
T7	715	248	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T35	0	80	0	0
T36	0	39	0	0
T38	0	210	0	0
T39	0	279	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	80	0	0
T146	0	38	0	0
T159	0	106	0	0
T160	0	178	0	0
T188	0	74	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	29	0	0
T23	1827	0	0	0
T32	20103	0	0	0
T35	0	1	0	0
T36	583	1	0	0
T38	0	1	0	0
T40	12838	0	0	0
T42	664	0	0	0
T43	31380	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	2	0	0
T83	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T151	422	0	0	0
T159	0	1	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T4,T5,T13
1	1	Covered	T1,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T36
0	1	Covered	T11
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T36
0	1	Covered	T11,T33,T98
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T36
1	-	Covered	T11,T33,T98

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T36
DetectSt	168	Covered	T1,T11,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T36
DebounceSt->IdleSt	163	Covered	T11,T38,T194
DetectSt->IdleSt	186	Covered	T11
DetectSt->StableSt	191	Covered	T1,T11,T36
IdleSt->DebounceSt	148	Covered	T1,T11,T36
StableSt->IdleSt	206	Covered	T11,T33,T98

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T36
0	1	Covered	T1,T11,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T194
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T36
DetectSt	-	-	-	-	1	-	-	Covered	T11
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T33,T98
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	99	0	0
CntIncr_A	9094833	134621	0	0
CntNoWrap_A	9094833	8427070	0	0
DetectStDropOut_A	9094833	1	0	0
DetectedOut_A	9094833	16581	0	0
DetectedPulseOut_A	9094833	47	0	0
DisabledIdleSt_A	9094833	7864035	0	0
DisabledNoDetection_A	9094833	7866360	0	0
EnterDebounceSt_A	9094833	52	0	0
EnterDetectSt_A	9094833	48	0	0
EnterStableSt_A	9094833	47	0	0
PulseIsPulse_A	9094833	47	0	0
StayInStableSt	9094833	16506	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	6594	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	99	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	5	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	2	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T65	0	2	0	0
T98	0	2	0	0
T148	0	2	0	0
T160	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	134621	0	0
T1	703	51	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	183	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	41	0	0
T34	0	17	0	0
T35	0	38	0	0
T36	0	43	0	0
T38	0	62	0	0
T65	0	91	0	0
T148	0	37	0	0
T160	0	65316	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427070	0	0
T1	703	300	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T136	402	0	0	0
T151	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	16581	0	0
T1	703	42	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	40	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	159	0	0
T34	0	38	0	0
T35	0	42	0	0
T36	0	46	0	0
T65	0	46	0	0
T98	0	17	0	0
T148	0	38	0	0
T160	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	47	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	1	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T65	0	1	0	0
T98	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7864035	0	0
T1	703	4	0	0
T2	107379	4	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7866360	0	0
T1	703	4	0	0
T2	107379	4	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	52	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	3	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T38	0	1	0	0
T65	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	48	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	2	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T65	0	1	0	0
T98	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	47	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	1	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T65	0	1	0	0
T98	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	47	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	1	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T65	0	1	0	0
T98	0	1	0	0
T148	0	1	0	0
T160	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	16506	0	0
T1	703	40	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	39	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	158	0	0
T34	0	36	0	0
T35	0	40	0	0
T36	0	44	0	0
T65	0	44	0	0
T98	0	16	0	0
T148	0	36	0	0
T160	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6594	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	7	0	0
T4	528	6	0	0
T5	1054	5	0	0
T13	2046	8	0	0
T14	2737	15	0	0
T15	522	4	0	0
T16	413	0	0	0
T17	427	1	0	0
T18	0	23	0	0
T49	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	18	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	1	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T83	0	2	0	0
T85	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T138	0	1	0	0
T149	0	1	0	0
T151	422	0	0	0
T155	0	2	0	0
T173	0	1	0	0
T176	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T11
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T11
0	1	Covered	T85,T195,T162
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T11
0	1	Covered	T7,T11,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T11
1	-	Covered	T7,T11,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T11
DetectSt	168	Covered	T2,T7,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T11
DebounceSt->IdleSt	163	Covered	T147,T187,T196
DetectSt->IdleSt	186	Covered	T85,T195,T162
DetectSt->StableSt	191	Covered	T2,T7,T11
IdleSt->DebounceSt	148	Covered	T2,T7,T11
StableSt->IdleSt	206	Covered	T7,T11,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T11
0	1	Covered	T2,T7,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T147,T187,T196
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T85,T195,T162
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T33
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	149	0	0
CntIncr_A	9094833	267447	0	0
CntNoWrap_A	9094833	8427020	0	0
DetectStDropOut_A	9094833	3	0	0
DetectedOut_A	9094833	107122	0	0
DetectedPulseOut_A	9094833	68	0	0
DisabledIdleSt_A	9094833	7872740	0	0
DisabledNoDetection_A	9094833	7875073	0	0
EnterDebounceSt_A	9094833	79	0	0
EnterDetectSt_A	9094833	71	0	0
EnterStableSt_A	9094833	68	0	0
PulseIsPulse_A	9094833	68	0	0
StayInStableSt	9094833	107024	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	37	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	149	0	0
T2	107379	2	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	4	0	0
T11	0	2	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	4	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	4	0	0
T75	0	2	0	0
T146	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	267447	0	0
T2	107379	61443	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	110	0	0
T11	0	86	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	82	0	0
T37	0	28	0	0
T38	0	93	0	0
T39	0	89	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	70	0	0
T75	0	46	0	0
T146	0	18	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427020	0	0
T1	703	302	0	0
T2	107379	106976	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3	0	0
T85	850	1	0	0
T162	0	1	0	0
T195	0	1	0	0
T197	7316	0	0	0
T198	1461	0	0	0
T199	422	0	0	0
T200	506	0	0	0
T201	423	0	0	0
T202	414	0	0	0
T203	682	0	0	0
T204	837	0	0	0
T205	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	107122	0	0
T2	107379	45527	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	92	0	0
T11	0	197	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	251	0	0
T37	0	61	0	0
T38	0	78	0	0
T39	0	209	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	82	0	0
T75	0	86	0	0
T146	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	68	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	2	0	0
T11	0	1	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	2	0	0
T75	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7872740	0	0
T1	703	302	0	0
T2	107379	4	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7875073	0	0
T1	703	303	0	0
T2	107379	4	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	79	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	2	0	0
T11	0	1	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	2	0	0
T75	0	1	0	0
T146	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	71	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	2	0	0
T11	0	1	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	2	0	0
T75	0	1	0	0
T146	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	68	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	2	0	0
T11	0	1	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	2	0	0
T75	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	68	0	0
T2	107379	1	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	2	0	0
T11	0	1	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	2	0	0
T75	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	107024	0	0
T2	107379	45525	0	0
T3	823731	0	0	0
T6	2827	0	0	0
T7	0	89	0	0
T11	0	196	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T25	495	0	0	0
T33	0	248	0	0
T37	0	59	0	0
T38	0	77	0	0
T39	0	208	0	0
T49	430	0	0	0
T50	425	0	0	0
T66	0	79	0	0
T75	0	84	0	0
T146	0	85	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	37	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T66	0	1	0	0
T72	0	1	0	0
T146	0	1	0	0
T159	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T11,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T11,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T11,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T11
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T11,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T33
0	1	Covered	T11,T33,T149
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T33
1	-	Covered	T11,T33,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T11,T33
DetectSt	168	Covered	T1,T11,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T11,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T33
DebounceSt->IdleSt	163	Covered	T157,T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T11,T33
IdleSt->DebounceSt	148	Covered	T1,T11,T33
StableSt->IdleSt	206	Covered	T11,T33,T146

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T11,T33
0	1	Covered	T1,T11,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T11,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T157
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T11,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T33,T149
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	101	0	0
CntIncr_A	9094833	117383	0	0
CntNoWrap_A	9094833	8427068	0	0
DetectStDropOut_A	9094833	0	0	0
DetectedOut_A	9094833	38188	0	0
DetectedPulseOut_A	9094833	50	0	0
DisabledIdleSt_A	9094833	7646057	0	0
DisabledNoDetection_A	9094833	7648390	0	0
EnterDebounceSt_A	9094833	52	0	0
EnterDetectSt_A	9094833	50	0	0
EnterStableSt_A	9094833	49	0	0
PulseIsPulse_A	9094833	49	0	0
StayInStableSt	9094833	38114	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	6196	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	101	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	4	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	2	0	0
T55	0	2	0	0
T98	0	2	0	0
T122	0	2	0	0
T146	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	117383	0	0
T1	703	51	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	97	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	41	0	0
T55	0	32	0	0
T98	0	41	0	0
T122	0	70	0	0
T146	0	18	0	0
T149	0	72	0	0
T150	0	92	0	0
T188	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427068	0	0
T1	703	300	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	38188	0	0
T1	703	41	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	352	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	33	0	0
T55	0	15	0	0
T98	0	60	0	0
T122	0	38	0	0
T146	0	37	0	0
T149	0	152	0	0
T150	0	43	0	0
T188	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	50	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	2	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T55	0	1	0	0
T98	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7646057	0	0
T1	703	4	0	0
T2	107379	4	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7648390	0	0
T1	703	4	0	0
T2	107379	4	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	52	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	2	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T55	0	1	0	0
T98	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	50	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	2	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T55	0	1	0	0
T98	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	49	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	2	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T55	0	1	0	0
T98	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	49	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	2	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T55	0	1	0	0
T98	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	38114	0	0
T1	703	39	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T11	0	349	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	32	0	0
T55	0	14	0	0
T98	0	58	0	0
T122	0	36	0	0
T146	0	35	0	0
T149	0	151	0	0
T150	0	42	0	0
T188	0	42	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6196	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T4	528	6	0	0
T5	1054	0	0	0
T6	0	16	0	0
T13	2046	11	0	0
T14	2737	14	0	0
T15	522	5	0	0
T16	413	0	0	0
T17	427	5	0	0
T18	0	28	0	0
T25	0	9	0	0
T49	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	24	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T33	0	1	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T136	402	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	422	0	0	0
T155	0	1	0	0
T156	0	1	0	0
T174	0	1	0	0
T187	0	1	0	0
T206	0	1	0	0
T207	0	2	0	0