Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.61	97.83	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T11,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T36
1	0	Covered	T4,T1,T13
1	1	Covered	T7,T11,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T36
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T36
0	1	Covered	T7,T65,T37
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T36
1	-	Covered	T7,T65,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T36
DetectSt	168	Covered	T7,T11,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T11,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T36
DebounceSt->IdleSt	163	Covered	T11,T158,T208
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T11,T36
IdleSt->DebounceSt	148	Covered	T7,T11,T36
StableSt->IdleSt	206	Covered	T7,T11,T65

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T11,T36
0	1	Covered	T7,T11,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T158,T208
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T65,T37
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	118	0	0
CntIncr_A	9094833	35259	0	0
CntNoWrap_A	9094833	8427051	0	0
DetectStDropOut_A	9094833	0	0	0
DetectedOut_A	9094833	4033	0	0
DetectedPulseOut_A	9094833	56	0	0
DisabledIdleSt_A	9094833	8333609	0	0
DisabledNoDetection_A	9094833	8335956	0	0
EnterDebounceSt_A	9094833	62	0	0
EnterDetectSt_A	9094833	56	0	0
EnterStableSt_A	9094833	56	0	0
PulseIsPulse_A	9094833	56	0	0
StayInStableSt	9094833	3955	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	118	0	0
T7	715	2	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	3	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T149	0	4	0	0
T209	0	4	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	35259	0	0
T7	715	55	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	22	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	43	0	0
T37	0	14	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	91	0	0
T146	0	18	0	0
T147	0	99	0	0
T149	0	144	0	0
T209	0	70	0	0
T210	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427051	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	4033	0	0
T7	715	52	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	60	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	130	0	0
T37	0	55	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	1	0	0
T146	0	40	0	0
T147	0	60	0	0
T149	0	190	0	0
T209	0	80	0	0
T210	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	56	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	2	0	0
T209	0	2	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8333609	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8335956	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	62	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	2	0	0
T209	0	2	0	0
T210	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	56	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	2	0	0
T209	0	2	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	56	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	2	0	0
T209	0	2	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	56	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	2	0	0
T209	0	2	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3955	0	0
T7	715	51	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	58	0	0
T26	493	0	0	0
T27	628	0	0	0
T36	0	128	0	0
T37	0	54	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T83	0	80	0	0
T146	0	39	0	0
T147	0	59	0	0
T149	0	188	0	0
T209	0	77	0	0
T210	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	33	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T26	493	0	0	0
T27	628	0	0	0
T37	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T65	0	1	0	0
T83	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T149	0	2	0	0
T153	0	1	0	0
T187	0	3	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T33,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T33,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T33,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T36,T33
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T33,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T33,T35
0	1	Covered	T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T33,T35
0	1	Covered	T35,T39,T209
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T33,T35
1	-	Covered	T35,T39,T209

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T33,T35
DetectSt	168	Covered	T1,T33,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T33,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T33,T35
DebounceSt->IdleSt	163	Covered	T211,T76,T212
DetectSt->IdleSt	186	Covered	T187
DetectSt->StableSt	191	Covered	T1,T33,T35
IdleSt->DebounceSt	148	Covered	T1,T33,T35
StableSt->IdleSt	206	Covered	T35,T146,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T33,T35
0	1	Covered	T1,T33,T35
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T33,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T33,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T33,T35
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T33,T35
DetectSt	-	-	-	-	1	-	-	Covered	T187
DetectSt	-	-	-	-	0	1	-	Covered	T1,T33,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T39,T209
StableSt	-	-	-	-	-	-	0	Covered	T1,T33,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	101	0	0
CntIncr_A	9094833	73190	0	0
CntNoWrap_A	9094833	8427068	0	0
DetectStDropOut_A	9094833	1	0	0
DetectedOut_A	9094833	64669	0	0
DetectedPulseOut_A	9094833	49	0	0
DisabledIdleSt_A	9094833	8090016	0	0
DisabledNoDetection_A	9094833	8092349	0	0
EnterDebounceSt_A	9094833	53	0	0
EnterDetectSt_A	9094833	50	0	0
EnterStableSt_A	9094833	49	0	0
PulseIsPulse_A	9094833	49	0	0
StayInStableSt	9094833	64594	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	6120	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	101	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	2	0	0
T35	0	2	0	0
T39	0	2	0	0
T122	0	2	0	0
T146	0	2	0	0
T147	0	2	0	0
T148	0	4	0	0
T172	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	73190	0	0
T1	703	51	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	41	0	0
T35	0	38	0	0
T39	0	89	0	0
T122	0	70	0	0
T146	0	18	0	0
T147	0	99	0	0
T148	0	74	0	0
T172	0	45	0	0
T209	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427068	0	0
T1	703	300	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1	0	0
T153	1060	0	0	0
T187	132226	1	0	0
T213	507	0	0	0
T214	425	0	0	0
T215	524	0	0	0
T216	295471	0	0	0
T217	1211	0	0	0
T218	534	0	0	0
T219	405	0	0	0
T220	1171	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	64669	0	0
T1	703	94	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	156	0	0
T35	0	81	0	0
T39	0	149	0	0
T122	0	54	0	0
T146	0	59	0	0
T147	0	283	0	0
T148	0	18	0	0
T172	0	23	0	0
T209	0	86	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	49	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T172	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8090016	0	0
T1	703	4	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8092349	0	0
T1	703	4	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	53	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T172	0	1	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	50	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T172	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	49	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T172	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	49	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	1	0	0
T35	0	1	0	0
T39	0	1	0	0
T122	0	1	0	0
T146	0	1	0	0
T147	0	1	0	0
T148	0	2	0	0
T172	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	64594	0	0
T1	703	92	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T33	0	154	0	0
T35	0	80	0	0
T39	0	148	0	0
T122	0	53	0	0
T146	0	57	0	0
T147	0	281	0	0
T148	0	16	0	0
T172	0	22	0	0
T209	0	85	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6120	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T4	528	5	0	0
T5	1054	0	0	0
T6	0	13	0	0
T13	2046	10	0	0
T14	2737	14	0	0
T15	522	5	0	0
T16	413	0	0	0
T17	427	3	0	0
T18	0	31	0	0
T25	0	9	0	0
T49	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	22	0	0
T35	677	1	0	0
T39	0	1	0	0
T64	494	0	0	0
T122	0	1	0	0
T148	0	2	0	0
T150	0	1	0	0
T152	0	1	0	0
T158	0	1	0	0
T172	0	1	0	0
T187	0	2	0	0
T209	0	1	0	0
T221	493	0	0	0
T222	405	0	0	0
T223	822	0	0	0
T224	423	0	0	0
T225	425	0	0	0
T226	407	0	0	0
T227	406	0	0	0
T228	519	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T4,T13,T14
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T11
1	-	Covered	T1,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T11
DetectSt	168	Covered	T1,T7,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T11
DebounceSt->IdleSt	163	Covered	T229,T76,T230
DetectSt->IdleSt	186	Covered	T83
DetectSt->StableSt	191	Covered	T1,T7,T11
IdleSt->DebounceSt	148	Covered	T1,T7,T11
StableSt->IdleSt	206	Covered	T1,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T229,T230
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T83
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	127	0	0
CntIncr_A	9094833	68843	0	0
CntNoWrap_A	9094833	8427042	0	0
DetectStDropOut_A	9094833	1	0	0
DetectedOut_A	9094833	4811	0	0
DetectedPulseOut_A	9094833	61	0	0
DisabledIdleSt_A	9094833	8279480	0	0
DisabledNoDetection_A	9094833	8281824	0	0
EnterDebounceSt_A	9094833	65	0	0
EnterDetectSt_A	9094833	62	0	0
EnterStableSt_A	9094833	61	0	0
PulseIsPulse_A	9094833	61	0	0
StayInStableSt	9094833	4730	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	40	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	127	0	0
T1	703	4	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	4	0	0
T11	0	6	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	2	0	0
T72	0	4	0	0
T122	0	2	0	0
T148	0	4	0	0
T159	0	2	0	0
T160	0	2	0	0
T161	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	68843	0	0
T1	703	102	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	110	0	0
T11	0	108	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	17	0	0
T72	0	94	0	0
T122	0	70	0	0
T148	0	74	0	0
T159	0	41	0	0
T160	0	65316	0	0
T161	0	161	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427042	0	0
T1	703	298	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1	0	0
T78	781	0	0	0
T83	650	1	0	0
T179	505	0	0	0
T180	606	0	0	0
T181	522	0	0	0
T189	523	0	0	0
T190	1098	0	0	0
T191	5927	0	0	0
T192	20847	0	0	0
T193	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	4811	0	0
T1	703	44	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	187	0	0
T11	0	227	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	15	0	0
T72	0	163	0	0
T122	0	117	0	0
T148	0	126	0	0
T159	0	178	0	0
T160	0	179	0	0
T161	0	308	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	61	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	2	0	0
T11	0	3	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	1	0	0
T72	0	2	0	0
T122	0	1	0	0
T148	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8279480	0	0
T1	703	4	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8281824	0	0
T1	703	4	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	65	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	2	0	0
T11	0	3	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	1	0	0
T72	0	2	0	0
T122	0	1	0	0
T148	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	62	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	2	0	0
T11	0	3	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	1	0	0
T72	0	2	0	0
T122	0	1	0	0
T148	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	61	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	2	0	0
T11	0	3	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	1	0	0
T72	0	2	0	0
T122	0	1	0	0
T148	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	61	0	0
T1	703	2	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	2	0	0
T11	0	3	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	1	0	0
T72	0	2	0	0
T122	0	1	0	0
T148	0	2	0	0
T159	0	1	0	0
T160	0	1	0	0
T161	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	4730	0	0
T1	703	41	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	184	0	0
T11	0	223	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	14	0	0
T72	0	161	0	0
T122	0	116	0	0
T148	0	124	0	0
T159	0	176	0	0
T160	0	178	0	0
T161	0	304	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	40	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T7	0	1	0	0
T11	0	2	0	0
T13	2046	0	0	0
T14	2737	0	0	0
T15	522	0	0	0
T16	413	0	0	0
T17	427	0	0	0
T18	5116	0	0	0
T19	521	0	0	0
T34	0	1	0	0
T72	0	2	0	0
T98	0	1	0	0
T122	0	1	0	0
T148	0	2	0	0
T149	0	1	0	0
T160	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T11,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T36
1	0	Covered	T4,T1,T13
1	1	Covered	T7,T11,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T34,T35
0	1	Covered	T85
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T34,T35
0	1	Covered	T35,T72,T149
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T34,T35
1	-	Covered	T35,T72,T149

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T34
DetectSt	168	Covered	T11,T34,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T34,T35
DebounceSt->IdleSt	163	Covered	T7,T173,T76
DetectSt->IdleSt	186	Covered	T85
DetectSt->StableSt	191	Covered	T11,T34,T35
IdleSt->DebounceSt	148	Covered	T7,T11,T34
StableSt->IdleSt	206	Covered	T11,T35,T146

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T11,T34
0	1	Covered	T7,T11,T34
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T11,T34,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T7,T173
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T34
DetectSt	-	-	-	-	1	-	-	Covered	T85
DetectSt	-	-	-	-	0	1	-	Covered	T11,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T72,T149
StableSt	-	-	-	-	-	-	0	Covered	T11,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	83	0	0
CntIncr_A	9094833	121208	0	0
CntNoWrap_A	9094833	8427086	0	0
DetectStDropOut_A	9094833	1	0	0
DetectedOut_A	9094833	22207	0	0
DetectedPulseOut_A	9094833	39	0	0
DisabledIdleSt_A	9094833	7883595	0	0
DisabledNoDetection_A	9094833	7885930	0	0
EnterDebounceSt_A	9094833	44	0	0
EnterDetectSt_A	9094833	40	0	0
EnterStableSt_A	9094833	39	0	0
PulseIsPulse_A	9094833	39	0	0
StayInStableSt	9094833	22143	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	6169	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	83	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	4	0	0
T98	0	2	0	0
T146	0	2	0	0
T149	0	2	0	0
T150	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	121208	0	0
T7	715	55	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	86	0	0
T26	493	0	0	0
T27	628	0	0	0
T34	0	17	0	0
T35	0	38	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	94	0	0
T98	0	41	0	0
T146	0	18	0	0
T149	0	72	0	0
T150	0	92	0	0
T209	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427086	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1	0	0
T85	850	1	0	0
T197	7316	0	0	0
T198	1461	0	0	0
T199	422	0	0	0
T200	506	0	0	0
T201	423	0	0	0
T202	414	0	0	0
T203	682	0	0	0
T204	837	0	0	0
T205	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	22207	0	0
T11	8504	179	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T34	0	39	0	0
T35	0	81	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	85	0	0
T83	0	126	0	0
T98	0	60	0	0
T136	402	0	0	0
T146	0	59	0	0
T149	0	114	0	0
T150	0	40	0	0
T151	422	0	0	0
T209	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	39	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	2	0	0
T83	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	422	0	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7883595	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7885930	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	44	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T72	0	2	0	0
T98	0	1	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	40	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	2	0	0
T83	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	422	0	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	39	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	2	0	0
T83	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	422	0	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	39	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	2	0	0
T83	0	1	0	0
T98	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	422	0	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	22143	0	0
T11	8504	177	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T34	0	37	0	0
T35	0	80	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	82	0	0
T83	0	124	0	0
T98	0	58	0	0
T136	402	0	0	0
T146	0	57	0	0
T149	0	113	0	0
T150	0	38	0	0
T151	422	0	0	0
T209	0	88	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6169	0	0
T1	703	1	0	0
T2	107379	0	0	0
T3	823731	0	0	0
T4	528	6	0	0
T5	1054	0	0	0
T6	0	14	0	0
T13	2046	13	0	0
T14	2737	14	0	0
T15	522	6	0	0
T16	413	0	0	0
T17	427	3	0	0
T18	0	28	0	0
T25	0	5	0	0
T49	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	13	0	0
T35	677	1	0	0
T64	494	0	0	0
T72	0	1	0	0
T149	0	1	0	0
T152	0	2	0	0
T174	0	1	0	0
T176	0	2	0	0
T177	0	1	0	0
T208	0	1	0	0
T221	493	0	0	0
T222	405	0	0	0
T223	822	0	0	0
T224	423	0	0	0
T225	425	0	0	0
T226	407	0	0	0
T227	406	0	0	0
T228	519	0	0	0
T231	0	1	0	0
T232	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T11,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T65
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T11,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T33
0	1	Covered	T84,T156,T233
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T33
0	1	Covered	T7,T11,T33
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T33
1	-	Covered	T7,T11,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T33
DetectSt	168	Covered	T7,T11,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T11,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T33
DebounceSt->IdleSt	163	Covered	T11,T122,T76
DetectSt->IdleSt	186	Covered	T84,T156,T233
DetectSt->StableSt	191	Covered	T7,T11,T33
IdleSt->DebounceSt	148	Covered	T7,T11,T33
StableSt->IdleSt	206	Covered	T7,T11,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T11,T33
0	1	Covered	T7,T11,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T122
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T33
DetectSt	-	-	-	-	1	-	-	Covered	T84,T156,T233
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T33
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	120	0	0
CntIncr_A	9094833	65301	0	0
CntNoWrap_A	9094833	8427049	0	0
DetectStDropOut_A	9094833	3	0	0
DetectedOut_A	9094833	29839	0	0
DetectedPulseOut_A	9094833	56	0	0
DisabledIdleSt_A	9094833	8123671	0	0
DisabledNoDetection_A	9094833	8126007	0	0
EnterDebounceSt_A	9094833	63	0	0
EnterDetectSt_A	9094833	59	0	0
EnterStableSt_A	9094833	55	0	0
PulseIsPulse_A	9094833	55	0	0
StayInStableSt	9094833	29759	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	120	0	0
T7	715	2	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	3	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	2	0	0
T38	0	2	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	2	0	0
T122	0	1	0	0
T146	0	4	0	0
T148	0	2	0	0
T172	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	65301	0	0
T7	715	55	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	172	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	41	0	0
T38	0	93	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	46	0	0
T122	0	27	0	0
T146	0	36	0	0
T148	0	37	0	0
T172	0	45	0	0
T188	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427049	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3	0	0
T84	743	1	0	0
T156	0	1	0	0
T233	0	1	0	0
T234	670	0	0	0
T235	170859	0	0	0
T236	622	0	0	0
T237	137430	0	0	0
T238	523	0	0	0
T239	752	0	0	0
T240	17315	0	0	0
T241	505	0	0	0
T242	527	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	29839	0	0
T7	715	48	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	199	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	9	0	0
T38	0	197	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	40	0	0
T146	0	40	0	0
T148	0	137	0	0
T172	0	40	0	0
T178	0	47	0	0
T188	0	76	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	56	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8123671	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8126007	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	63	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	1	0	0
T122	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T172	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	59	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	55	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	55	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	1	0	0
T146	0	2	0	0
T148	0	1	0	0
T172	0	1	0	0
T178	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	29759	0	0
T7	715	47	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	198	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	8	0	0
T38	0	196	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T75	0	38	0	0
T146	0	37	0	0
T148	0	136	0	0
T172	0	39	0	0
T178	0	45	0	0
T188	0	74	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	30	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	1	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T38	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T78	0	1	0	0
T83	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T172	0	1	0	0
T187	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T11,T33

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T11,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T33
1	0	Covered	T4,T5,T1
1	1	Covered	T7,T11,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T33
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T33
0	1	Covered	T11,T146,T72
1	0	Covered	T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T33
1	-	Covered	T11,T146,T72

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T33
DetectSt	168	Covered	T7,T11,T33
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T11,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T33
DebounceSt->IdleSt	163	Covered	T76
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T11,T33
IdleSt->DebounceSt	148	Covered	T7,T11,T33
StableSt->IdleSt	206	Covered	T11,T146,T72

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T11,T33
0	1	Covered	T7,T11,T33
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T33
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T76
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T33
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T33
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T33
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T146,T72
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	71	0	0
CntIncr_A	9094833	58617	0	0
CntNoWrap_A	9094833	8427098	0	0
DetectStDropOut_A	9094833	0	0	0
DetectedOut_A	9094833	120237	0	0
DetectedPulseOut_A	9094833	35	0	0
DisabledIdleSt_A	9094833	7873492	0	0
DisabledNoDetection_A	9094833	7875837	0	0
EnterDebounceSt_A	9094833	36	0	0
EnterDetectSt_A	9094833	35	0	0
EnterStableSt_A	9094833	35	0	0
PulseIsPulse_A	9094833	35	0	0
StayInStableSt	9094833	120182	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9094833	6927	0	0
gen_low_level_sva.LowLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	71	0	0
T7	715	2	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	4	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	2	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	2	0	0
T72	0	2	0	0
T146	0	2	0	0
T148	0	2	0	0
T152	0	2	0	0
T172	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	58617	0	0
T7	715	55	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	22	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	41	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	32	0	0
T72	0	47	0	0
T146	0	18	0	0
T148	0	37	0	0
T152	0	38	0	0
T172	0	45	0	0
T209	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8427098	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	120237	0	0
T7	715	38	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	123	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	369	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	14	0	0
T72	0	106	0	0
T146	0	63	0	0
T148	0	39	0	0
T152	0	170	0	0
T172	0	109	0	0
T209	0	169	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	35	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	1	0	0
T72	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T152	0	1	0	0
T172	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7873492	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7875837	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	36	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	1	0	0
T72	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T152	0	1	0	0
T172	0	1	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	35	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	1	0	0
T72	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T152	0	1	0	0
T172	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	35	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	1	0	0
T72	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T152	0	1	0	0
T172	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	35	0	0
T7	715	1	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	2	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	1	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	1	0	0
T72	0	1	0	0
T146	0	1	0	0
T148	0	1	0	0
T152	0	1	0	0
T172	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	120182	0	0
T7	715	36	0	0
T8	22334	0	0	0
T9	26454	0	0	0
T10	3835	0	0	0
T11	0	120	0	0
T26	493	0	0	0
T27	628	0	0	0
T33	0	367	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T55	0	13	0	0
T72	0	105	0	0
T146	0	62	0	0
T148	0	37	0	0
T152	0	169	0	0
T172	0	107	0	0
T209	0	167	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	6927	0	0
T1	703	1	0	0
T2	107379	1	0	0
T3	823731	7	0	0
T4	528	5	0	0
T5	1054	5	0	0
T13	2046	11	0	0
T14	2737	14	0	0
T15	522	3	0	0
T16	413	0	0	0
T17	427	2	0	0
T18	0	17	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	14	0	0
T11	8504	1	0	0
T12	22990	0	0	0
T23	1827	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T42	664	0	0	0
T56	567	0	0	0
T62	493	0	0	0
T72	0	1	0	0
T136	402	0	0	0
T146	0	1	0	0
T151	422	0	0	0
T152	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T176	0	1	0	0
T177	0	2	0	0
T187	0	2	0	0