Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T8,T9
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T8,T9
1	0	Covered	T8,T9,T12
1	1	Covered	T18,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T8,T9
0	1	Covered	T18,T8,T67
1	0	Covered	T8,T94,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T40
0	1	Covered	T9,T12,T40
1	0	Covered	T79,T55

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T40
1	-	Covered	T9,T12,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T8,T9
DetectSt	168	Covered	T18,T8,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T12,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T8,T9
DebounceSt->IdleSt	163	Covered	T55,T243,T76
DetectSt->IdleSt	186	Covered	T18,T8,T67
DetectSt->StableSt	191	Covered	T9,T12,T40
IdleSt->DebounceSt	148	Covered	T18,T8,T9
StableSt->IdleSt	206	Covered	T9,T12,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T8,T9
0	1	Covered	T18,T8,T9
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T8,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T8,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T243,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T8,T67
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T40
DetectSt	-	-	-	-	0	0	-	Covered	T18,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T40
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T40
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	2865	0	0
CntIncr_A	9094833	103473	0	0
CntNoWrap_A	9094833	8424304	0	0
DetectStDropOut_A	9094833	346	0	0
DetectedOut_A	9094833	81499	0	0
DetectedPulseOut_A	9094833	854	0	0
DisabledIdleSt_A	9094833	7951437	0	0
DisabledNoDetection_A	9094833	7953603	0	0
EnterDebounceSt_A	9094833	1438	0	0
EnterDetectSt_A	9094833	1428	0	0
EnterStableSt_A	9094833	854	0	0
PulseIsPulse_A	9094833	854	0	0
StayInStableSt	9094833	80509	0	0
gen_high_event_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	685	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	2865	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	60	0	0
T9	0	12	0	0
T12	0	34	0	0
T18	5116	20	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	4	0	0
T41	0	6	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	26	0	0
T68	0	8	0	0
T69	0	32	0	0
T70	0	22	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	103473	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	2082	0	0
T9	0	396	0	0
T12	0	1683	0	0
T18	5116	492	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	122	0	0
T41	0	210	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	695	0	0
T68	0	340	0	0
T69	0	992	0	0
T70	0	858	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8424304	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	346	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	17	0	0
T18	5116	10	0	0
T19	521	0	0	0
T25	495	0	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T55	0	1	0	0
T67	0	13	0	0
T94	0	7	0	0
T96	0	12	0	0
T97	0	2	0	0
T99	0	15	0	0
T100	0	6	0	0
T244	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	81499	0	0
T9	26454	849	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	2210	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T40	0	62	0	0
T41	0	411	0	0
T42	664	0	0	0
T68	0	104	0	0
T69	0	1595	0	0
T70	0	1814	0	0
T79	0	567	0	0
T127	0	2358	0	0
T144	0	34	0	0
T151	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	854	0	0
T9	26454	6	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	17	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	664	0	0	0
T68	0	4	0	0
T69	0	16	0	0
T70	0	11	0	0
T79	0	31	0	0
T127	0	16	0	0
T144	0	1	0	0
T151	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7951437	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7953603	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1438	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	30	0	0
T9	0	6	0	0
T12	0	17	0	0
T18	5116	10	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	13	0	0
T68	0	4	0	0
T69	0	16	0	0
T70	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1428	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	30	0	0
T9	0	6	0	0
T12	0	17	0	0
T18	5116	10	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	13	0	0
T68	0	4	0	0
T69	0	16	0	0
T70	0	11	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	854	0	0
T9	26454	6	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	17	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	664	0	0	0
T68	0	4	0	0
T69	0	16	0	0
T70	0	11	0	0
T79	0	31	0	0
T127	0	16	0	0
T144	0	1	0	0
T151	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	854	0	0
T9	26454	6	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	17	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T40	0	2	0	0
T41	0	3	0	0
T42	664	0	0	0
T68	0	4	0	0
T69	0	16	0	0
T70	0	11	0	0
T79	0	31	0	0
T127	0	16	0	0
T144	0	1	0	0
T151	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	80509	0	0
T9	26454	839	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	2188	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T40	0	60	0	0
T41	0	407	0	0
T42	664	0	0	0
T68	0	100	0	0
T69	0	1576	0	0
T70	0	1803	0	0
T79	0	536	0	0
T127	0	2341	0	0
T144	0	32	0	0
T151	422	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	685	0	0
T9	26454	2	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	12	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	664	0	0	0
T68	0	4	0	0
T69	0	13	0	0
T70	0	11	0	0
T77	0	15	0	0
T127	0	15	0	0
T151	422	0	0	0
T245	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T6,T8
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T6,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T9,T10
1	0	Covered	T13,T14,T18
1	1	Covered	T6,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Covered	T93,T95,T98
1	0	Covered	T55,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T9,T10
0	1	Covered	T6,T9,T10
1	0	Covered	T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T9,T10
1	-	Covered	T6,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T9,T10
DetectSt	168	Covered	T6,T9,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T9,T10
DebounceSt->IdleSt	163	Covered	T11,T31,T24
DetectSt->IdleSt	186	Covered	T93,T95,T98
DetectSt->StableSt	191	Covered	T6,T9,T10
IdleSt->DebounceSt	148	Covered	T6,T9,T10
StableSt->IdleSt	206	Covered	T6,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T9,T10
0	1	Covered	T6,T9,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T9,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T31,T24
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T93,T95,T98
DetectSt	-	-	-	-	0	1	-	Covered	T6,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T6,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T6,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T6,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	837	0	0
CntIncr_A	9094833	41003	0	0
CntNoWrap_A	9094833	8426332	0	0
DetectStDropOut_A	9094833	26	0	0
DetectedOut_A	9094833	16115	0	0
DetectedPulseOut_A	9094833	349	0	0
DisabledIdleSt_A	9094833	8080430	0	0
DisabledNoDetection_A	9094833	8082083	0	0
EnterDebounceSt_A	9094833	461	0	0
EnterDetectSt_A	9094833	379	0	0
EnterStableSt_A	9094833	349	0	0
PulseIsPulse_A	9094833	349	0	0
StayInStableSt	9094833	15736	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	316	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	837	0	0
T6	2827	4	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	8	0	0
T10	0	2	0	0
T11	0	2	0	0
T12	0	10	0	0
T24	0	4	0	0
T27	628	0	0	0
T31	0	20	0	0
T32	0	10	0	0
T43	0	6	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	41003	0	0
T6	2827	50	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	240	0	0
T10	0	25	0	0
T11	0	40	0	0
T12	0	425	0	0
T24	0	214	0	0
T27	628	0	0	0
T31	0	2034	0	0
T32	0	600	0	0
T43	0	264	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426332	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	26	0	0
T39	949	0	0	0
T93	14737	2	0	0
T95	0	4	0	0
T98	0	3	0	0
T101	0	3	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	3	0	0
T108	0	7	0	0
T114	743	0	0	0
T115	526	0	0	0
T116	497	0	0	0
T117	502	0	0	0
T118	729	0	0	0
T119	96750	0	0	0
T120	4416	0	0	0
T121	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	16115	0	0
T6	2827	6	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	234	0	0
T10	0	3	0	0
T12	0	175	0	0
T24	0	73	0	0
T27	628	0	0	0
T31	0	43	0	0
T32	0	102	0	0
T41	0	73	0	0
T43	0	12	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	349	0	0
T6	2827	2	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	4	0	0
T10	0	1	0	0
T12	0	5	0	0
T24	0	1	0	0
T27	628	0	0	0
T31	0	9	0	0
T32	0	5	0	0
T41	0	1	0	0
T43	0	3	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8080430	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8082083	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	461	0	0
T6	2827	2	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	4	0	0
T10	0	1	0	0
T11	0	2	0	0
T12	0	5	0	0
T24	0	3	0	0
T27	628	0	0	0
T31	0	11	0	0
T32	0	5	0	0
T43	0	3	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	379	0	0
T6	2827	2	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	4	0	0
T10	0	1	0	0
T12	0	5	0	0
T24	0	1	0	0
T27	628	0	0	0
T31	0	9	0	0
T32	0	5	0	0
T41	0	1	0	0
T43	0	3	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	349	0	0
T6	2827	2	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	4	0	0
T10	0	1	0	0
T12	0	5	0	0
T24	0	1	0	0
T27	628	0	0	0
T31	0	9	0	0
T32	0	5	0	0
T41	0	1	0	0
T43	0	3	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	349	0	0
T6	2827	2	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	4	0	0
T10	0	1	0	0
T12	0	5	0	0
T24	0	1	0	0
T27	628	0	0	0
T31	0	9	0	0
T32	0	5	0	0
T41	0	1	0	0
T43	0	3	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	15736	0	0
T6	2827	4	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	230	0	0
T10	0	2	0	0
T12	0	170	0	0
T24	0	72	0	0
T27	628	0	0	0
T31	0	34	0	0
T32	0	97	0	0
T41	0	71	0	0
T43	0	9	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T90	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	316	0	0
T6	2827	2	0	0
T7	715	0	0	0
T8	22334	0	0	0
T9	26454	4	0	0
T10	0	1	0	0
T12	0	5	0	0
T24	0	1	0	0
T27	628	0	0	0
T31	0	9	0	0
T32	0	5	0	0
T43	0	3	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T74	0	2	0	0
T90	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T8,T9
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T8,T9
1	0	Covered	T8,T9,T12
1	1	Covered	T18,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T8,T9
0	1	Covered	T18,T67,T69
1	0	Covered	T69,T94,T246

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T12
1	-	Covered	T8,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T8,T9
DetectSt	168	Covered	T18,T8,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T8,T9
DebounceSt->IdleSt	163	Covered	T55,T243,T76
DetectSt->IdleSt	186	Covered	T18,T67,T69
DetectSt->StableSt	191	Covered	T8,T9,T12
IdleSt->DebounceSt	148	Covered	T18,T8,T9
StableSt->IdleSt	206	Covered	T8,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T8,T9
0	1	Covered	T18,T8,T9
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T8,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T8,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T243,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T67,T69
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	0	0	-	Covered	T18,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	3102	0	0
CntIncr_A	9094833	115046	0	0
CntNoWrap_A	9094833	8424067	0	0
DetectStDropOut_A	9094833	439	0	0
DetectedOut_A	9094833	96094	0	0
DetectedPulseOut_A	9094833	879	0	0
DisabledIdleSt_A	9094833	7942760	0	0
DisabledNoDetection_A	9094833	7944919	0	0
EnterDebounceSt_A	9094833	1558	0	0
EnterDetectSt_A	9094833	1545	0	0
EnterStableSt_A	9094833	879	0	0
PulseIsPulse_A	9094833	879	0	0
StayInStableSt	9094833	95072	0	0
gen_high_event_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	736	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	3102	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	18	0	0
T9	0	14	0	0
T12	0	20	0	0
T18	5116	46	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	22	0	0
T41	0	38	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	30	0	0
T68	0	50	0	0
T69	0	54	0	0
T70	0	44	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	115046	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	387	0	0
T9	0	287	0	0
T12	0	620	0	0
T18	5116	1150	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	583	0	0
T41	0	1482	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	805	0	0
T68	0	1825	0	0
T69	0	2044	0	0
T70	0	1188	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8424067	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	439	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	0	0	0
T18	5116	23	0	0
T19	521	0	0	0
T25	495	0	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T55	0	1	0	0
T67	0	15	0	0
T69	0	13	0	0
T94	0	17	0	0
T96	0	11	0	0
T99	0	8	0	0
T246	0	16	0	0
T247	0	11	0	0
T248	0	19	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	96094	0	0
T8	22334	1442	0	0
T9	26454	796	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	2141	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	924	0	0
T41	0	2293	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	2738	0	0
T70	0	3133	0	0
T77	0	4362	0	0
T79	0	2771	0	0
T127	0	2610	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	879	0	0
T8	22334	9	0	0
T9	26454	7	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	10	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	11	0	0
T41	0	19	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	25	0	0
T70	0	22	0	0
T77	0	32	0	0
T79	0	31	0	0
T127	0	16	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7942760	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7944919	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1558	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	9	0	0
T9	0	7	0	0
T12	0	10	0	0
T18	5116	23	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	11	0	0
T41	0	19	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	15	0	0
T68	0	25	0	0
T69	0	27	0	0
T70	0	22	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1545	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	9	0	0
T9	0	7	0	0
T12	0	10	0	0
T18	5116	23	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	11	0	0
T41	0	19	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	15	0	0
T68	0	25	0	0
T69	0	27	0	0
T70	0	22	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	879	0	0
T8	22334	9	0	0
T9	26454	7	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	10	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	11	0	0
T41	0	19	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	25	0	0
T70	0	22	0	0
T77	0	32	0	0
T79	0	31	0	0
T127	0	16	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	879	0	0
T8	22334	9	0	0
T9	26454	7	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	10	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	11	0	0
T41	0	19	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	25	0	0
T70	0	22	0	0
T77	0	32	0	0
T79	0	31	0	0
T127	0	16	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	95072	0	0
T8	22334	1428	0	0
T9	26454	785	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	2126	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	911	0	0
T41	0	2272	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	2712	0	0
T70	0	3109	0	0
T77	0	4330	0	0
T79	0	2731	0	0
T127	0	2591	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	736	0	0
T8	22334	4	0	0
T9	26454	3	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	5	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T40	0	9	0	0
T41	0	17	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T68	0	24	0	0
T70	0	20	0	0
T77	0	32	0	0
T79	0	22	0	0
T127	0	13	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T8,T9
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T8,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T13,T14,T18
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Covered	T43,T75,T147
1	0	Covered	T55,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
1	0	Covered	T55,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T12
1	-	Covered	T8,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T8,T9,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T12
DebounceSt->IdleSt	163	Covered	T43,T24,T70
DetectSt->IdleSt	186	Covered	T43,T75,T147
DetectSt->StableSt	191	Covered	T8,T9,T12
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T8,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T24,T70
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Covered	T43,T75,T147
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	0	0	-	Covered	T8,T9,T12
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	844	0	0
CntIncr_A	9094833	46627	0	0
CntNoWrap_A	9094833	8426325	0	0
DetectStDropOut_A	9094833	38	0	0
DetectedOut_A	9094833	18080	0	0
DetectedPulseOut_A	9094833	356	0	0
DisabledIdleSt_A	9094833	8066115	0	0
DisabledNoDetection_A	9094833	8067818	0	0
EnterDebounceSt_A	9094833	447	0	0
EnterDetectSt_A	9094833	399	0	0
EnterStableSt_A	9094833	356	0	0
PulseIsPulse_A	9094833	356	0	0
StayInStableSt	9094833	17680	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	309	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	844	0	0
T8	22334	8	0	0
T9	26454	8	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	10	0	0
T24	0	10	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	4	0	0
T32	0	6	0	0
T40	0	4	0	0
T41	0	6	0	0
T43	0	9	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T74	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	46627	0	0
T8	22334	244	0	0
T9	26454	300	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	320	0	0
T24	0	682	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	222	0	0
T32	0	267	0	0
T40	0	90	0	0
T41	0	150	0	0
T43	0	391	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T74	0	236	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426325	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	38	0	0
T24	15410	0	0	0
T31	22349	0	0	0
T40	12838	0	0	0
T41	16455	0	0	0
T43	31380	4	0	0
T63	4505	0	0	0
T65	638	0	0	0
T67	5316	0	0	0
T75	0	6	0	0
T90	485	0	0	0
T103	0	12	0	0
T147	0	7	0	0
T156	0	4	0	0
T249	0	1	0	0
T250	0	1	0	0
T251	0	2	0	0
T252	0	1	0	0
T253	438	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	18080	0	0
T8	22334	211	0	0
T9	26454	176	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	280	0	0
T24	0	64	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	194	0	0
T32	0	154	0	0
T40	0	138	0	0
T41	0	227	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T70	0	292	0	0
T74	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	356	0	0
T8	22334	4	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	5	0	0
T24	0	4	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T40	0	2	0	0
T41	0	3	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T70	0	1	0	0
T74	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8066115	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8067818	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	447	0	0
T8	22334	4	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	5	0	0
T24	0	6	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	5	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T74	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	399	0	0
T8	22334	4	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	5	0	0
T24	0	4	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T40	0	2	0	0
T41	0	3	0	0
T43	0	4	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T74	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	356	0	0
T8	22334	4	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	5	0	0
T24	0	4	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T40	0	2	0	0
T41	0	3	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T70	0	1	0	0
T74	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	356	0	0
T8	22334	4	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	5	0	0
T24	0	4	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T40	0	2	0	0
T41	0	3	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T70	0	1	0	0
T74	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	17680	0	0
T8	22334	204	0	0
T9	26454	172	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	275	0	0
T24	0	60	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	192	0	0
T32	0	151	0	0
T40	0	134	0	0
T41	0	224	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T70	0	291	0	0
T74	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	309	0	0
T8	22334	1	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	0	5	0	0
T24	0	4	0	0
T26	493	0	0	0
T27	628	0	0	0
T28	777	0	0	0
T31	0	2	0	0
T32	0	3	0	0
T41	0	3	0	0
T52	402	0	0	0
T53	407	0	0	0
T54	504	0	0	0
T70	0	1	0	0
T74	0	2	0	0
T126	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T8,T9
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T18,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T18,T8,T9
1	0	Covered	T8,T9,T12
1	1	Covered	T18,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T18,T8,T9
0	1	Covered	T18,T8,T67
1	0	Covered	T8,T40,T245

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T41
0	1	Covered	T9,T12,T41
1	0	Covered	T80,T55,T254

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T41
1	-	Covered	T9,T12,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T18,T8,T9
DetectSt	168	Covered	T18,T8,T9
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T12,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T18,T8,T9
DebounceSt->IdleSt	163	Covered	T55,T243,T76
DetectSt->IdleSt	186	Covered	T18,T8,T40
DetectSt->StableSt	191	Covered	T9,T12,T41
IdleSt->DebounceSt	148	Covered	T18,T8,T9
StableSt->IdleSt	206	Covered	T9,T12,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T18,T8,T9
0	1	Covered	T18,T8,T9
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T18,T8,T9
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T18,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T18,T8,T9
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T18,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T243,T76
DebounceSt	-	0	0	-	-	-	-	Covered	T18,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T18,T8,T40
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T41
DetectSt	-	-	-	-	0	0	-	Covered	T18,T8,T9
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T41
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T41
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	2983	0	0
CntIncr_A	9094833	104421	0	0
CntNoWrap_A	9094833	8424186	0	0
DetectStDropOut_A	9094833	417	0	0
DetectedOut_A	9094833	73264	0	0
DetectedPulseOut_A	9094833	835	0	0
DisabledIdleSt_A	9094833	7958140	0	0
DisabledNoDetection_A	9094833	7960311	0	0
EnterDebounceSt_A	9094833	1499	0	0
EnterDetectSt_A	9094833	1487	0	0
EnterStableSt_A	9094833	835	0	0
PulseIsPulse_A	9094833	835	0	0
StayInStableSt	9094833	72298	0	0
gen_high_event_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	687	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	2983	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	44	0	0
T9	0	14	0	0
T12	0	6	0	0
T18	5116	6	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	18	0	0
T41	0	20	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	30	0	0
T68	0	50	0	0
T69	0	32	0	0
T70	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	104421	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	1531	0	0
T9	0	490	0	0
T12	0	246	0	0
T18	5116	147	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	820	0	0
T41	0	670	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	808	0	0
T68	0	1525	0	0
T69	0	768	0	0
T70	0	675	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8424186	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	417	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	13	0	0
T18	5116	3	0	0
T19	521	0	0	0
T25	495	0	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T55	0	1	0	0
T67	0	15	0	0
T96	0	20	0	0
T99	0	5	0	0
T245	0	8	0	0
T247	0	21	0	0
T254	0	9	0	0
T255	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	73264	0	0
T9	26454	714	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	383	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T41	0	1215	0	0
T42	664	0	0	0
T68	0	3038	0	0
T69	0	1214	0	0
T70	0	66	0	0
T77	0	1943	0	0
T79	0	3298	0	0
T94	0	235	0	0
T127	0	615	0	0
T151	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	835	0	0
T9	26454	7	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	3	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T41	0	10	0	0
T42	664	0	0	0
T68	0	25	0	0
T69	0	16	0	0
T70	0	9	0	0
T77	0	14	0	0
T79	0	31	0	0
T94	0	5	0	0
T127	0	7	0	0
T151	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7958140	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	7960311	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1499	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	22	0	0
T9	0	7	0	0
T12	0	3	0	0
T18	5116	3	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	9	0	0
T41	0	10	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	15	0	0
T68	0	25	0	0
T69	0	16	0	0
T70	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	1487	0	0
T6	2827	0	0	0
T7	715	0	0	0
T8	22334	22	0	0
T9	0	7	0	0
T12	0	3	0	0
T18	5116	3	0	0
T19	521	0	0	0
T25	495	0	0	0
T40	0	9	0	0
T41	0	10	0	0
T49	430	0	0	0
T50	425	0	0	0
T51	423	0	0	0
T52	402	0	0	0
T67	0	15	0	0
T68	0	25	0	0
T69	0	16	0	0
T70	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	835	0	0
T9	26454	7	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	3	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T41	0	10	0	0
T42	664	0	0	0
T68	0	25	0	0
T69	0	16	0	0
T70	0	9	0	0
T77	0	14	0	0
T79	0	31	0	0
T94	0	5	0	0
T127	0	7	0	0
T151	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	835	0	0
T9	26454	7	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	3	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T41	0	10	0	0
T42	664	0	0	0
T68	0	25	0	0
T69	0	16	0	0
T70	0	9	0	0
T77	0	14	0	0
T79	0	31	0	0
T94	0	5	0	0
T127	0	7	0	0
T151	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	72298	0	0
T9	26454	703	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	379	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T41	0	1203	0	0
T42	664	0	0	0
T68	0	3012	0	0
T69	0	1194	0	0
T70	0	57	0	0
T77	0	1929	0	0
T79	0	3258	0	0
T94	0	230	0	0
T127	0	607	0	0
T151	422	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	687	0	0
T9	26454	3	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	2	0	0
T23	1827	0	0	0
T26	493	0	0	0
T28	777	0	0	0
T36	583	0	0	0
T41	0	8	0	0
T42	664	0	0	0
T68	0	24	0	0
T69	0	12	0	0
T70	0	9	0	0
T77	0	14	0	0
T79	0	22	0	0
T94	0	5	0	0
T127	0	6	0	0
T151	422	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T18,T8,T9
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T18,T8,T9
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T12,T32

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T12,T32

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T12,T32

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T12,T32
1	0	Covered	T13,T14,T18
1	1	Covered	T9,T12,T32

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T32
0	1	Covered	T74,T185,T211
1	0	Covered	T55,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T12,T32
0	1	Covered	T9,T12,T32
1	0	Covered	T77,T55,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T12,T32
1	-	Covered	T9,T12,T32

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T12,T32
DetectSt	168	Covered	T9,T12,T32
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T12,T32

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T12,T32
DebounceSt->IdleSt	163	Covered	T31,T24,T126
DetectSt->IdleSt	186	Covered	T74,T185,T55
DetectSt->StableSt	191	Covered	T9,T12,T32
IdleSt->DebounceSt	148	Covered	T9,T12,T32
StableSt->IdleSt	206	Covered	T9,T12,T32

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T12,T32
0	1	Covered	T9,T12,T32
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T12,T32
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T12,T32
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T55,T76
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T12,T32
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T24,T126
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T12,T32
DetectSt	-	-	-	-	1	-	-	Covered	T74,T185,T55
DetectSt	-	-	-	-	0	1	-	Covered	T9,T12,T32
DetectSt	-	-	-	-	0	0	-	Covered	T9,T12,T32
StableSt	-	-	-	-	-	-	1	Covered	T9,T12,T32
StableSt	-	-	-	-	-	-	0	Covered	T9,T12,T32
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9094833	833	0	0
CntIncr_A	9094833	46060	0	0
CntNoWrap_A	9094833	8426336	0	0
DetectStDropOut_A	9094833	39	0	0
DetectedOut_A	9094833	14691	0	0
DetectedPulseOut_A	9094833	350	0	0
DisabledIdleSt_A	9094833	8087735	0	0
DisabledNoDetection_A	9094833	8089440	0	0
EnterDebounceSt_A	9094833	440	0	0
EnterDetectSt_A	9094833	393	0	0
EnterStableSt_A	9094833	350	0	0
PulseIsPulse_A	9094833	350	0	0
StayInStableSt	9094833	14313	0	0
gen_high_level_sva.HighLevelEvent_A	9094833	8429564	0	0
gen_not_sticky_sva.StableStDropOut_A	9094833	316	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	833	0	0
T9	26454	8	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	2	0	0
T23	1827	0	0	0
T24	0	18	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	9	0	0
T32	0	10	0	0
T36	583	0	0	0
T41	0	4	0	0
T42	664	0	0	0
T43	0	6	0	0
T68	0	2	0	0
T69	0	8	0	0
T74	0	10	0	0
T151	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	46060	0	0
T9	26454	212	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	68	0	0
T23	1827	0	0	0
T24	0	1302	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	763	0	0
T32	0	680	0	0
T36	583	0	0	0
T41	0	156	0	0
T42	664	0	0	0
T43	0	261	0	0
T68	0	89	0	0
T69	0	252	0	0
T74	0	700	0	0
T151	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8426336	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	39	0	0
T46	2439	0	0	0
T47	656	0	0	0
T57	2176	0	0	0
T66	753	0	0	0
T74	22600	5	0	0
T101	0	3	0	0
T108	0	3	0	0
T109	522	0	0	0
T110	420	0	0	0
T111	454	0	0	0
T185	0	8	0	0
T211	0	2	0	0
T231	0	1	0	0
T256	0	9	0	0
T257	0	2	0	0
T258	0	1	0	0
T259	0	5	0	0
T260	426	0	0	0
T261	824	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	14691	0	0
T9	26454	264	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	52	0	0
T23	1827	0	0	0
T24	0	58	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	172	0	0
T32	0	22	0	0
T36	583	0	0	0
T41	0	95	0	0
T42	664	0	0	0
T43	0	17	0	0
T68	0	66	0	0
T69	0	211	0	0
T126	0	223	0	0
T151	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	350	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	1	0	0
T23	1827	0	0	0
T24	0	8	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	4	0	0
T32	0	5	0	0
T36	583	0	0	0
T41	0	2	0	0
T42	664	0	0	0
T43	0	3	0	0
T68	0	1	0	0
T69	0	4	0	0
T126	0	13	0	0
T151	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8087735	0	0
T1	703	302	0	0
T2	107379	106978	0	0
T3	823731	823330	0	0
T4	528	127	0	0
T5	1054	653	0	0
T13	2046	443	0	0
T14	2737	733	0	0
T15	522	121	0	0
T16	413	12	0	0
T17	427	26	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8089440	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	440	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	1	0	0
T23	1827	0	0	0
T24	0	10	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	5	0	0
T32	0	5	0	0
T36	583	0	0	0
T41	0	2	0	0
T42	664	0	0	0
T43	0	3	0	0
T68	0	1	0	0
T69	0	4	0	0
T74	0	5	0	0
T151	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	393	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	1	0	0
T23	1827	0	0	0
T24	0	8	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	4	0	0
T32	0	5	0	0
T36	583	0	0	0
T41	0	2	0	0
T42	664	0	0	0
T43	0	3	0	0
T68	0	1	0	0
T69	0	4	0	0
T74	0	5	0	0
T151	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	350	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	1	0	0
T23	1827	0	0	0
T24	0	8	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	4	0	0
T32	0	5	0	0
T36	583	0	0	0
T41	0	2	0	0
T42	664	0	0	0
T43	0	3	0	0
T68	0	1	0	0
T69	0	4	0	0
T126	0	13	0	0
T151	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	350	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	1	0	0
T23	1827	0	0	0
T24	0	8	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	4	0	0
T32	0	5	0	0
T36	583	0	0	0
T41	0	2	0	0
T42	664	0	0	0
T43	0	3	0	0
T68	0	1	0	0
T69	0	4	0	0
T126	0	13	0	0
T151	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	14313	0	0
T9	26454	260	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	51	0	0
T23	1827	0	0	0
T24	0	50	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	168	0	0
T32	0	17	0	0
T36	583	0	0	0
T41	0	93	0	0
T42	664	0	0	0
T43	0	14	0	0
T68	0	65	0	0
T69	0	206	0	0
T126	0	210	0	0
T151	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	8429564	0	0
T1	703	303	0	0
T2	107379	106979	0	0
T3	823731	823331	0	0
T4	528	128	0	0
T5	1054	654	0	0
T13	2046	446	0	0
T14	2737	737	0	0
T15	522	122	0	0
T16	413	13	0	0
T17	427	27	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9094833	316	0	0
T9	26454	4	0	0
T10	3835	0	0	0
T11	8504	0	0	0
T12	22990	1	0	0
T23	1827	0	0	0
T24	0	8	0	0
T26	493	0	0	0
T28	777	0	0	0
T31	0	4	0	0
T32	0	5	0	0
T36	583	0	0	0
T41	0	2	0	0
T42	664	0	0	0
T43	0	3	0	0
T68	0	1	0	0
T69	0	3	0	0
T126	0	13	0	0
T151	422	0	0	0